WO2018129907A1 - 一种集成供电系统的封装件及封装方法 - Google Patents

一种集成供电系统的封装件及封装方法 Download PDF

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Publication number
WO2018129907A1
WO2018129907A1 PCT/CN2017/095430 CN2017095430W WO2018129907A1 WO 2018129907 A1 WO2018129907 A1 WO 2018129907A1 CN 2017095430 W CN2017095430 W CN 2017095430W WO 2018129907 A1 WO2018129907 A1 WO 2018129907A1
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Prior art keywords
power supply
supply system
package
module
die
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PCT/CN2017/095430
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English (en)
French (fr)
Inventor
林章申
林正忠
何志宏
蔡奇风
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中芯长电半导体(江阴)有限公司
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Publication date
Priority claimed from CN201720028551.8U external-priority patent/CN206412351U/zh
Priority claimed from CN201710018589.1A external-priority patent/CN106531710A/zh
Application filed by 中芯长电半导体(江阴)有限公司 filed Critical 中芯长电半导体(江阴)有限公司
Priority to US15/760,558 priority Critical patent/US10636779B2/en
Publication of WO2018129907A1 publication Critical patent/WO2018129907A1/zh

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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

Definitions

  • the present invention relates to the field of semiconductor packaging technologies, and in particular, to a package and a packaging method for an integrated power supply system.
  • the power supply system converts the high voltage of the power supply into many different low voltages required for discrete devices in the system.
  • the efficiency of the power supply system determines the power loss of the down conversion, and the number of power rails determines the number of discrete voltage supplies or devices that can be supported.
  • adding more power rails requires copying more power components, such as increasing component count, increasing board size, increasing the number of boards, increasing system size, cost, and weight.
  • an object of the present invention is to provide a package and a packaging method for an integrated power supply system for solving various problems in the prior art.
  • the present invention provides a package for an integrated power supply system, including:
  • the power supply system die comprises an active module, a passive module and a rewiring layer, the active module and the passive module are packaged, the rewiring layer is located in the package forming the active module and passive On the module, an electrical connection between the active module and the passive module is implemented, and a plurality of power supply tracks that connect the bare core of the power system are provided;
  • the power system die is docked with a plurality of the power supply tracks, and is packaged and fixed on the rewiring layer;
  • the external power source directly supplies power to the power system die through the power system die.
  • the power supply system die is a high-voltage power supply system die, converting a high voltage of the external power source into a plurality of different low voltages required in the power system die, and providing a plurality of docking applications.
  • the active module includes a controller and a buck converter
  • the passive module includes a capacitor, an inductor, and an electric Resistance.
  • the active module is laterally aligned with the passive module.
  • a solder bump is disposed under the bare core of the power supply system, and a metal lead is disposed between the solder bump and the rewiring layer, and the bare core of the power supply system passes through the solder bump of the base A block is secured to the package substrate and electrical connection to the external device is achieved by the metal lead and the base solder bump.
  • the active module and the passive module are directly soldered to the rewiring layer through a microbump connection or a metal pad.
  • the power system die is connected to the rewiring layer through a plurality of micro bumps.
  • the present invention also provides a method for packaging a package of the above integrated power supply system, comprising the following steps:
  • An active module and a passive module of the power supply system die are mounted on the rewiring layer, and a metal lead is formed, and the rewiring layer electrically connects the active module and the passive module, and provides multiple interconnections The power supply track of the bare core of the electrical system;
  • the power system die is mounted on the rewiring layer to realize the docking of the power system die and the plurality of power supply tracks, and the power system die package is fixed on the rewiring layer.
  • the rewiring layer comprises: a metal wiring, a via, and a dielectric layer disposed around the metal wiring and the via, the metal wiring implementing the active module, the passive module, and An electrical connection between the metal leads and through which the interlayer connections between the plurality of metal wires are achieved.
  • the rewiring layer is provided with an under bump metal layer, and the active module, the passive module, the metal lead, and the power system die pass through the under bump metal layer and the rewiring layer Electrical connection.
  • the power supply system die is a high-voltage power supply system die, converting a high voltage of the external power source into a plurality of different low voltages required in the power system die, and providing a plurality of docking applications.
  • the active module includes a controller and a buck converter, the passive module including a capacitor, an inductor, and a resistor.
  • the active module is laterally aligned with the passive module.
  • the active module and the passive module and the rewiring layer are directly connected by a microbump or a metal pad welding.
  • each of the metal leads comprises a plurality of wires formed on the rewiring layer by wire bonding.
  • the method of packaging the active module and the passive module and the metal lead on the rewiring layer is compression molding, transfer molding, liquid sealing molding, vacuum lamination or spin coating.
  • the excess package covering the active module and the passive module and the metal lead is ground away. Molding material.
  • the power system die is connected to the rewiring layer through a plurality of micro bumps.
  • the package and the packaging method of the integrated power supply system of the present invention have the following beneficial effects:
  • the present invention provides a new method of integrating the entire power supply system into the package.
  • the power transmission efficiency is improved, and the available number of different voltage tracks is increased.
  • the invention adopts existing active components and passive components to form a 2.5D intermediate layer, and then integrates a power system die such as an ASIC into the top of the 2.5D intermediate layer to obtain a 3D stack structure, which is directly under the bare core of the power system.
  • the tight integration of the power supply system bare core solves the problems faced by existing power supply systems.
  • the power supply system bare core can provide thousands of low-voltage power supply rails and the power system directly through the micro-bumps; due to the integration of passive components, the parasitic resistance of the PCB board can be eliminated, and the power supply efficiency and response time of the power supply control can be improved. Reducing pressure drop and noise increases fidelity and reduces the amount of design required.
  • FIG. 1 is a schematic structural diagram of a package of an integrated power supply system according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a power supply principle of a package of an integrated power supply system according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing a packaging method of a package of an integrated power supply system according to an embodiment of the present invention.
  • 4a-4h are schematic diagrams showing the process flow of a package encapsulation method of an integrated power supply system according to an embodiment of the present invention.
  • the present invention proposes a new technology for integrating the entire power supply system into a package by using a three-dimensional chip stacking technique.
  • the present invention provides a package of an integrated power supply system, comprising: a power system die 601 and a power supply system die disposed under the power system die 601;
  • the power supply system die includes an active module 401, a passive module 402, and a rewiring layer 200.
  • the active module 401 and the passive module 402 are packaged, and the rewiring layer 200 is located in the package molding.
  • an electrical connection between the active module 401 and the passive module 402 is implemented, and a plurality of power supply rails that are connected to the bare core 601 of the power system are provided;
  • the power system die 601 is docked with a plurality of the power supply tracks, and is packaged and fixed on the rewiring layer 200;
  • the external power source directly supplies power to the power system die 601 through the power system die.
  • the power system die 601 may be an ASIC Die, such as a chip such as a GPU and a DRAM.
  • the power supply system die is a high voltage power supply system die, converting a high voltage of the external power source into a plurality of different low voltages required in the power system die 601, and providing A plurality of low-voltage power supply rails that are connected to the bare core of the power system.
  • the active module 401 of the power supply system die may include a controller and a buck converter
  • the passive module 402 may include a capacitor, an inductor, and a resistor.
  • the active module 401 of the power supply system die is laterally arranged with the passive component 402 such that the active module 401 and the passive module 402 are packaged in the same level to facilitate the upper rewiring layer. 200 electrical connection and layout design.
  • a solder bump 501 is disposed under the bare core of the power supply system, and a metal lead 301 is disposed between the solder bump 501 and the rewiring layer 200.
  • the base solder bump 501 secures the entire package to the package substrate 700, which can be electrically connected to the external device by the metal leads 301 connected to the base solder bumps 501.
  • the base solder bump 501 under the power supply system die may be a Ball Grid Array (BGA) solder ball.
  • BGA Ball Grid Array
  • the active module 401 and the passive module 402 and the rewiring layer 200 may be directly soldered by a micro-bumps connection or a metal pad, specifically
  • the connection method is various, for example, by ultrasonic bonding, thermocompression bonding or ordinary reflow soldering.
  • the power system die 601 and the rewiring layer 200 may be connected by a plurality of micro bumps 602, and the specific connection may be ultrasonic bonding, thermocompression bonding, or common Reflow soldering, etc.
  • the package of the integrated power supply system provided by the invention forms a 2.5D intermediate layer by using existing active components and passive components, and then integrates a power system die such as an ASIC into the top of the 2.5D intermediate layer to obtain a 3D stack structure. Therefore, the power supply system die is tightly integrated directly under the bare core of the power system.
  • the power supply mode is shown in Figure 2.
  • the external high-voltage power supply directly supplies power to the package.
  • the power supply system of the package converts the high voltage into the voltage required by the power system, and is directly supplied through the micro-bumps or bumps through multiple power supply rails. The power system is bare.
  • the bare core of the power supply system can provide thousands of low-voltage power supply tracks and the power system directly docked through the micro-bumps; due to the integration of passive components, the parasitic resistance generated by the conventional PCB board can be eliminated, and the improved
  • the power supply efficiency and response time of the power supply control improve the fidelity by reducing the voltage drop and noise, and reduce the required design margin, thereby effectively solving the problems faced by the conventional power supply system.
  • the present invention further provides a packaging method for a package of the above integrated power supply system, including the following steps. Step:
  • S1 provides a carrier
  • S3 installs an active module and a passive module of the power supply system die on the rewiring layer, and forms a metal lead, and the rewiring layer realizes electrical connection between the active module and the passive module, and provides multiple docking The power supply track of the bare core of the power system;
  • S5 forms a base solder bump connecting the metal leads
  • S7 mounts the power system die on the rewiring layer, realizes the docking of the power system die and the plurality of power supply tracks, and fixes the power system die package on the rewiring layer .
  • a carrier 101 is provided.
  • the material of the carrier 101 may be selected from one or more of glass, stainless steel, silicon, silicon oxide, metal or ceramic, or the like.
  • the carrier 101 may be of a flat type.
  • the carrier 101 may be a glass circular plate having a certain thickness.
  • an adhesion layer 1011 is formed on the surface of the carrier 101 for adhering and fixing the rewiring layer 200.
  • the rewiring layer 200 may be adhered by means of glue or tape.
  • the adhesion layer 1011 is also removed.
  • the adhesive layer 1011 may be a double-sided tape which is heated or UV-debonded.
  • one side may be UV-debonded on the other side, and the other side may be heated and de-bonded, or one side may be directly peeled off by heating and dissolving the other side.
  • the method is different.
  • the adhesion layer 1011 may also be a sacrificial layer of laser debonding. After the sacrificial layer is formed, the rewiring layer 200 may be adhered and fixed by applying glue on the sacrificial layer. When peeling off, the sacrificial layer can be removed by laser and then the glue can be removed.
  • the sacrificial layer may be deposited by CVD on the carrier 101 or may be coated with a LTHC (light to heat) material, and the glue may be removed by chemical reagents.
  • the rewiring layer 200 may include: a metal connection 201, a via hole, and a dielectric layer 202 disposed around the metal connection 201 and the via hole, where the metal connection 201 is used to implement the The electrical connection between the source module 401, the passive module 402 and the metal lead 301, and the interlayer connection between the multilayer metal wires 201 can be realized through the through holes.
  • the material of the metal connection 201 includes one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the metal wiring 201 may be a Cu wire, and the seed layer of the Cu wire may be a Ti/Cu layer.
  • the method of forming the metal wiring 201 may include one or more of electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process.
  • the through hole may be formed by laser drilling, mechanical drilling, reactive ion etching, nanoimprinting or other suitable opening. method.
  • the filling material of the through hole may be solder or Cu, and the filling method may be electrolytic plating, electroless plating, screen printing, wire bonding or other method suitable for filling a conductive material in the through hole.
  • the rewiring layer 200 may further be provided with a bump under metal layer (UBM), and the active module 401, the passive module 402, the metal lead 301, and the power system die 601 may pass through
  • UBM bump under metal layer
  • the under bump metal layer is electrically connected to the rewiring layer 200.
  • an active module 401 and a passive module 402 of the power supply system die are mounted on the rewiring layer 200, and a metal lead 301 is formed, so that the rewiring layer 200 implements the active module 401.
  • the electrical connection is made between the passive module 402 and the power supply track of the plurality of docking power system die 601.
  • the bare core of the power supply system may be a bare core of the high voltage power supply system, and the high voltage of the external power source is converted into a plurality of different low voltages required in the bare core of the power system, and the plurality of dockings are provided.
  • the active module 401 may include a controller and a buck converter.
  • the passive module 402 may include a capacitor, an inductor, and a resistor. In this embodiment, the passive module 402 includes a capacitor 4022, an inductor 4021, and a resistor ( Not shown in the figure).
  • the active module 401 and the passive component 402 such as the capacitive component 4022 and the inductive component 4021 can be laterally arranged in the same leveling layer to facilitate electrical connection and layout design of the rewiring layer 200.
  • the specific arrangement position can be designed according to actual needs. The invention is not limited thereto.
  • the active module 401 and the passive module 402 of the power supply system die when installed, the active module 401 and the passive module 402 and the rewiring layer 200 may pass through the micro bumps ( ⁇ -Bumps) soldering or metal pad soldering directly.
  • the specific connection method is various. For example, it can be ultrasonic bonding, hot pressing bonding or ordinary reflow soldering.
  • the metal lead 301 is formed on the rewiring layer 200 in order to achieve electrical connection between the power supply system die and an external device.
  • a layer of encapsulation layer containing the source module 401 and the passive module 402 may be interposed between the rewiring layer 200 and the subsequently fabricated base solder bump 501, and the rewiring layer 200 may be utilized to pass through the package.
  • the metal lead 301 of the layer is electrically connected to the base solder bump 501.
  • the metal lead 301 is a vertical column, and the metal lead 301 may be a plurality of wires. Each of the metal wires 301 may include a plurality of wires, and the wires may be wire bonded.
  • the method is formed on the rewiring layer 200, for example, a plurality of gold wires or copper wires can be used as one metal wire 301 at one place. Due to the wire bonding method by wire bonding, each time the wire is thinned, it is necessary to apply a plurality of wires as a metal wire to be connected to the subsequent base solder bump 501.
  • the active module 401, the passive module 402, and the metal lead 301 are packaged on the rewiring layer 200.
  • the excess package molding material covering the active module 401 and the passive module 402 and the metal lead 301 can be ground.
  • the package molding method may be compressed into Type, transfer molding, liquid seal molding, vacuum lamination, spin coating or other suitable method.
  • the material to be packaged may be an epoxy resin, a liquid type thermosetting epoxy resin, a plastic molding compound or the like.
  • the method of grinding may include one or more of mechanical grinding, chemical polishing, and etching.
  • a base solder bump 501 connecting the metal leads 301 is formed.
  • the base solder bump 501 may be a solder ball or the like.
  • a ball grid array (BGA) solder ball is used.
  • the package can achieve mounting on the package substrate and electrical connection to external devices through the base solder bumps 501.
  • the carrier 101 is removed, and a protective layer 502 is formed on the base solder bump 501.
  • the method of removing the carrier 101 may include one or more of mechanical grinding, chemical polishing, etching, ultraviolet peeling, mechanical peeling, or other suitable methods.
  • the adhesive layer 1011 can be removed by debonding, thereby removing the carrier 101.
  • a protective layer 502 is formed on the solder bump 501 to protect the solder bump 501 from being damaged in a subsequent process.
  • the protective layer 502 may be formed of a tape or the like.
  • the electrical system die 601 is mounted on the rewiring layer 200 to achieve docking with a plurality of the power supply tracks, and then the power system die can be grounded by underfilling.
  • a 601 package is fixed to the rewiring layer 200.
  • the power system die may be an ASIC Die.
  • the power system die 601 and the rewiring layer 200 may be connected by a plurality of micro bumps 602, and the specific connection manner may be ultrasonic bonding, thermocompression bonding, or ordinary reflow soldering.
  • the underfill may be a CUF (Capillary Underfill) or a molding underfill (MUF, Molding UnderFill).
  • the package can be mounted on a package substrate for application.
  • the present invention integrates the entire power supply system into the device package by using a three-dimensional chip stacking technology, and the power supply system die can provide several low-voltage power supply tracks and the power system directly docked through the micro bumps;
  • the component can eliminate the parasitic resistance of the PCB, improve the power supply efficiency and response time of the power supply control, improve the fidelity by reducing the voltage drop and noise, and reduce the required design margin.
  • the package and packaging method of the integrated power supply system of the invention improves the power transmission efficiency, increases the available quantity of different voltage tracks, and solves various problems faced by the existing power supply system. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Dc-Dc Converters (AREA)

Abstract

一种集成供电系统的封装件及封装方法,该封装件包括:用电系统裸芯(601)和位于用电系统裸芯下方的供电系统裸芯;供电系统裸芯包括有源模块(401)、无源模块(402)和再布线层(200),有源模块和无源模块封装成型,再布线层位于封装成型的有源模块和无源模块之上,实现有源模块和无源模块之间电连接,并提供多条对接用电系统裸芯的供电轨道;用电系统裸芯与多条供电轨道对接,并封装固定在再布线层上;外部电源直接通过供电系统裸芯向用电系统裸芯供电。通过使用三维芯片堆叠技术,提高了电力输送效率,增加了不同电压轨道的可用数量。

Description

一种集成供电系统的封装件及封装方法 技术领域
本发明涉及半导体封装技术领域,特别是涉及一种集成供电系统的封装件及封装方法。
背景技术
所有的计算和通信系统都需要供电系统。供电系统会将电源的高电压转换成系统中离散器件所需的许多不同的低电压。供电系统的效率决定了向下转换的电力损失,而供电轨数决定了可支持的离散电压供应或器件的数量。
目前的供电技术面临着如下挑战:
一、随着过程中节点的收缩,设备电压的减小,电力输送的效率会随之降低,使功率消耗更大。
二、添加更多的供电轨道需要复制更多的供电组件,如增加元件数量、增大电路板尺寸、增加电路板的层数、加大系统体积、成本和重量。
三、由于再布线层的线距、线宽的限制,需要增加封装尺寸。
因此,如何提高电力输送效率,增加不同电压轨道的可用数量,已成为本领域技术人员亟待解决的一个重要技术问题。
发明内容
鉴于以上所述现有技术,本发明的目的在于提供一种集成供电系统的封装件及封装方法,用于解决现有技术中的种种问题。
为实现上述目的及其他相关目的,本发明提供一种集成供电系统的封装件,包括:
用电系统裸芯和位于所述用电系统裸芯下方的供电系统裸芯;
其中,所述供电系统裸芯包括有源模块、无源模块和再布线层,所述有源模块和无源模块封装成型,所述再布线层位于封装成型的所述有源模块和无源模块之上,实现有源模块和无源模块之间电连接,并提供多条对接所述用电系统裸芯的供电轨道;
所述用电系统裸芯与多条所述供电轨道对接,并封装固定在所述再布线层上;
外部电源直接通过所述供电系统裸芯向所述用电系统裸芯供电。
可选地,所述供电系统裸芯为高压供电系统裸芯,将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压,并提供多条对接所述用电系统裸芯的低压供电轨道。
可选地,所述有源模块包括控制器和降压转换器,所述无源模块包括电容、电感和电 阻。
可选地,所述有源模块与所述无源模块横向排列。
可选地,所述供电系统裸芯下方设有底座焊料凸块,在所述底座焊料凸块与所述再布线层之间设有金属引线,所述供电系统裸芯通过所述底座焊料凸块固定在封装基底上并通过所述金属引线和所述底座焊料凸块实现与外部器件的电连接。
可选地,所述有源模块和所述无源模块与所述再布线层通过微凸块连接或金属焊盘直接焊接。
可选地,所述用电系统裸芯与所述再布线层通过多个微凸块连接。
为实现上述目的及其他相关目的,本发明还提供一种上述集成供电系统的封装件的封装方法,包括以下步骤:
提供一载体;
在所述载体上形成再布线层;
在所述再布线层上安装供电系统裸芯的有源模块和无源模块,并形成金属引线,所述再布线层实现有源模块和无源模块之间电连接,并提供多条对接用电系统裸芯的供电轨道;
将所述有源模块和无源模块以及所述金属引线在所述再布线层上封装成型;
形成连接所述金属引线的底座焊料凸块;
去除所述载体;
将用电系统裸芯安装在所述再布线层上,实现用电系统裸芯与多条所述供电轨道的对接,并将所述用电系统裸芯封装固定在所述再布线层上。
可选地,所述再布线层包括:金属连线、通孔以及设于所述金属连线和通孔周围的介电层,所述金属连线实现所述有源模块、无源模块和金属引线之间的电连接,并通过所述通孔实现多层金属连线之间的层间连接。
可选地,所述再布线层上设有凸块下金属层,所述有源模块、无源模块、金属引线以及用电系统裸芯通过所述凸块下金属层与所述再布线层电连接。
可选地,所述供电系统裸芯为高压供电系统裸芯,将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压,并提供多条对接所述用电系统裸芯的低压供电轨道。
可选地,所述有源模块包括控制器和降压转换器,所述无源模块包括电容、电感和电阻。
可选地,所述有源模块与所述无源模块横向排列。
可选地,所述有源模块和所述无源模块与所述再布线层通过微凸块连接或金属焊盘直接 焊接。
可选地,每根所述金属引线包含多条金属丝,所述金属丝采用引线键合的方法在所述再布线层上形成。
可选地,将所述有源模块和无源模块以及所述金属引线在所述再布线层上封装成型的方法为压缩成型、传递模塑、液封成型、真空层压或旋涂。
可选地,将所述有源模块和无源模块以及所述金属引线在所述再布线层上封装成型之后,研磨掉覆盖所述有源模块和无源模块以及所述金属引线的多余封装成型材料。
可选地,所述用电系统裸芯与所述再布线层通过多个微凸块连接。
如上所述,本发明的集成供电系统的封装件及封装方法,具有以下有益效果:
本发明提供了一种将整个供电系统集成到封装中的新方法,通过使用三维芯片堆叠技术,提高了电力输送效率,增加了不同电压轨道的可用数量。
本发明采用现有的有源元件和无源元件形成2.5D中间层,再将用电系统裸芯如ASIC集成到2.5D中间层的顶部得到3D堆栈结构,通过直接在用电系统裸芯下方紧密集成供电系统裸芯,解决了现有供电系统面临的问题。供电系统裸芯能够提供数千条低压供电轨道与用电系统通过微凸块直接对接;由于集成了无源元件,可以消除PCB板的寄生电阻,提高了供电控制的供电效率和响应时间,通过减少压降和噪声提高了保真度,减少了所需的设计余量。
附图说明
图1显示为本发明实施例提供的集成供电系统的封装件结构示意图。
图2显示为本发明实施例提供的集成供电系统的封装件的供电原理示意图。
图3显示为本发明实施例提供的集成供电系统的封装件的封装方法示意图。
图4a-4h显示为本发明实施例提供的集成供电系统的封装件的封装方法的工艺流程示意图。
元件标号说明
101       载体
1011      黏附层
200       再布线层
201       金属连线
202       介电层
301       金属引线
401       有源模块
402       无源模块
4021      电感元件
4022      电容元件
501       底座焊料凸块
502       保护层
601       用电系统裸芯
602       微凸块
700       封装基底
S1~S7    步骤
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。需说明的是,在不冲突的情况下,以下实施例及实施例中的特征可以相互组合。
需要说明的是,以下实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
为了克服现有技术中供电系统面临的问题,本发明提出了一种通过使用三维芯片堆叠技术将整个供电系统集成到封装中的新技术。请参阅图1,本发明提供一种集成供电系统的封装件,包括:用电系统裸芯601和位于所述用电系统裸芯601下方的供电系统裸芯;
其中,所述供电系统裸芯包括有源模块401、无源模块402和再布线层200,所述有源模块401和无源模块402封装成型,所述再布线层200位于封装成型的所述有源模块401和无源模块402之上,实现有源模块401和无源模块402之间电连接,并提供多条对接所述用电系统裸芯601的供电轨道;
所述用电系统裸芯601与多条所述供电轨道对接,并封装固定在所述再布线层200上;
外部电源直接通过所述供电系统裸芯向所述用电系统裸芯601供电。
在本发明的一些实施例中,所述用电系统裸芯601可以为专用集成电路裸芯(ASIC Die),例如可以是GPU和DRAM等芯片。
在本发明的一些实施例中,所述供电系统裸芯为高压供电系统裸芯,将外部电源的高电压转换成所述用电系统裸芯601中需要的多个不同的低电压,并提供多条对接所述用电系统裸芯的低压供电轨道。具体地,所述供电系统裸芯的有源模块401可以包括控制器和降压转换器,所述无源模块402可以包括电容、电感和电阻。
在本发明的一些实施例中,所述供电系统裸芯的有源模块401与被动元件402横向排列,这样有源模块401与无源模块402封装在同一平层中,便于上层的再布线层200的电连接和布图设计。
在本发明的一些实施例中,所述供电系统裸芯下方设有底座焊料凸块501,在所述底座焊料凸块501与所述再布线层200之间设有金属引线301,可以通过所述底座焊料凸块501将整个封装件固定在封装基底700上,所述供电系统裸芯可以通过与所述底座焊料凸块501连接的所述金属引线301实现与外部器件的电连接。具体地,所述供电系统裸芯下方的所述底座焊料凸块501可以为球状引脚栅格阵列(Ball Grid Array,BGA)焊球。
在本发明的一些实施例中,所述有源模块401和所述无源模块402与所述再布线层200之间可以通过微凸块(μ-Bumps)连接或金属焊盘直接焊接,具体的连接方式是多样的,例如,可以通过超声键合、热压键合或普通的回流焊等方法。
在本发明的一些实施例中,所述用电系统裸芯601与所述再布线层200可以通过多个微凸块602连接,具体的连接方式可以是超声键合、热压键合或普通的回流焊等。
本发明提供的集成供电系统的封装件,采用现有的有源元件和无源元件形成2.5D中间层,再将用电系统裸芯如ASIC集成到2.5D中间层的顶部得到3D堆栈结构,从而直接在用电系统裸芯下方紧密集成供电系统裸芯。供电方式如图2所示,外部高压电源直接向封装件供电,封装件的供电系统将高电压转化为符合用电系统需要的电压,并通过多条供电轨道通过微凸块或凸块直接供给用电系统裸芯。采用本发明的技术方案,供电系统裸芯能够提供数千条低压供电轨道与用电系统通过微凸块直接对接;由于集成了无源元件,可以消除采用传统PCB板产生的寄生电阻,提高了供电控制的供电效率和响应时间,通过减少压降和噪声提高了保真度,减少了所需的设计余量,从而可有效的解决传统供电系统面临的问题。
请参阅图3,本发明还提供一种上述集成供电系统的封装件的封装方法,包括以下步 骤:
S1提供一载体;
S2在所述载体上形成再布线层;
S3在所述再布线层上安装供电系统裸芯的有源模块和无源模块,并形成金属引线,所述再布线层实现有源模块和无源模块之间电连接,并提供多条对接用电系统裸芯的供电轨道;
S4将所述有源模块和无源模块以及所述金属引线在所述再布线层上封装成型;
S5形成连接所述金属引线的底座焊料凸块;
S6去除所述载体;
S7将用电系统裸芯安装在所述再布线层上,实现用电系统裸芯与多条所述供电轨道的对接,并将所述用电系统裸芯封装固定在所述再布线层上。
下面通过具体实例来详细说明上述封装方法。
首先,如图4a所示,提供一载体101。所述载体101的材料可以选自玻璃、不锈钢、硅、氧化硅、金属或陶瓷中的一种或多种,或其他类似物。所述载体101可以为平板型。例如,所述载体101可以为具有一定厚度的玻璃圆形平板。本实施例中,在所述载体101表面形成黏附层1011用于黏附固定所述再布线层200。具体地,可以采用胶水或胶带的方式黏附所述再布线层200。后续去除所述载体101时,黏附层1011也一并去除。例如,黏附层1011可以是采用加热或UV解胶的双面胶带,剥离时可以一面采用UV解胶另一面采用加热解胶,或者一面采用加热解胶另一面直接撕去,两面胶带解除粘性的方法不同。或者,黏附层1011也可以是镭射解胶的牺牲层,形成这层牺牲层后,在牺牲层上涂胶水可以黏附固定所述再布线层200。剥离时,可采用镭射去除牺牲层,然后再清除胶水。牺牲层可以在载体101上采用CVD沉积,也可以涂覆LTHC(light to heat)材料得到,胶水可以采用化学试剂清除。
然后,如图4b所示,在所述载体101上形成再布线层200。具体地,所述再布线层200可以包括:金属连线201、通孔以及设于所述金属连线201和通孔周围的介电层202,所述金属连线201用于实现所述有源模块401、无源模块402和金属引线301之间的电连接,并可以通过所述通孔实现多层金属连线201之间的层间连接。其中,金属连线201的材料包括Cu、Al、Ag、Au、Sn、Ni、Ti、Ta中的一种或多种,或其他适合的导电金属材料。例如,金属连线201可以为Cu线,制作Cu线的种子层可以为Ti/Cu层。形成所述金属连线201的方法可以包括电解镀、化学镀、丝网印刷中的一种或多种,或其他适合的金属沉积工艺。所述通孔的形成方法可以为激光钻孔、机械钻孔、反应离子刻蚀、纳米压印或其他适合的开孔 方法。所述通孔的填充材料可以为焊料或Cu,填充方法可以为电解镀、化学镀、丝网印刷、引线键合或其他适合在通孔中填充导电材料的方法。
本实施例中,所述再布线层200上还可以设有凸块下金属层(UBM),所述有源模块401、无源模块402、金属引线301以及用电系统裸芯601可以通过所述凸块下金属层与所述再布线层200电连接。
随后,如图4c所示,在所述再布线层200上安装供电系统裸芯的有源模块401和无源模块402,并形成金属引线301,使所述再布线层200实现有源模块401和无源模块402之间电连接,并提供多条对接用电系统裸芯601的供电轨道。
本实施例中,供电系统裸芯可以为高压供电系统裸芯,将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压,并提供多条对接所述用电系统裸芯的低压供电轨道。所述有源模块401可以包括控制器和降压转换器,所述无源模块402可以包括电容、电感和电阻,本实施例中,无源模块402包括电容元件4022、电感元件4021和电阻(图中未示出)等。有源模块401与电容元件4022、电感元件4021等无源模块402可以横向地排列在同一平层中,便于再布线层200的电连接和布图设计,具体排布的位置可以根据实际需要进行设计,本发明对此不作限制。
本实施例中,安装供电系统裸芯的有源模块401和无源模块402时,所述有源模块401和所述无源模块402与所述再布线层200之间可以通过微凸块(μ-Bumps)连接或金属焊盘直接焊接,具体的连接方式是多样的,例如,可以通过超声键合、热压键合或普通的回流焊等方法。
在所述再布线层200上形成金属引线301是为了实现所述供电系统裸芯与外部器件的电连接。在所述再布线层200与后续制作的底座焊料凸块501之间将会隔着一层含有源模块401和无源模块402的封装层,所述再布线层200可利用穿过这层封装层的金属引线301实现与底座焊料凸块501的电连接。在本实施例中,所述金属引线301为竖直柱状,所述金属引线301可以为多根,每根金属引线301可以包含多条金属丝,这些金属丝可采用引线键合(wire bond)的方法在所述再布线层200上形成,例如可以在一处打多条金丝或铜丝作为一根金属引线301。由于采取引线键合的打线方法,每次打的金属丝较细,因此需要打多条金属丝作为一根金属引线以便与后续的底座焊料凸块501连接。
接下来,如图4d所示,将所述有源模块401、无源模块402以及所述金属引线301在所述再布线层200上封装成型。封装成型之后,可以研磨掉覆盖所述有源模块401和无源模块402以及所述金属引线301的多余封装成型材料。具体地,所述封装成型方法可以为压缩成 型、传递模塑、液封成型、真空层压、旋涂或其他适合的方法。封装成型的材料可以为环氧类树脂、液体型热固性环氧树脂、塑料成型化合物或类似物。研磨的方法可以包括机械研磨、化学抛光、刻蚀中的一种或多种。
然后,如图4e所示,形成连接所述金属引线301的底座焊料凸块501。本实施例中,所述底座焊料凸块501可以是焊锡球等,本实施例采用球状引脚栅格阵列(Ball Grid Array,BGA)焊球。所述封装件通过所述底座焊料凸块501可以实现在封装基底上的固定以及与外部器件的电连接。
接着,如图4f所示,去除所述载体101,并在所述底座焊料凸块501上形成保护层502。具体地,去除所述载体101的方法可以包括机械研磨、化学抛光、刻蚀、紫外线剥离、机械剥离中的一种或多种,或其他适合的方法。本实施例中,可以通过解胶的方式去除黏附层1011,从而去除所述载体101。本实施例中,在所述底座焊料凸块501上先形成一层保护层502可以保护所述底座焊料凸块501在后续工艺中不被破坏。所述保护层502可以采用胶带等类似物。
接下来,如图4g所示,将用电系统裸芯601安装在所述再布线层200上,实现与多条所述供电轨道的对接,然后可以通过底部填充将所述用电系统裸芯601封装固定在所述再布线层200上。本实施例中,所述用电系统裸芯可以为专用集成电路裸芯(ASIC Die)。具体地,所述用电系统裸芯601与所述再布线层200可以通过多个微凸块602连接,具体的连接方式可以是超声键合、热压键合或普通的回流焊等。所述底部填充可以为毛细管底部填充(CUF,Capillary Underfill)或成型材料底部填充(MUF,Molding UnderFill)。最后,如图4h所示,去除保护层502后即可将所述封装件安装到封装基底上应用。
综上所述,本发明通过使用三维芯片堆叠技术将整个供电系统集成到器件封装中,供电系统裸芯能够提供数条低压供电轨道与用电系统通过微凸块直接对接;由于集成了无源元件,可以消除PCB板的寄生电阻,提高了供电控制的供电效率和响应时间,通过减少压降和噪声提高了保真度,减少了所需的设计余量。本发明的集成供电系统的封装件及封装方法提高了电力输送效率,增加了不同电压轨道的可用数量,解决了现有供电系统面临的多种问题。所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。

Claims (18)

  1. 一种集成供电系统的封装件,其特征在于,包括:
    用电系统裸芯和位于所述用电系统裸芯下方的供电系统裸芯;
    其中,所述供电系统裸芯包括有源模块、无源模块和再布线层,所述有源模块和无源模块封装成型,所述再布线层位于封装成型的所述有源模块和无源模块之上,实现有源模块和无源模块之间电连接,并提供多条对接所述用电系统裸芯的供电轨道;
    所述用电系统裸芯与多条所述供电轨道对接,并封装固定在所述再布线层上;
    外部电源直接通过所述供电系统裸芯向所述用电系统裸芯供电。
  2. 根据权利要求1所述的集成供电系统的封装件,其特征在于:所述供电系统裸芯为高压供电系统裸芯,将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压,并提供多条对接所述用电系统裸芯的低压供电轨道。
  3. 根据权利要求1所述的集成供电系统的封装件,其特征在于:所述有源模块包括控制器和降压转换器,所述无源模块包括电容、电感和电阻。
  4. 根据权利要求1所述的集成供电系统的封装件,其特征在于:所述有源模块与所述无源模块横向排列。
  5. 根据权利要求1所述的集成供电系统的封装件,其特征在于:所述供电系统裸芯下方设有底座焊料凸块,在所述底座焊料凸块与所述再布线层之间设有金属引线,所述供电系统裸芯通过所述底座焊料凸块固定在封装基底上并通过所述金属引线和所述底座焊料凸块实现与外部器件的电连接。
  6. 根据权利要求1所述的集成供电系统的封装件,其特征在于:所述有源模块和所述无源模块与所述再布线层通过微凸块连接或金属焊盘直接焊接。
  7. 根据权利要求1所述的集成供电系统的封装件,其特征在于:所述用电系统裸芯与所述再布线层通过多个微凸块连接。
  8. 一种根据权利要求1-7中任一项所述的集成供电系统的封装件的封装方法,其特征在于,
    包括以下步骤:
    提供一载体;
    在所述载体上形成再布线层;
    在所述再布线层上安装供电系统裸芯的有源模块和无源模块,并形成金属引线,所述再布线层实现有源模块和无源模块之间电连接,并提供多条对接用电系统裸芯的供电轨道;
    将所述有源模块和无源模块以及所述金属引线在所述再布线层上封装成型;
    形成连接所述金属引线的底座焊料凸块;
    去除所述载体;
    将用电系统裸芯安装在所述再布线层上,实现用电系统裸芯与多条所述供电轨道的对接,并将所述用电系统裸芯封装固定在所述再布线层上。
  9. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:所述再布线层包括:金属连线、通孔以及设于所述金属连线和通孔周围的介电层,所述金属连线实现所述有源模块、无源模块和金属引线之间的电连接,并通过所述通孔实现多层金属连线之间的层间连接。
  10. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:所述再布线层上设有凸块下金属层,所述有源模块、无源模块、金属引线以及用电系统裸芯通过所述凸块下金属层与所述再布线层电连接。
  11. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:所述供电系统裸芯为高压供电系统裸芯,将外部电源的高电压转换成所述用电系统裸芯中需要的多个不同的低电压,并提供多条对接所述用电系统裸芯的低压供电轨道。
  12. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:所述有源模块包括控制器和降压转换器,所述无源模块包括电容、电感和电阻。
  13. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:所述有源模块与所述无源模块横向排列。
  14. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:所述有源模块和所述无源模块与所述再布线层通过微凸块连接或金属焊盘直接焊接。
  15. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:每根所述金属引线包含多条金属丝,所述金属丝采用引线键合的方法在所述再布线层上形成。
  16. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:将所述有源模块和无源模块以及所述金属引线在所述再布线层上封装成型的方法为压缩成型、传递模塑、液封成型、真空层压或旋涂。
  17. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:将所述有源模块和无源模块以及所述金属引线在所述再布线层上封装成型之后,研磨掉覆盖所述有源模块和无源模块以及所述金属引线的多余封装成型材料。
  18. 根据权利要求8所述的集成供电系统的封装件的封装方法,其特征在于:所述用电系统裸芯与所述再布线层通过多个微凸块连接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024066603A1 (zh) * 2022-09-28 2024-04-04 华为技术有限公司 芯片封装结构和电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859762A (zh) * 2009-04-07 2010-10-13 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN105428260A (zh) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构的制造方法
CN106531710A (zh) * 2017-01-11 2017-03-22 中芯长电半导体(江阴)有限公司 一种集成供电系统的封装件及封装方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11168185A (ja) * 1997-12-03 1999-06-22 Rohm Co Ltd 積層基板体および半導体装置
JP6224274B2 (ja) * 2014-12-24 2017-11-01 インテル コーポレイション スタックされた集積回路パッケージに集積されたパッシブコンポーネント
US10236209B2 (en) * 2014-12-24 2019-03-19 Intel Corporation Passive components in vias in a stacked integrated circuit package
US9935076B1 (en) * 2015-09-30 2018-04-03 Apple Inc. Structure and method for fabricating a computing system with an integrated voltage regulator module
US9627365B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US10170448B2 (en) * 2016-12-07 2019-01-01 Micron Technology, Inc. Apparatus and method of power transmission sensing for stacked devices
CN109103167B (zh) * 2017-06-20 2020-11-03 晟碟半导体(上海)有限公司 用于存储器装置的异构性扇出结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859762A (zh) * 2009-04-07 2010-10-13 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN105428260A (zh) * 2015-12-22 2016-03-23 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构的制造方法
CN106531710A (zh) * 2017-01-11 2017-03-22 中芯长电半导体(江阴)有限公司 一种集成供电系统的封装件及封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024066603A1 (zh) * 2022-09-28 2024-04-04 华为技术有限公司 芯片封装结构和电子设备

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