CN106910732A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN106910732A
CN106910732A CN201610810326.XA CN201610810326A CN106910732A CN 106910732 A CN106910732 A CN 106910732A CN 201610810326 A CN201610810326 A CN 201610810326A CN 106910732 A CN106910732 A CN 106910732A
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CN
China
Prior art keywords
semiconductor
wire
conductive structure
pedestal
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610810326.XA
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English (en)
Inventor
周哲雅
许文松
陈南诚
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MediaTek Inc
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MediaTek Inc
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Publication date
Priority claimed from US15/238,454 external-priority patent/US10991669B2/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN106910732A publication Critical patent/CN106910732A/zh
Pending legal-status Critical Current

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Abstract

本发明实施例公开了一种半导体封装。其包括：基座；多个第一导电结构；以及半导体元件，通过该多个第一导电结构接合至该基座；其中，该半导体元件包括：载体基底；多个第二导电结构；以及第一半导体主体，通过该多个第二导电结构接合至该载体基底；其中，该多个第一导电结构和该多个第二导电结构分别设置在该载体基底的两相对表面上；其中，该载体基底及该基座均为该第一半导体主体的扇出结构。本发明实施例的半导体封装可以具有较低的制造成本。

Description

半导体封装
技术领域
本发明涉及半导体技术领域，尤其涉及一种使用倒装芯片技术的半导体封装。
背景技术
为了确保电子产品或通信设备(诸如可穿戴式设备)的小型化和多功能性，会要求半导体封装具有小尺寸，以支持多针连接、高速和高功能。输入/输出(I/O)引脚数的增加再加上对高性能集成电路(IC)的需求增加，导致了倒装芯片封装的发展。倒装芯片技术使用芯片/晶粒上的凸块以与封装基板互连，诸如印刷电路板(Printed Circuit Board，PCB)。倒置芯片并正面向下地接合至封装基板。倒装芯片技术实现了与设备的高密度互连。
但是，随着芯片尺寸变小，相应地要求PCB的线宽和间距进一步缩小。如此，PCB的制造过程变得更加困难和复杂。而且PCB需要由适合微小布局的特殊材料制成。相应地，难以降低PCB及含该PCB的半导体封装的制造成本。
因此，期望一种使用倒装芯片技术并且具有更低制造成本的新的半导体封装。
发明内容
有鉴于此，本发明实施例提供了一种半导体封装，可以降低其制造成本。
本发明实施例提供了一种半导体封装，包括：基座；多个第一导电结构；以及半导体元件，通过该多个第一导电结构接合至该基座；其中，该半导体元件包括：载体基底；多个第二导电结构；以及第一半导体主体，通过该多个第二导电结构接合至该载体基底；其中，该多个第一导电结构和该多个第二导电结构分别设置在该载体基底的两相对表面上；其中，该载体基底及该基座均为该第一半导体主体的扇出结构。
其中，进一步包括：多个第三导电结构，接合在该基座上，并且该多个第一导电结构和该多个第三导电结构分别设置在该基座的两相对表面上。
其中，该多个第一导电结构的尺寸大于该多个第二导电结构的尺寸且小于该多个第三导电结构的尺寸。
其中，该多个第一导电结构之间的间距大于该多个第二导电结构之间的间距，且小于该多个第三导电结构之间的间距。
其中，该多个第三导电结构之间的间距与该多个第二导电结构之间的间距之比值介于5～9之间，并且该多个第三导电结构之间的间距与该多个第一导电结构之间的间距之比值大于1且小于等于3。
其中，该半导体元件进一步包括：模塑料，设置在该载体基底上，并且围绕该第一半导体主体及该多个第二导电结构。
其中，进一步包括：底胶填充材质，设置在该基座上，并且围绕该半导体元件及该多个第一导电结构，以及填充该半导体元件与该基座之间的间隙。
其中，该载体基底的宽度大于该第一半导体主体的宽度，且小于该基座的宽度。
其中，该第一半导体主体为半导体晶粒。
其中，该半导体元件还包括：第二半导体主体，与该第一半导体主体并排设置在该载体基底上或者堆叠在该第一半导体主体上。
其中，该第一半导体主体使用倒装芯片方式接合至该载体基底。
其中，当该第二半导体主体与该第一半导体主体并排设置在该载体基底上时，该第二半导体主体使用倒装芯片或者线接合方式接合至该载体基底。
其中，当该第二半导体主体堆叠在该第一半导体主体上时，该第二半导体主体使用线接合方式接合至该载体基底。
其中，进一步包括：散热基座，通过黏合层附着至该基座，并且覆盖该半导体元件。
其中，进一步包括：散热界面材料，位于该散热基座与该半导体元件之间。
其中，该载体基底包括：导线，该第二导电结构直接接合在该导线上。
其中，该导线为细长形的。
其中，该导线用于携带输入/输出信号、接地信号或电源信号穿过该载体基底的至少一部分。
其中，该导线的顶面位于该载体基底面向该半导体主体的表面的上方、下方或者对齐。
其中，该导线的宽度小于该第一半导体主体上的连接至该第二导电结构的接垫的宽度。
其中，该导线的形状不同于该第一半导体主体上的连接至该第二导电结构的接垫的形状。
其中，该第二导电结构包括：焊锡盖层，直接接触该导线。
其中，该第二导电结构包括：宽度大于该导线的宽度的铜层和/或宽度大于该导线的宽度的焊锡盖层。
本发明实施例的有益效果是：
本发明实施例，半导体主体(例如晶粒)并非直接接合至基座，而先通过载体基底(作为扇出结构)来使得第一导电结构之间的间距扩大，然后再通过第一导电结构接合至基座，从而使得基座可以无需采用昂贵的ABF1-2-1基座，而可以采用普通的廉价基座，从而降低了半导体封装的制造成本。
附图说明
通过阅读接下来的详细描述及参考附图所做的示例可以更容易地理解本发明，其中：
图1-4为本发明不同实施例的半导体封装的剖面示意图；
图5A-5E为本发明实施例的形成半导体封装的过程的各阶段的剖面示意图；
图6A-6E为本发明实施例的形成半导体封装的过程的各阶段的剖面示意图；
图7A为根据本发明一些实施例的半导体封装的部分透视图；
图7B和7C为根据本发明一些实施例的半导体封装的部分的剖面示意图；
图8A～8D为本发明不同实施例的半导体封装的剖面示意图。
具体实施方式
以下描述仅是出于说明本发明一般原理的目的，而不应视为限制。本发明的范围可参考所附的权利要求来确定。
参考特定实施例与参考确定的附图来描述本发明，但是本发明不限制于此，并且本发明仅由权利要求来限定。描述的附图仅是示意图而非限制。在附图中，出于说明目的而夸大了某些元件的尺寸，并且某些元件的尺寸并非按比例绘制。图中的尺寸和相对尺寸不对应本发明实践中的真实尺寸。
图1-4为本发明不同实施例的半导体封装的剖面示意图。在一些实施例中，上述半导体封装可为倒装芯片封装(flip chip package)，该倒装芯片封装使用导电结构来将半导体元件(semiconductor device)连接至基座。可替换地，上述半导体封装可为使用接合线技术的封装，以将半导体元件连接至基座。
例如，导电结构可为焊料凸块、铜柱凸块或者其他合适的导电结构。上述的半导体元件可以为半导体晶粒/芯片或者含有半导体晶粒的半导体封装。该基座可以为PCB或者另一合适的基底。
图1显示本发明实施例的半导体封装500a的剖面示意图。请参考图1，上述半导体封装500a可包括基座200，上述基座200具有元件贴附面(device attach surface)214。在本发明实施例中，基座200，例如为印刷电路板(PCB)，可由聚丙烯(polypropylene，PP)或者另一合适的材料来形成。并且注意基座200可为单一层(single layer)结构或多层(multilayer)结构。
多条导线(conductive trace)202a，内嵌于基座200中。在本发明实施例中，导线202a可包括信号线段或接地线段，上述信号线段或接地线段可用于半导体元件300的输入/输出(input/output，I/O)连接，其中半导体元件300直接安装(mounted)至基座200上。换言之，导线202a携带输入/输出(I/O)信号、接地(ground)信号或电源(power)信号穿过基座200的至少一部分。因此，每条导线202a的至少一部分作为基座200的外部连接区。
在一些实施例中，导线202a的宽度W1设计为大于5μm(微米)，诸如介于10μm～20μm之间。然而，应注意导线202a的宽度W1并无限制。对于不同的设计，如果有需要的话，导线的宽度W1可以小于5μm或者为另一合适的值。在一些实施例中，导线202a的长度大于其宽度。因此，导线202a为细长的线(elongated lines)或者为条纹(stripe)。
相反地，接垫结构则又短又厚(stout)。例如，接垫结构的宽度大约为100μm或者大于100μm。接垫结构一般为矩形、椭圆形或者多边形。相应地，于同一预定大小的区域内，接垫结构的面积大于导线202a的面积。另外，导线202a的形状远不同于接垫结构的形状。应注意导线202a和接垫结构在形状和面积上具有本质区别。
更具体地，由于导线202a为细长的并且其宽度远小于接垫结构的宽度，因此导线202a比接垫结构承受更小的接合应力。由于导线202a比接垫结构更窄，因此在相同区域内，导线202a比接垫结构允许更密集的间距及更多的线路。相反地，导线202a比接垫结构具有更高的I/O密度。每片IC的更多的I/O连接能够提供更好的设备性能。更小和更靠近的间隔连接符合小型化的要求。
另外，导线202a比接垫结构，能提供基座200的更好的布局密度，从而降低封装尺寸和基座200的层数(如2～4层导电层即可，而不是6层)，进而降低了制造成本。应注意导线202a在应力承受、I/O密度和制造成本上，与接垫结构具有本质不同。
半导体元件300可透过接合工艺用面向基座200的主动表面(active surface)而固接于基座200的元件贴附面214上。在本发明实施例中，半导体元件300可包括晶粒(die)、无源元件(passive component)、封装(package)或晶圆级封装(wafer level package)。在本实施例中，半导体元件300可为倒装芯片封装(flip chip package)。半导体元件300的电路设置于上述主动表面上，且导电接垫(conductive pad)304设置于上述电路的顶部上。上述半导体元件300的上述电路藉由设置于半导体元件300的主动表面上的多个导电结构222互连至基座200的电路。本发明实施例的信号流向例如可以为：来自半导体元件300的信号经过导电结构222直接传递至导线202a而不通过接垫来传递至导线，然后导线202a携带该信号穿过该基座200的至少部分。
如图1所示，半导体元件300可包括半导体主体301，位于上述半导体主体301上(overlying)的导电接垫304，以及覆盖导电接垫304的绝缘层302。在本实施例中，半导体主体301可包括但并非限制于半导体基板、形成于上述半导体基板的主要表面(mainsurface)上的电路元件、层间介电层(Inter-Layer Dielectric，ILD)和互连结构。在本发明实施例中，上述互连结构可包括多个金属层、与金属层交错堆叠(laminate)的多个介电层，以及穿过位于半导体主体301上的该些介电层的多个介层孔插塞(via)。半导体主体301也可以称为半导体晶粒。
上述导电接垫304可包括上述互连结构的上述金属层的最上层金属层。在一些实施例中，导电接垫304可以包括但不限于铝、铜或者他们的合金。在一些实施例中，绝缘层302可以为单一层结构或多层结构。在一些实施例中，绝缘层302可包括但并非限制于氮化硅、氧化硅、氮氧化硅、聚酰亚胺(polyimide)或上述任意组合。并且，绝缘层302可具有诸如应力缓冲和绝缘等功能。可于绝缘层302中形成多个开口。每一个开口暴露出导电接垫304的至少一部分。导电接垫304在形状、面积、应力耐受、I/O密度和制造成本方面不同于导线202a。
在一些实施例中，导电结构222可包括导电凸块结构(例如铜凸块结构或焊锡凸块结构)、导线结构，或导电膏结构(conductive paste structure)。在一些实施例中，导电结构222可为由金属堆叠构成的铜凸块结构，上述金属堆叠包括凸块下金属层(under bumpmetallurgy(UBM)layer)306、铜层216(例如电镀铜层)、导电缓冲层218和焊锡盖层(soldercap)220。但是，应注意图1所示的导电结构222仅为示例而不是对本发明的限制。
在一些实施例中，可利用例如溅镀(sputtering)法或电镀(plating)法的沉积工艺以及后续的非等向性蚀刻工艺(anisotropic etching process)，于开口中暴露出来的导电接垫304上形成凸块下金属层(UBM layer)306。上述非等向性蚀刻工艺于形成导电柱状物之后进行。凸块下金属层306也可延伸于绝缘层302的顶面上。在本实施例中，凸块下金属层306可包括钛、铜或上述组合。
铜层216(例如电镀铜层)，可形成于凸块下金属层306上。铜层216可以帮助增强导电结构222的机械强度。绝缘层302中的开口可利用铜层216和凸块下金属层306来填充。且位于绝缘层302中的开口内的铜层216和凸块下金属层306可形成导电结构222的集成插塞(integral plug)。铜层216的形成位置(图未显示)可利用干膜光阻(dry filmphotoresist)图型(pattern)或液态光阻(liquid photoresist)图型来定义。
可透过电镀焊锡和图案化光阻层或透过网印(screen printing)工艺和后续的回焊工艺于铜层216上形成焊锡盖层220。在一些实施例中，导电结构222(例如为导电柱状结构)可作为导电接垫304的焊点(solder joint)，而导电接垫304用于传输形成于其上的半导体元件300的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号。
可利用电镀法于铜层216和焊锡盖层220之间形成导电缓冲层218。上述导电缓冲层218可作为形成于其上的焊锡盖层220的种晶层(seed layer)、黏着层(adhesion layer)以及阻障层(barrier layer)。上述的导电缓冲层218可以包括：镍(Ni)或者另一合适的材料。
在本发明实施例中，可于半导体元件300和基座200之间的间隙中导入底胶填充材质230。该底胶填充材质230围绕该导电结构222。部分的底胶填充材质230可以直接接触基座200的元件贴附面214。当导线202a从基座200的元件贴附面214凹进时，部分的底胶填充材质230可以延伸进入基座200中。在本发明实施例中，底胶填充材质或底胶230可包括毛细填充胶(capillary underfill，CUF)、成型底部填充胶(molded underfill，MUF)、非导电性绝缘胶(nonconductive paste，NCP)、非导电性绝缘膜(nonconductive film，NCF)或上述任意组合。
在本发明实施例中，导线具有顶面，上述顶面可位于上述基座的表面的上方、下方或对齐上述基座的表面，以改善高密度半导体封装的绕线能力。如图1所示，导线202a的顶面212a设置于上述基座200的元件贴附面214的下方。意即导线202a的底面206a和导线202a的至少一部分侧壁204a设计连接至或者直接接触基座200。在一些实施例中，导电结构222的焊锡盖层220设置为直接触基座200的元件贴附面214及导线202a的顶面212a。由于导线202a的顶面凹陷于基座200的元件贴附面214内，因此导电结构222的焊锡盖层220延伸进入基座200。增加凸块接合至导线的空间(bump-to-trace space)，且有效地避免凸块接合至导线的桥接问题(the problem of bump-to-trace bridging)。
图2显示本发明另一实施例的半导体封装500b的剖面示意图。上述附图中的各元件如有与图1所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。在本实施例中，半导体封装500b包括：内嵌于基座200中的导线202b。上述的导线202b可具有顶面212b，上述顶面212b设计为对齐于基座200的元件贴附面214，以改善用于高密度半导体封装的绕线能力。意即导线202b的底面206b和侧壁204b设计为完全连接至基座200。因此，导电结构222的焊锡盖层220设置于基座200的元件贴附面214上，且仅直接接触导线202b的顶面212b。
图3显示本发明又一实施例的半导体封装500c的剖面示意图。上述附图中的各元件如有与图1和2所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。在本实施例中，半导体封装500c包括：内嵌于基座200中的导线202c。上述的导线202c可具有顶面212c，其设计为位于基座200的元件贴附面214的上方，以改善用于高密度半导体封装的绕线能力。意即导线202c的底面206c和导线202c的仅一部分侧壁204c设计为连接至或者直接接触基座200。在本实施例中，导电结构222的焊锡盖层220设置于基座200的元件贴附面214上，且包裹导线202c的顶面212c和导线202c的部分侧壁204c。
如图1～3所示，基座200包括：单层结构。可替换地，基座可以包括：多层结构。但是，本发明的实施例不限制于此。在其他的一些实施例中，基座200可以包括：多层结构。
图4显示本发明又另一实施例的半导体封装500d的剖面示意图。上述附图中的各元件如有与图1-3所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。在本发明一些实施例中，半导体封装500d包括：内嵌于基座200中的导线202d。上述的导线202d可具有顶面212d，上述顶面212d设计对齐于基座200的元件贴附面214，以改善用于高密度半导体封装的绕线能力。意即导线202d的底面206d和侧壁204d设计为连接至基座200。并且，具有开口210的绝缘层208设置于基座200上。上述绝缘层208设置于基座200的元件贴附面214及导线202d的上方。在本实施例中，基座200和绝缘层208可一起视为多层基座。
如图4所示，导线202d从开口210中暴露出来。因此，导电结构222的焊锡盖层220形成于绝缘层208上并且延伸进入开口210。如此，焊锡盖层220通过开口210直接接触导线202d的顶面212d。应注意绝缘层208不需对齐于导线202d的侧壁204d。可替换地，绝缘层208可设计为位于如图4所示的导线202d的侧壁204d的外侧或内侧。
图5A-5E为本发明实施例的半导体封装的基座的制造方法的剖面示意图。图5A-5E中的各元件如有与图1-4所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。图5A～5E示出了制造两个基座200c和200d的方法，其中基座200c和200d类似于半导体封装500a、500b、500c和500d中的基座200。在一些实施例中，制造基座200c和200d的方法也可称为双侧基座工艺(double-sided base fabricating process)。
如图5A所示，提供载板400，上述载板400具有导电种晶层(conductive seedlayer)402a和导电种晶层402b。在本发明实施例中，载板400可包括FR4环氧玻璃(FR4glassepoxy)或不锈钢(stainless steel)或者另一合适的材料。并且，导电种晶层402a和导电种晶层402b分别位于载体400的顶面401和底面403上。导电种晶层402a和导电种晶层402b作为种晶层以用于后续形成的位于上述载板400的顶面401和底面403上的基座的互连导线。在本发明一实施例中，导电种晶层402a和导电种晶层402b可包括铜或者另一合适的材料。
接着，如图5B所示，分别于载板400的顶面401和底面403上形成第一导线404a和404b。第一导线404a和404b的底部分别连接至导电种晶层402a和402b的顶部。在本发明实施例中，可利用电镀工艺(plating process)和非等向性蚀刻工艺形成第一导线404a和404b。上述电镀工艺和非等向性蚀刻工艺同时于上述载板400的顶面401和底面403进行。在本发明实施例中，电镀工艺可包括有电电镀工艺(electrical plating process)。
在本发明实施例中，第一导线404a和404b可包括铜或者另一合适的材料。在本发明实施例中，第一导线404a和404b的宽度可设计为大于5μm。然而，应注意导线的宽度并无限制。对于不同的设计，如果有需要的话，导线的宽度可以小于5μm。在本实施例中，上述非等向性蚀刻工艺可精确地控制第一导线404a和404b的宽度。
接着，如图5C所示，进行堆叠工艺，将第一基座材料层406a和第二基座材料层406b分别堆叠于载板400的顶面401和底面403上。其中第一基座材料层406a和第二基座材料层406b分别覆盖第一导线404a和404b。在本实施例中，同时于上述载板400的顶面401和底面403上进行第一基座材料层406a和第二基座材料层406b的堆叠工艺。在本发明实施例中，第一基座材料层406a和第二基座材料层406b可包括聚丙烯(polypropylene，PP)或者另一合适的材料。
接着，请再参考图5C，进行钻孔工艺，以形成穿过第一基座材料层406a和第二基座材料层406b的开口(图未显示)，以定义后续形成的介层孔插塞408a和408b的位置。在本发明实施例中，上述钻孔工艺包括激光钻孔工艺、蚀刻钻孔工艺或机械钻孔工艺。在本实施例中，上述钻孔工艺同时在上述第一基座材料层406a和第二基座材料层406b上进行。
接着，进行电镀工艺，以将导电材料填入上述开口中，以分别在顶面401和底面403上形成介层孔插塞408a和408b。其中上述介层孔插塞408a和408b分别将第一导线404a和404b互连至后续形成的第二导线410a和410b。在一些实施例中，上述电镀工艺同时在上述第一基座材料层406a和第二基座材料层406b上进行。
接着，请再参考图5C，分别于上述第一基座材料层406a的第一表面412上和第二基座材料层406b的第一表面414上形成多个第二导线410a～410b。上述第一基座材料层406a的第一表面412和第二基座材料层406b的第一表面414分别远离上述载板400的顶面401和底面403。可利用电镀工艺和非等向性蚀刻工艺形成第二导线410a和410b。上述电镀工艺和非等向性蚀刻工艺同时于上述第一基座材料层406a的第一表面412上和第二基座材料层406b的第一表面414上进行。在本发明实施例中，电镀工艺可包括有电电镀工艺。
在本发明实施例中第二导线410a和410b可包括铜。在本发明实施例中，第二导线410a和410b的宽度可设计为大于5μm。然而，应注意导线的宽度并无限制。对于不同的设计，如果有需要的话，导线的宽度可以小于5μm。在本实施例中，上述非等向性蚀刻工艺可精确地控制第二导线410a和410b的宽度。
接着，如图5D和5E所示，将带有第一导线404a和第二导线410a的第一基座材料层406a以及带有该第一导线404b和该第二导线410b的第二基座材料层406b分别从如上述载板400的顶面401和底面403分离，以形成彼此分离的基座200c和基座200d。接着，分别从基座200c和基座200d上移除导电种晶层402a和导电种晶层402b。
如图5D和5E所示，第一导线404a和404b分别对齐于基座200c的第二表面416和基座200d的第二表面418，其中第二表面416和418分别相对于第一表面412和414。在本实施例中，利用双侧基座工艺(double-sided base fabricating process)，同时于相对表面(载体400的顶面401和底面403)上制造基座200c和基座200d。
可对本发明实施例做出各种变形和/或修改。在其他的一些实施例中，分离如图5D和5E所示的基座200c和基座200d之后，可选择性分别于基座200c的第二表面416上和基座200d的第二表面418上形成具有开口的保护层(passivation layer)或绝缘层(图未示)。在本实施例中，基座200c/200d和其上的钝化层或绝缘层可一起视为多层基座(multilayerbase)。在本实施例中，基座200c的第一导线404a或基座200d的第一导线404b从钝化层或绝缘层的开口中暴露出来。具有开口的绝缘层或钝化层以及第一导线404a/404b可类似于如图4所示的具有开口210的绝缘层208以及导线202d。
图6A-6E为本发明另一实施例的半导体封装的制造方法的剖面示意图。上述附图中的各元件如有与图1-4、图5A-5E所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。图6E显示本发明另一实施例的半导体封装500e的剖面示意图。
如图6A所示，提供具有顶面451的基座450。接着，如图6B所示，于上述基座450的顶面451上形成至少一条导线454。在本发明实施例中，可利用电镀工艺和非等向性蚀刻工艺形成导线454。在本发明实施例中，电镀工艺可包括有电电镀工艺。在本发明实施例中，导线454可包括铜或者另一合适的材料。在本发明实施例中，导线454的宽度可设计大于5μm。然而，应注意导线的宽度并无限制。对于不同的设计，如果有需要的话，导线的宽度可以小于5μm。在本实施例中，上述非等向性蚀刻工艺可精确地控制导线454的宽度。
接着，如图6C所示，进行堆叠工艺，于上述基座450的顶面451上设置额外绝缘材料456。并且，上述额外绝缘材料456覆盖导线454的顶面460和侧壁462。在一些实施例中，基座450及其上的绝缘层456可一起视为多层基座。
接着，请参考图6d，进行钻孔工艺，以形成穿过上述额外绝缘材料456的至少一开口458，以定义后续形成的导电结构的位置，上述导电结构例如可为铜凸块结构或焊锡凸块结构。在本发明实施例中，上述钻孔工艺包括激光钻孔工艺、蚀刻钻孔工艺或机械钻孔工艺。在本实施例中，导线454的顶面460会从上述额外绝缘材料456的开口458中暴露出来。
接着，请参考图6E，进行接合工艺，将半导体元件300藉由导电结构222固接于基座450。上述附图中的半导体元件300和导电结构222的元件如有与图1-4所示相同或相似的部分，则可参考前面的相关叙述，在此不做重复说明。进行接合工艺之后，导电结构222设置穿过上述额外绝缘材料456的开口458，且直接接触至导线454的顶面460。接着，可于半导体元件300和上述额外绝缘材料456之间的间隙中导入底胶填充材质230。在本发明实施例中，底胶填充材质230可包括毛细底胶填充材质(capillary underfill，CUF)、成型底胶填充材质(molded underfill，MUF)、非导电性绝缘胶(nonconductive paste，NCP)、非导电性绝缘膜(nonconductive film，NCF)或上述任意组合。最后，上述基座450、上述额外绝缘材料456、上述半导体元件300、上述导线454和上述导电结构222一起形成半导体封装500e。
本发明实施例提供一种半导体封装。上述半导体封装设计包括内嵌于基座(例如为印刷电路板(PCB))中的导线。上述导线具有顶面，上述顶面可位于上述基座的表面的上方、下方或对齐上述基座的表面，以改善用于高密度半导体封装的绕线能力。并且，上述导线的宽度可设计大于5μm。再者，上述基座可包括单一层结构或多层结构。本发明实施例也提供一种用于半导体封装的基座的制造方法。在本发明实施例中，上述方法可同时于载板的两侧制造两个基座。并且，导线内嵌于上述基座中。再者，可利用电镀工艺和非等向性蚀刻工艺形成导线，且上述非等向性蚀刻工艺可精确地控制上述导线的宽度。在本发明另一实施例中，上述方法可制造包括单一层结构或多层结构的基座，以增加设计选择。
图7A为根据本发明实施例的半导体封装的部分的透视图。图7B和7C为根据本发明实施例的半导体封装的部分的剖面示意图。图7A～7C所示的半导体封装的部分可以为半导体封装500a、500b、500c、500d或500e的一部分。
图7A～7C所示的导线100为细长的线或者条纹。也就是，导线100的长度远大于其宽度。在一些实施例中，导线100的至少一部分嵌入于基座(未示出)中，诸如基座200，200c或200d。导线100的一部分作为基座的外部连接区。在一些实施例中，导线100相同或者相似于导线202a、202b、202c、202d、404a、404b或454，并且出于简洁而不再描述。
如图7A～7C所示，导电结构110设置在导线100的作为外部连接区的部分上。在一些实施例中，导电结构110包括：焊锡盖层120，导电缓冲层130，铜层140及UBM层150。在一些实施例中，上述焊锡盖层120，导电缓冲层130及铜层140的宽度大于导线100的宽度。对于不同实施例，可以替换或者移除上述焊锡盖层120、导电缓冲层130、铜层140和UBM层150中的至少一个。可以将另外的层添加至导电结构110。
上述焊锡盖层120夹在导线100及导电缓冲层130之间。上述铜层140夹在导电缓冲层130和UBM层150之间。在一些实施例中，上述焊锡盖层120、导电缓冲层130、铜层140及UBM层150可以分别相同或者类似于焊锡盖层220、导电缓冲层218、铜层216及UBM层306。相应地，出于简洁而不再描述。
如图7A～7C所示，导电结构160设置在导电结构110上。在一些实施例中，导电结构160为导电接垫。上述导电接垫可以包含于互连结构或者RDL结构的最上层金属层中。导电结构160可以相同或者类似于导电接垫304。在一些实施例中，导电结构160的形状为矩形或者八边形，使得导电结构160的长度大致等于其宽度。在一些实施例中，导电结构160比导线100短，如图7B所示。在一些实施例中，导电结构160比导线100宽，如图7C所示。在一些实施例中，导线100的形状和面积不同于导电结构160。
图8A～8D为根据本发明不同实施例的半导体封装之剖面示意图。如图8A所示，半导体封装500f包括：半导体元件300、导电结构650、基座660及导电结构700。上述半导体元件300为封装并且使用倒装芯片技术安置在基座660的元件贴附面614上。如此，半导体元件300经由导电结构650和基座660电性连接至导电结构700。在一些实施例中，半导体元件300可以使用接合工艺(相同于上述提及的接合工艺)安置在基座660的元件贴附面614上。也就是说，半导体元件300通过导电结构650接合至嵌入于基座660中的导线690。
如图8A所示，半导体元件300包括：半导体主体301、导电结构600、载体基底610及模塑料640。在一些实施例中，上述半导体主体301可以包括但不限于：半导体层、于该半导体层的主要表面上制造的电路元件、ILD层和互连结构。在一些实施例中，该互连结构可以包括：导电层、与该导电层交替层压的介电层、以及多个穿过该半导体层上的介电层而形成的介层孔插塞。
在半导体主体301的主动面上存在导电接垫304和绝缘层302。半导体主体301的主动面面向基座660的元件贴附面614。导电接垫304包含于互连结构中的最上层导电层中。在一些实施例中，导电接垫304类似或者相同于图7A～7C所示的导电结构160。在一些实施例中，导电接垫304可以包括但不限于：铝、铜或者他们的合金。在一些实施例中，绝缘层302可以为单层结构或者多层结构。在一些实施例中，绝缘层302可以包括但不限于：氮化硅、氧化硅、氮氧化硅、聚酰亚胺或者他们的任意组合。于绝缘层302中形成多个开口，以部分地暴露导电接垫304。
导电结构600将导电接垫304连接至载体基底610。每个导电结构600的顶面直接接触一个导电接垫304。导电结构600的底面直接接触载体基底610中的一条导线。在一些实施例中，导电结构600为导电凸块、导电柱、导电胶结构、或者另一合适的导电结构。导电结构600可以包括：焊料、铜或者另一合适的导电材料。在一些实施例中，导电结构600相同或者类似于图1～4所示的导电结构222或者图7A～7C所示的导电结构110。例如，导电结构600可以包括：焊锡盖层、导电缓冲层、铜层和UBM层。在一些实施例中，导电结构600的尺寸小于导电结构650的尺寸。在一些实施例中，导电结构600之间的间距P1小于导电结构650之间的间距P2。
载体基底610也可称为“基座”，相同或者类似于图1～4所示的基座200。在一些实施例中，半导体主体301使用与上述提及的接合工艺相同的接合工艺安置在载体基底610上。也就是说，半导体主体301通过导电结构600接合至嵌入于载体基底610中的导线。如此，导电结构600的底面直接接触嵌入于载体基底610中的导线，而不接触接垫结构/部分。
在一些实施例中，载体基底610可以为RDL结构。载体基底610包括：一条或者多条导线630，设置在IMD层620中并且被IMD层620围绕。最上层的导线630电性连接至导电结构600。最底层的导线630电性连接至导电结构650。最上层的导线630相同或者类似于导线202a、202b、202c、202d、404a、404b或454。导线630的至少一部分嵌入于载体基底610中。例如，导线630的底面低于载体基底610的顶面，该顶面面向半导体主体301。另外，导线630的至少下面部分的侧壁埋入于载体基底610中。导线630可以包括：信号线段或者接地线段。信号线段或者接地线段用于安置于载体基底610上的半导体主体301的I/O连接。
根据本发明实施例，最顶层的导线630具有顶面，该顶面位于该载体基底610的顶面的上方、下方或者对齐该载体基底610的顶面。如此，可以显著地改善高密度半导体封装的绕线能力。在一些实施例中，导线630的宽度小于导电接垫304的宽度，类似于图7A～7C所示的导线100和导电结构160之间的关系。在一些实施例中，导线630不包括：接垫结构/部分。导线630在形状、面积、应力承受、I/O密度和制造成本等方面不同于接垫结构。但是，在其他实施例中，导电结构600可以不直接接合至导线630上，而在载体基底610的顶面上设置导电接垫(可嵌入于载体基底610中)，然后将导电结构600设置在该导电接垫上，例如该导电接垫直接接触导电结构600的底面。另外，将该导线630电性连接至该导电接垫，例如该导线630与该导电接垫可以一体成形。
IMD层620可以包括：多个次介电(sub-dielectric)层。为了简化示意图，在此中仅绘示了单个介电层作为示例。在一些实施例中，IMD层620可以由有机材料、非有机村料或者类似物形成，其中有机材料包括：聚合物基材料，非有机材料包括：氮化硅(SiNx)、氧化硅(SiOx)、石墨烯或者类似物。在一些实施例中，IMD层620为高k值介电层(k为介电层的介电常数)。在其他的一些实施例中，IMD层620可以由光敏材料形成，该光敏材料包括：干膜光阻(dry film photoresist)或者贴膜(taping film)。
如图8A所示，载体基底610的宽度大于半导体主体301的宽度，并且基座660的宽度大于载体基底610的宽度。如此，半导体主体301的电路通过大于一次的扇出(即通过载体基底610和基座660)连接至导电结构700。
模塑料640围绕半导体主体301及导电结构600。在一些实施例中，模塑料640直接接触载体基底610的导线630。在一些实施例中，模塑料640由诸如环氧树脂、树脂、可塑聚合物或者另一合适的模塑材料等非导电材料形成。在一些实施例中，模塑料640在实质为液体时应用，接着通过化学反应固化。在其他一些实施例中，模塑料640为UV(紫外)或者热固化的聚合物，该聚合物可作为凝胶或者可塑固定来应用，并且接着通过UV或者热固化工艺来固化。模塑料640可以按照模型进行固化。
在一些实施例中，导电结构650可以为导电凸块、导电柱、导电膏结构、或者另一合适的导电结构。导电结构650可以包括：焊料、铜或者另一合适的导电材料。在一些实施例中，导电结构650相同或者类似于导电结构110或222。例如，导电结构650可以包括：焊锡盖层、导电缓冲层、铜层和UBM层。
根据一些实施例，基座660为PCB并且可以由含有玻璃纤维的聚丙烯(polypropylene，PP)、环氧树脂、聚酰亚胺、氰酸酯、另一合适的材料或者他们的组合。在一些实施例中，基座660可以为多层结构，诸如两层或者四层。图示的基座660的配置仅为示例并且不是对本发明的限制。应注意根据一些实施例，基座660为非ABF(Ajinomoto Build-UpFilm，味之素复合膜)1-2-1基座。在一些实施例中，基座660的材料不同于ABF，以便基座660的成本低于ABF1-2-1基座的成本。
基座660也包括：导线670、690和位于导线670与690之间的导电插塞680。导电插塞680和导线670、690携带输入/输出信号、接地信号或电源信号穿过基座660的至少部分。基座660上方的导电结构650通过导线670、690及导电插塞680电性连接至基座660下方的导电结构700。在一些实施例中，导电插塞680之一夹在导线670之一和导线690之一之间。在其他的一些实施例中，基座660进一步包括：一条或者多条导线，位于导线670及690之间，以及导电插塞680之一穿透基座660中的所有导线。
导电结构700接合至基座660的底面，该底面背向载体基底610并且比基座660的元件贴附面614更远离导线690。在一些实施例中，导电结构700为导电凸块或者另一合适的导电结构。导电结构700可以包括：焊料或者另一合适的导电材料。在一些实施例中，导电结构700的尺寸大于导电结构650及600的尺寸。在一些实施例中，导电结构700之间的间距P3大于导电结构650之间的间距P2。在一些实施例中，间距P3大于导电结构600之间的间距P1。
在一些实施例中，间距P3与间距P1之间的比值大于3，诸如大约介于5～9之间。在一些实施例中，间距P3与间距P2之间的比值大于1并且小于等于3。但是，应注意对于上述比值没有限制。对于不同的设计，如果有需求，间距P3与间距P2之间的比值可以大于3。
在一些实施例中，底胶填充材质(诸如如图1～4所示的底胶填充材质230)设置在半导体元件300与基座660之间的间隙中。该底胶填充材质围绕该导电结构650。
如图8A所示，该半导体封装500f另外包括：散热基座(heat slug)710、黏合层720、以及散热界面材料(thermal interface material，TIM)730。该散热基座710通过该黏合层720附着在基座660的元件贴附面614上。如此，散热基座710覆盖半导体元件300。在一些实施例中，黏合层720直接接触基座660中的导线690之一。
TIM730位于半导体元件300及散热基座710之间，以消散来自半导体元件300的热量。在一些实施例中，TIM730夹在半导体主体301的非主动面及散热基座710之间。在其他一些实施例中，半导体封装500f不包括：该散热基座710，该黏合层720和/或该TIM730。
尽管图8A所示的实施例提供了含有半导体主体301的封装，但是本发明的实施例不限制于此。图8B示出了半导体封装500g，类似于该半导体封装500f。图8B与图8A中，相同的元件使用相同的参考符号，并且出于简洁而不赘述。
如图8B所示，该半导体元件300包括：多个半导体主体301。该多个半导体主体301可以为多个具有相同或者不同功能的半导体晶粒。该多个半导体晶粒具有相同或者不同的尺寸。半导体元件300中的半导体晶粒的实际数量、功能和尺寸由设计要求决定，并且不是限制。可替换地，半导体主体301之一可以由IPD(Integrated Passive Device，集成无源元件)、电容、电感、变容二极管或者另一合适的无源元件替换。半导体主体301由模塑料640围绕。TIM730介于半导体元件300及散热基座710之间，以消散来自半导体元件300的热量。
可以对本发明实施例做出各种变化和/或修改。图8C示出了半导体封装500h，类似于该半导体封装500g。图8C和图8A及图8B中相同的元件，使用相同的参考符号来标记，并且出于简洁而不赘述。
如图8C所示，倒置半导体主体301之一，并且通过导电结构600将其导电接垫304电性连接至载体基底610。另一半导体主体301正面向上并且通过黏合层602附着至载体基底610上。另外，该另一半导体主体301的导电接垫304通过导电结构604电性连接至载体基底610，该导电结构604可不同于导电结构600。例如，导电结构600为导电柱，而导电结构604为接合线。导电结构604封闭于模塑料640中。模塑料640的一部分在半导体主体301之一和TIM730之间延伸。用于电性连接导电接垫304及载体基底610的真实的导电结构由设计要求决定，并且不受限制。
尽管图8B及8C示出的实施例提供了含有多个并排设置的半导体主体301的封装，但是本发明的实施例不限制于此。图8D示出了半导体封装500i，类似于半导体封装500h。图8D中与图8A～8C相同的元件，使用相同的参考附号来标记，并且出于简洁而不再赘述。
如图8D所示，半导体元件300包括：多个垂直堆叠的半导体主体301。翻转下面的半导体主体301并且通过导电结构600将其导电接垫304电性连接至载体基底610。上面覆盖的半导体主体301正面向上并且通过黏合层602附着至下面的半导体主体301上。另外，其导电接垫304通过导电结构604电性连接至载体基底610，其中该导电结构604不同于导电结构600。例如，导电结构600为导电柱而导电结构604为接合线。半导体主体301由模塑料640围绕并且通过模塑料640与TIM730分隔开。在其他的一些实施例中，在半导体元件300与散热基座710之间可以没有TIM。
根据本发明一些实施例的半导体封装提供了各种优势。该半导体封装包括：半导体元件，使用倒装芯片技术接合在基座上。该半导体元件为封装。该封装包括：至少一半导体晶粒及扇出结构(诸如载体基底)，该扇出结构设置在该半导体晶粒及该第一导电结构之间。具体地，半导体晶粒接合至嵌入于扇出结构中的导线，而不是接垫结构。扇出结构通过第一导电结构将半导体晶粒电性连接至基座下方的第二导电结构。由于扇出结构，因此第一导电结构之间的间距变大。另外，第二导电结构之间的间距与第一导电结构之间的间距的差变小。如此，基座不限定于具有小线宽及间距的基座。显著的增强了基座的设计灵活性。例如，基座可以为用于PCB的普通的廉价基座，而不是昂贵的ABF1-2-1基座。相应地，可以显著地降低基座和含有该基座的半导体封装的制造成本。本发明实施例提供了具有改善的集成灵活性及更低的制造成本的半导体封装。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (16)

1.一种半导体封装，其特征在于，包括：
基座；
多个第一导电结构；以及
半导体元件，通过该多个第一导电结构接合至该基座；
其中，该半导体元件包括：
载体基底；
多个第二导电结构；以及
第一半导体主体，通过该多个第二导电结构接合至该载体基底；
其中，该多个第一导电结构和该多个第二导电结构分别设置在该载体基底的两相对表面上；
其中，该载体基底及该基座均为该第一半导体主体的扇出结构。
2.如权利要求1所述半导体封装，其特征在于，进一步包括：
多个第三导电结构，接合在该基座上，并且该多个第一导电结构和该多个第三导电结构分别设置在该基座的两相对表面上。
3.如权利要求2所述半导体封装，其特征在于，该多个第一导电结构的尺寸大于该多个第二导电结构的尺寸且小于该多个第三导电结构的尺寸。
4.如权利要求2所述半导体封装，其特征在于，该多个第一导电结构之间的间距大于该多个第二导电结构之间的间距，且小于该多个第三导电结构之间的间距。
5.如权利要求2所述半导体封装，其特征在于，该多个第三导电结构之间的间距与该多个第二导电结构之间的间距之比值介于5～9之间，并且该多个第三导电结构之间的间距与该多个第一导电结构之间的间距之比值大于1且小于等于3。
6.如权利要求1所述半导体封装，其特征在于，该半导体元件进一步包括：
模塑料，设置在该载体基底上，并且围绕该第一半导体主体及该多个第二导电结构。
7.如权利要求6所述半导体封装，其特征在于，进一步包括：
底胶填充材质，设置在该基座上，并且围绕该半导体元件及该多个第一导电结构，以及填充该半导体元件与该基座之间的间隙。
8.如权利要求1所述半导体封装，其特征在于，该载体基底的宽度大于该第一半导体主体的宽度，且小于该基座的宽度。
9.如权利要求1所述半导体封装，其特征在于，该第一半导体主体为半导体晶粒。
10.如权利要求1所述半导体封装，其特征在于，该半导体元件还包括：
第二半导体主体，与该第一半导体主体并排设置在该载体基底上或者堆叠在该第一半导体主体上。
11.如权利要求10所述半导体封装，其特征在于，该第一半导体主体使用倒装芯片方式接合至该载体基底；
当该第二半导体主体与该第一半导体主体并排设置在该载体基底上时，该第二半导体主体使用倒装芯片或者线接合方式接合至该载体基底；
当该第二半导体主体堆叠在该第一半导体主体上时，该第二半导体主体使用线接合方式接合至该载体基底。
12.如权利要求1所述半导体封装，其特征在于，进一步包括：
散热基座，通过黏合层附着至该基座，并且覆盖该半导体元件。
13.如权利要求12所述半导体封装，其特征在于，进一步包括：
散热界面材料，位于该散热基座与该半导体元件之间。
14.如权利要求1所述半导体封装，其特征在于，该载体基底包括：导线，该第二导电结构直接接合在该导线上。
15.如权利要求14所述半导体封装，其特征在于，
该导线为细长形的；
或者，该导线用于携带输入/输出信号、接地信号或电源信号穿过该载体基底的至少一部分；
或者，该导线的顶面位于该载体基底面向该半导体主体的表面的上方、下方或者对齐；
或者，该导线的宽度小于该第一半导体主体上的连接至该第二导电结构的接垫的宽度；
或者，该导线的形状不同于该第一半导体主体上的连接至该第二导电结构的接垫的形状。
16.如权利要求14所述半导体封装，其特征在于，该第二导电结构包括：焊锡盖层，直接接触该导线；
或者，该第二导电结构包括：宽度大于该导线的宽度的铜层和/或宽度大于该导线的宽度的焊锡盖层。
CN201610810326.XA 2015-09-16 2016-09-08 半导体封装 Pending CN106910732A (zh)

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