CN113809059A - 衬底结构和其形成方法以及半导体封装结构 - Google Patents

衬底结构和其形成方法以及半导体封装结构 Download PDF

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CN113809059A
CN113809059A CN202110648531.1A CN202110648531A CN113809059A CN 113809059 A CN113809059 A CN 113809059A CN 202110648531 A CN202110648531 A CN 202110648531A CN 113809059 A CN113809059 A CN 113809059A
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electronic component
substrate
metal layer
substrate structure
thickness
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许武州
陈敏尧
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本公开提供了一种衬底结构、其制造方法以及包含所述衬底结构的半导体封装结构。所述衬底结构包含衬底、第一电子组件、第二电子组件以及多个金属层。所述第一电子组件安置在所述衬底内。所述第二电子组件安置在所述衬底内并且与所述第一电子组件一起在水平方向上排列。所述金属层安置在所述衬底的上表面上方。所述第一电子组件上方的金属层的数量大于所述第二电子组件上方的金属层的数量。

Description

衬底结构和其形成方法以及半导体封装结构
技术领域
本公开涉及一种衬底结构，并且更具体地涉及一种包含不同大小的电子组件的衬底结构。
背景技术
智能系统的日益复杂性提高了IC集成的重要性。用于制造具有较小尺寸的半导体封装结构的主要方法之一是将有源装置和无源装置嵌入到衬底中。利用此类嵌入式衬底，可以减少导电传递路径，因此可以减少功率损耗。
然而，当嵌入不同大小的电子组件时，可能需要纵横比(aspect ratio)较大的通孔，这增加了如激光钻孔或电镀等制造工艺的难度。另外，电子组件的两个相对侧上的端子可能位于距衬底邻近表面不同距离的位置，且具有不同的直径，这对半导体封装结构的布局设计产生不利影响，并且不利于阻抗匹配。
发明内容
在一些实施例中，一种衬底结构包含衬底、第一电子组件、第二电子组件以及多个金属层。所述第一电子组件安置在所述衬底内。所述第二电子组件安置在所述衬底内并且与所述第一电子组件一起在水平方向上排列。所述金属层安置在所述衬底的上表面上方。所述第一电子组件上方的金属层的数量大于所述第二电子组件上方的金属层的数量。
在一些实施例中，一种半导体封装结构包含衬底结构、第一重布结构、第一半导体芯片和包封料。所述衬底结构包含衬底、第一电子组件以及第二电子组件。所述第一电子组件安置在所述衬底内。所述第二电子组件安置在所述衬底内并且与所述第一电子组件在水平方向上排列。所述第一电子组件的厚度小于所述第二电子组件的厚度。所述第一重布结构安置在所述衬底结构的上表面上。所述第一半导体芯片安置在所述第一重布结构上。所述包封料覆盖所述第一半导体芯片和所述第一重布结构。
在一些实施例中，一种用于制造衬底结构的方法包含：提供具有第一空腔的核心衬底(core substrate)；在所述第一空腔中安置第一电子组件；形成覆盖并电连接到所述第一电子组件的第一金属层；形成穿透所述核心衬底的第二空腔；在所述第二空腔中安置第二电子组件；以及形成覆盖并电连接到所述第一电子组件和所述第二电子组件的第二金属层。
附图说明
当与附图一起阅读以下详细描述时，可以根据以下详细描述容易地理解本公开的一些实施例的各方面。注意，各种结构可能未按比例绘制，并且为了讨论的清楚起见，可以任意增加或减小各种结构的尺寸。
图1展示了根据本公开的一些实施例的衬底结构的实例的横截面视图。
图1A展示了根据本公开的一些实施例的衬底结构的实例的横截面视图。
图2展示了根据本公开的一些实施例的衬底结构的实例的横截面视图。
图3展示了根据本公开的一些实施例的半导体封装结构的实例的横截面视图。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I、图4J、图4K、图4L和图4M展示了根据本公开的一些实施例的用于制造衬底结构的方法的实例的各种阶段。
具体实施方式
贯穿附图和详细描述，使用了共同的附图标记来指示相同或类似的组件。根据以下结合附图进行的详细描述将容易理解本公开的实施例。
以下公开提供了用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述了组件和布置的具体实例以解释本公开的某些方面。当然，这些仅仅是实例并且不旨在是限制性的。例如，在以下描述中，在第二特征上方或之上形成第一特征可以包含将第一特征和第二特征形成或安置成直接接触的实施例，并且还可以包含可以在第一特征与第二特征之间形成和安置另外的特征使得第一特征和第二特征可以不直接接触的实施例。另外，本公开可以在各个实例中重复附图标记和/或字母。这种重复是为了简单和清晰的目的并且本身并不指示所讨论的各个实施例和/或配置之间的关系。
图1和图1A展示了根据本公开的一些实施例的衬底结构1的实例的横截面视图。
衬底结构1包含衬底10、电子组件20、电子组件30、介电层11、介电层12和多个金属层，如金属层51、金属层52、金属层61和金属层62。
衬底10可以包含核心衬底。核心衬底可以包含预浸材料(prepreg，PP)、味之素增层膜(Ajinomoto build-up film，ABF)或其它合适的材料。在一些实施例中，核心衬底中使用的树脂材料可以是纤维增强树脂，以便增强核心衬底，并且增强纤维可以是但不限于玻璃纤维或凯芙拉纤维(Kevlar fiber)(aramid fiber，芳纶纤维)。衬底10定义了用于容纳具有不同大小的电子组件的多个空腔。衬底10可以包含用于电连接的一或多条导电迹线(trace)、一或多个衬垫(pad)、一或多个触点(contact)、一或多个通孔(via)。例如，在图1所展示的实施例中，衬底10可以包含衬垫101、衬垫102和通孔103。衬垫102安置在衬底10的上表面10a上并且衬垫102安置在衬底10的下表面10b上。通孔103穿透衬底10并连接衬垫101和衬垫102。
电子组件20安置在衬底10内。电子组件20安置在由衬底10定义的第一空腔中。电子组件20可以包含无源装置、有源装置或两者。在一些实施例中，电子组件20可以是集成无源装置(integrated passive device，IPD)。无源装置可以包含电感器、电容器或其它无源装置。有源装置可以包含二极管、晶体管或其它有源装置。电子组件20也可以被称为第一电子组件。
电子组件20具有表面20a和与表面20a相对的表面20b。表面20b也可以被称为下表面。表面20a也可以被称为上表面。电子组件20可以包含分别位于表面20a和表面20b上的端子22和端子21。端子22和端子21可以包含导电材料，如金属、金属合金或其它合适的材料。
介电层11包围或覆盖衬底10和电子组件20。电子组件20嵌入在介电层11中。在一些实施例中，介电层11覆盖衬底10的表面10a和表面10b，并填充由衬底10定义的第一空腔。介电层11可以由聚合物或非聚合物介电材料制成。在一些实施例中，介电层11可以包含处于硬化或半硬化状态的可流动介电材料，如液晶聚合物、具有预浸渍纤维的树脂、味之素增层膜(ABF)、环氧树脂、聚酰亚胺、模制原料或处于硬化或半硬化状态的其它可流动介电材料。介电层11与衬底10一起定义了用于容纳电子组件30的第二空腔。第二空腔不同于第一空腔。
电子组件30安置在衬底10内。电子组件30安置在由衬底10和介电层11定义的第二空腔中。电子组件30可以由衬底10与电子组件20分离。电子组件30和电子组件20可以并排排列(arranged side-by-side)或沿水平方向排列(arranged along a horizontaldirection)。电子组件30可以嵌入在介电层12中。电子组件30可以包含无源装置、有源装置或两者。在一些实施例中，电子组件30可以是IPD。无源装置可以包含电感器、电容器或其它无源装置。有源装置可以包含二极管、晶体管或其它有源装置。电子组件30的大小可以不同于电子组件20的大小。在一些实施例中，电子组件30的大小可以大于电子组件20的大小。电子组件30也可以被称为第二电子组件。
电子组件30具有表面30a和与表面30a相对的表面30b。表面30b也可以被称为下表面。表面30a也可以被称为上表面。电子组件30可以分别包含表面30a上的端子32和表面30b上的端子31。端子32和端子31可以包含导电材料，如金属、金属合金或其它合适的材料。
在一些实施例中，电子组件20和电子组件30中的至少一个电子组件是无源装置。在一些实施例中，电子组件20和电子组件30都是无源装置。
介电层12包围或覆盖介电层11、金属层51和52以及电子组件30。电子组件30嵌入在介电层12中。在一些实施例中，介电层12覆盖介电层11的上表面11a和下表面11b、金属层52的上表面和金属层51的下表面，并且填充由衬底10和介电层11定义的第二空腔。介电层12可以由聚合物或非聚合物介电材料制成。在一些实施例中，介电层12可以包含处于硬化或半硬化状态的可流动介电材料，如液晶聚合物、具有预浸渍纤维的树脂、味之素增层膜(ABF)、环氧树脂、聚酰亚胺、模制原料或处于硬化或半硬化状态的其它可流动介电材料。
电子组件20具有厚度T1。厚度T1可以是指电子组件20的垂直(vertical)尺寸。在一些实施例中，厚度T1可以是指沿垂直方向从电子组件20的上表面到下表面的距离。在如图1所展示的具有端子21和22的实施例中，厚度T1可以是指沿垂直方向从端子22的上表面到端子21的下表面的距离。
电子组件30具有厚度T2。厚度T2可以是指电子组件30的垂直尺寸。在一些实施例中，厚度T2可以是指沿垂直方向从电子组件30的上表面到下表面的距离。在如图1所展示的具有端子31和32的实施例中，厚度T2可以是指沿垂直方向从端子32的上表面到端子31的下表面的距离。
衬底10具有厚度T3。厚度T3可以是指衬底10的垂直尺寸。在一些实施例中，厚度T3可以是指沿垂直方向从衬底10的上表面到下表面的距离。在衬垫安置在衬底10的上表面和下表面上的实施例中，厚度T3可以是指沿垂直方向从衬垫102的上表面到衬垫101的下表面的距离。
在一些实施例中，电子组件20的厚度T1大于、基本上等于或小于衬底10的厚度T3。在一些实施例中，电子组件20的厚度T1基本上等于或小于衬底10的厚度T3。在一些实施例中，电子组件20的厚度T1基本上等于衬底10的厚度T3。
在一些实施例中，电子组件20的厚度T1小于电子组件30的厚度T2。
在一些实施例中，衬底10的厚度T3小于电子组件30的厚度T2。
在一些实施例中，电子组件20的厚度T1小于电子组件30的厚度T2；并且衬底10的厚度T3小于电子组件30的厚度T2。
在一些实施例中，电子组件20的厚度T1小于电子组件30的厚度T2，衬底10的厚度T3小于电子组件30的厚度T2，并且电子组件20的厚度T1基本上等于或小于衬底10的厚度T3。
在一些实施例中，电子组件20的下表面20b高于电子组件30的下表面30b。在一些实施例中，电子组件20的上表面20a低于电子组件30的上表面30a。在一些实施例中，电子组件20的下表面20b位于电子组件30的表面30b与表面30a之间的距离内。在一些实施例中，电子组件20的上表面20a位于电子组件30的表面30b与表面30a之间的距离内。
衬底结构1包含安置在衬底表面上方的多个金属层(例如，衬底10的表面10a上方的金属层52和62或者衬底10的表面10b上方的金属层51和61)。在一些实施例中，金属层可以具有一部分(例如，衬垫)，位于具有不同大小的电子组件中的一或多个电子组件正上方。在根据本公开的实施例中，安置在小电子组件上方或正上方的金属层的数量大于安置在大电子组件上方或正上方的金属层的数量。因此，可以通过两个或两个以上的小通孔，而不是单个通孔，来实现从小电子组件到最外层金属层的衬垫的电连接，这改善了通孔的纵横比并且因此有利于衬底结构的产量和电性能。
金属层51、52、61和62可以包含一或多条迹线和一或多个衬垫。金属层51、52、61和62可以包含金属、金属合金或其它合适的材料。金属层52和62安置在衬底10的表面10a的上方。金属层51和61安置在衬底10的表面10b的下方。空间描述仅用于说明的目的。
金属层51可以安置在介电层11的表面11b上。在一些实施例中，金属层51可以覆盖衬底10和电子组件20或安置在其下方。在一些实施例中，金属层51可以覆盖电子组件20的表面20b或安置在其下方。金属层51可以不覆盖电子组件30的表面30b或不安置在其下方。在一些实施例中，金属层51可以与电子组件30的端子31共面。也就是说，金属层51的高度(elevation)可以与电子组件30的端子31的高度基本上相同。更具体地，金属层51的下表面的高度可以与端子31的下表面的高度基本上相同。金属层51可以通过通孔501电连接到衬底10的衬垫102或电子组件20的端子21。
金属层52可以安置在介电层11的表面11a上。在一些实施例中，金属层52可以覆盖衬底10和电子组件20或安置在其上方。在一些实施例中，金属层52可以覆盖电子组件20的表面20a或安置在其上方。金属层52可以不覆盖电子组件30的表面30a或不安置在其上方。在一些实施例中，金属层52可以与电子组件30的端子32共面。也就是说，金属层52的高度可以与电子组件30的端子32的高度基本上相同。更具体地，金属层52的上表面的高度可以与电子组件30的端子32的上表面的高度基本上相同。金属层52可以通过通孔502电连接到衬底10的衬垫102或电子组件20的端子22。
金属层61可以安置在介电层12的表面12b上。在一些实施例中，金属层61可以覆盖衬底10、金属层51、电子组件20和电子组件30或安置在其下方。在一些实施例中，金属层61可以覆盖电子组件20的表面20b或安置在其下方。在一些实施例中，金属层61可以覆盖电子组件30的表面30b。金属层61可以通过通孔601、金属层51和通孔501电连接到衬底10的衬垫101或电子组件20的端子21。金属层61可以通过通孔601电连接到电子组件30的端子31。在一些实施例中，金属层51的厚度可以大于金属层61的厚度。
金属层62可以安置在介电层12的表面12a上。在一些实施例中，金属层62可以覆盖衬底10、金属层52、电子组件20和电子组件30或安置在其上方。在一些实施例中，金属层62可以覆盖电子组件20的表面20a或安置在其上方。在一些实施例中，金属层62可以覆盖电子组件30的表面30a或安置在其上方。金属层62可以通过通孔602、金属层52和通孔502电连接到衬底10的衬垫102或电子组件20的端子22。金属层62可以通过通孔602电连接到电子组件30的端子32。
可以根据电子组件的厚度调节金属层的厚度(例如，可以根据电子组件30的厚度调节金属层51和52的厚度)。因此，嵌入在衬底结构内的金属层的厚度可以大于最外层金属层的厚度。在一些实施例中，金属层51的厚度可以大于金属层61的厚度。在一些实施例中，金属层52的厚度可以大于金属层62的厚度。
在一些实施例中，位于电子组件20的正上方(即，之上)的金属层的数量大于位于电子组件30的正上方(即，之上)的金属层的数量。如图1所示，金属层52和金属层62位于电子组件20之上，而金属层62位于电子组件30之上。在一些实施例中，电子组件20之上的金属层的数量等于衬底10之上的金属层的数量。如图1所示，金属层52和金属层62位于电子组件20和衬底10之上。
金属层51或金属层52也可以被称为第一金属层或第一电镀层。金属层61或金属层62也可以被称为第二金属层或第二电镀层。
衬底结构1可以包含上表面1a和与上表面相对的下表面1b。衬底结构1的下表面1b可以由介电层12的下表面定义，或者由金属层61的下表面(如果存在)定义。上表面1a可以由介电层12的上表面或金属层62的上表面(如果存在)定义。
在一些实施例中，电子组件20的上表面20a与衬底结构1的上表面1a之间的距离基本上等于电子组件20的下表面20b与衬底结构1的表面1b之间的距离。在一些实施例中，电子组件30的上表面30a与衬底结构1的上表面1a之间的距离基本上等于表面30b与衬底结构1的表面1b之间的距离。在一些实施例中，衬垫101与表面1b之间的距离基本上等于衬垫102与表面1a之间的距离。
在一些实施例中，电子组件20的水平中心轴线与电子组件30的水平中心轴线基本上共面。在一些实施例中，衬底结构1包含相对于衬底结构1的中心轴线C彼此对称的上部部分和下部部分。中心轴线C可以与电子组件20的水平中心轴线或电子组件30的水平中心轴线基本上共面。
如图1A所示，在一些实施例中，衬底结构1具有第一部分R1，所述第一部分位于电子组件20的垂直投影方向处，并且衬底结构1的第一部分R1相对于电子组件20的水平中心轴线对称。如图1A所示，在一些实施例中，衬底结构1具有第二部分R2，所述第二部分R2位于电子组件30的垂直投影方向处，并且衬底结构1的第二部分R2相对于电子组件30的水平中心轴线对称。由于对称性，通孔601和602可以具有基本上相同的孔径或纵横比，并且通孔501和502可以具有基本上相同的孔径或纵横比。因此，可以优化用于形成通孔(例如，601和602、501和502)的工艺，如激光钻孔或电镀。
根据本公开的一些实施例，衬底结构包含不同大小的两个或两个以上的电子组件。较小的电子组件的水平中心轴线与较大的电子组件的水平中心轴线基本上共面，这改善了阻抗匹配和/或衬底结构的布局。此外，位于较大电子组件上方和下方对称位置处的通孔可以具有基本上相同的孔径或纵横比。例如，电子组件30正上方的通孔602的孔径或纵横比可以基本上等于电子组件30正下方的通孔601的孔径或纵横比。因此，可以优化如激光钻孔或电镀等工艺，由此增强衬底结构的产量和电性能。
图2展示了根据本公开的一些实施例的衬底结构2的实例的横截面视图。图2的衬底结构2具有与图1的衬底结构1的结构类似的结构，其中不同之处在于电子组件30的端子31与金属层51共面，而电子组件30的端子32与金属层52不共面。
在一些实施例中，衬底结构2位于电子组件30的垂直投影方向处的第二部分相对于电子组件30的水平中心轴线并未对称。在一些实施例中，端子32的上表面可以低于金属层52的上表面。在此实施例中，表面30b与表面1b之间的距离不等于表面30a与表面1a之间的距离。连接电子组件30的端子32和金属层62的通孔的深度大于连接电子组件30的端子31和金属层61的通孔的深度。
图3展示了根据本公开的一些实施例的半导体封装结构3的实例的横截面视图。
半导体封装结构3可以包含衬底结构1、包封料(encapsulant)40、重布结构(redistribution structure)71、重布结构72、半导体芯片81、半导体芯片82和焊球(solder balls)或凸点(bumps)84。由于电子组件20和30嵌入在衬底结构1中，因此可以减小半导体封装结构的大小，并且可以减小导电路径。
重布结构71和重布结构72可以安置在衬底结构1的两个相对侧上。重布结构71可以安置在衬底结构1的下表面1b上。重布结构72安置在衬底结构1的上表面1a上。重布结构71和重布结构72可以分别包含多个金属层、通孔和介电层。
半导体芯片81可以安置在重布结构71上。半导体芯片81可以通过重布结构71电连接到电子组件20和/或电子组件30。在一些实施例中，半导体芯片81可以是例如电源管理电路(power management integrated circuit，PMIC)或其它芯片。半导体芯片82可以安置在重布结构72上。半导体芯片82可以通过重布结构72电连接到电子组件20和/或电子组件30。半导体芯片82可以是例如专用集成电路(application specific integrated circuit，ASIC)或高带宽存储器(high bandwidth memory，HBM)。
可以在重布结构72上安置有包封料40。包封料40可以覆盖重布结构72。包封料40可以覆盖半导体芯片82。包封料40可以围绕或包围半导体芯片82。在一些实施例中，包封料40由模制材料制成，所述模制材料可以包含例如酚醛清漆基树脂、环氧树脂基树脂、硅基树脂或其它另一种合适的包封料。还可以包含合适的填料，如粉末状SiO2。
可以在重布结构71上安置焊球或凸点84。焊球或凸点84可以邻近于衬底10的表面1b。焊球或凸点84可以围绕半导体芯片81。焊球或凸点84可以包含例如AgSn、另一种导电金属或其合金。焊球或凸点84可以附接到例如印刷电路板(未示出)。
在此实施例中，可以将衬底结构1应用于半导体封装结构3。因此，可以改善半导体封装结构3的阻抗匹配。另外，可以改善制造半导体封装结构3的产量。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I、图4J、图4K、图4L和图4M展示了根据本公开的一些实施例的用于制造衬底结构的方法的实例的各种阶段。
如图4A所示，提供了核心衬底(core substrate)10。在核心衬底10的下表面10b和上表面10a中形成衬垫101和102，并且还形成了连接衬垫101和102的导电通孔103。
如图4B所示，形成空腔C1。空腔C1可以通过例如蚀刻工艺、激光钻孔或其它合适的技术形成。空腔C1可以穿透核心衬底10。
如图4C所示，在载体91上安置核心衬底10。在一些实施例中，核心衬底10可以通过粘性层(未示出)连接到载体91。在空腔C1中安置有电子组件20。电子组件20可以具有安置在其下表面和上表面(即，20b和20a)上的端子21和22。在一些实施例中，核心衬底10的厚度可以调节成使得电子组件20的厚度大于、基本上等于或小于核心衬底10的厚度。在一些实施例中，核心衬底10的衬垫101的下表面可以与电子组件20的端子21的下表面共面。
如图4D所示，形成介电层111。介电层111可以覆盖电子组件20。介电层111可以覆盖核心衬底10。介电层111可以例如通过向核心衬底的上表面涂覆介电涂层组合物和/或层压介电层(例如，PP或ABF层)形成。例如，在涂覆或层压期间，介电层111可以填充空腔C1。介电层111可以通过任何其它合适的工艺形成。
如图4E所示，在去除载体91和其上的粘性层之后，例如通过向介电层111的下表面涂覆介电涂层组合物和/或层压介电层(例如，PP或ABF层)形成介电层112。介电层111与介电层112一起构成包围核心衬底13和电子组件20的介电层11。介电层111和介电层112可以由相同或不同的材料制成。
介电层11可以如上文所展示的制备，或者通过任何其它合适的技术形成。例如，在一些实施例中，可以在安置核心衬底10和电子组件20之前在载体91上形成介电层112；并且然后施加介电层111以覆盖核心衬底10和电子组件20。本公开并不旨在限制于此。
如图4F所示，形成多个开口O11和O12。开口O11可以暴露核心衬底10的衬垫101。开口O11可以暴露电子组件20的端子21。开口O12可以暴露核心衬底10的衬垫102。开口O12可以暴露电子组件20的端子22。开口O11和/或O12的孔径可以根据设计要求进行修改。开口O11和O12可以通过激光钻孔、光刻工艺、蚀刻工艺或其它合适的工艺形成。
如图4G所示，可以执行第一电镀工艺以形成通孔501、金属层51、通孔502和金属层52。通孔501可以填充开口O11。通孔502可以填充开口O12。金属层51可以覆盖介电层11的下表面。金属层52可以覆盖介电层11的上表面。在其它一些实施例中，可以使用金属层52来电连接衬垫102和端子22。
如图4H所示，在图4G的结构中形成空腔C2。在一些实施例中，空腔C2的孔径大于空腔C1的孔径。空腔C2可以通过例如蚀刻工艺、激光钻孔或其它合适的技术形成。空腔C2可以穿透介电层11和核心衬底13。
如图4I所示，在载体92上安置图4H的结构。在一些实施例中，图4H的结构可以通过粘性层(未示出)连接到载体92。在空腔C2中安置有电子组件30。电子组件30可以具有安置在其下表面和上表面(即，30b和30a)上的端子31和32。电子组件30的厚度可以大于电子组件20的厚度。在一些实施例中，金属层51可以与电子组件30的端子31共面，因为两者都安置在载体92上。更具体地，金属层51的下表面可以与电子组件30的端子31的下表面共面。在一些实施例中，可以控制金属层52的厚度使得金属层502和端子32处于同一高度；并且如果需要，则可以一起调整金属层52的厚度、金属层51的厚度和介电层11的厚度以实现此类目的。
如图4J所示，形成介电层121。介电层121可以覆盖电子组件30、介电层11和金属层52。介电层11可以例如通过向图4I的结构的上表面涂覆介电涂层组合物和/或层压介电层(例如，PP或ABF层)形成。例如，在涂覆或层压期间，介电层121可以填充空腔C2。介电层121可以通过任何其它合适的工艺形成。
如图4K所示，在去除载体91和其上的粘性层之后，例如通过向介电层121的下表面涂覆介电涂层组合物和/或层压介电层(例如，PP或ABF层)形成介电层122。介电层121与介电层122一起构成包围电子组件30、介电层11和金属层52和51的介电层12。介电层121和介电层122可以由相同或不同的材料制成。
与介电层11类似，介电层12可以通过任何其它合适的技术形成。例如，在一些实施例中，可以在安置图4H的结构和电子组件30之前在载体92上形成有介电层122；并且然后施加介电层121。
如图4L所示，形成多个开口O21和O22。开口O21可以暴露金属层51。开口O21可以暴露电子组件30的端子31。开口O22可以暴露金属层52。开口O22可以暴露电子组件30的端子32。开口O21和O22的孔径可以根据设计要求进行修改。开口O21和O22可以通过激光钻孔、光刻工艺、蚀刻工艺或其它合适的工艺形成。
如图4M所示，可以执行第二电镀工艺以形成通孔601、金属层61、通孔602和金属层62，由此产生衬底结构1。通孔601可以填充开口O21。通孔602可以填充开口O22。金属层61可以覆盖介电层12的下表面。金属层62可以覆盖介电层12的上表面。在此实施例中，由于开口O21的孔径与开口O22的孔径基本上相同，因此可以分别开口O21和O22中形成具有较少的缺陷(如空隙)通孔601和602。在其它一些实施例中，可以使用金属层62电连接衬垫102、端子22和端子32。
除非另有说明，否则如“上方”、“下方”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“较高”、“下部”、“上部”、“之上”、“下面”等空间描述是关于附图中示出的朝向而指示的。应当理解，本文所使用的空间描述仅仅是出于说明的目的，并且本文所描述的结构的实际实施方案可以在空间上以任何朝向或方式布置，条件是这种布置不会使本公开的实施例的优点发生偏离。
如本文所使用的，术语“大约”、“基本上”、“基本”和“约”用于描述和解释小的变化。当结合事件或情形使用时，所述术语可以指代事件或情形精确发生的实例以及事件或情形接近发生的实例。例如，当与数值结合使用时，所述术语可以指代小于或等于所述数值的±10％，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％的变化范围。例如，如果两个数值之间的差值小于或等于平均值的±10％，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或者小于或等于±0.05％，则所述数值可以被视为“基本上”相同或相等。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，则可以将所述两个表面视为共面或基本上共面。
如本文所使用的，除非上下文另有明确指示，否则单数术语“一个/一种(a/an)”和“所述(the)”可以包含复数指代物。
如本文所使用的，术语“导电的(conductive)”、“导电的(electricallyconductive)”以及“导电性(electrical conductivity)”指代传输电流的能力。导电材料通常指示表现出对电流流动几乎没有或没有阻碍的那些材料。电导率的一种量度是西门子每米(S/m)。通常，导电材料是电导率大于约104S/m，如至少105S/m或至少106S/m的导电材料。材料的电导率有时可能随温度变化。除非另有说明，否则材料的电导率是在室温下测量的。
另外，量、比率和其它数值在本文中有时以范围格式呈现。应当理解的是，此范围格式是为了方便和简洁而使用的，并且应该灵活地理解为包含明确指定为范围的界限的数值，而且还包含所述范围内涵盖的所有单独数值或子范围，如同每个数值和子范围被明确指定一样。
虽然已经参考本公开的具体实施例描述和展示了本公开，但是这些描述和说明不是限制性的。本领域技术人员应当理解，在不脱离如由权利要求限定的本公开的精神和范围的情况下，可以作出各种改变并且可以取代等同物。图示可能不一定按比例绘制。由于制造工艺和公差，本公开中的艺术再现与实际装置之间可能存在区别。可能存在未具体展示的本公开的其它实施例。可以存在未具体展示的本公开的其它实施例。可以作出修改以使特定情况、材料、物质构成、方法或过程适于本公开的目标、精神和范围。所有这种修改均旨在落入所附权利要求的范围内。虽然已经参考以特定顺序执行的特定操作描述了本文所公开的方法，但是应理解，可以在不脱离本公开的教导的情况下对这些操作进行组合、细分或重新排列以形成等效方法。因此，除非本文明确指出，否则操作的顺序和分组并不是本公开的限制。

Claims (20)

1.一种衬底结构，其包括：
衬底；
第一电子组件，所述第一电子组件安置在所述衬底内；
第二电子组件，所述第二电子组件安置在所述衬底内并且与所述第一电子组件一起在水平方向上排列；以及
多个金属层，所述多个金属层安置在所述衬底的上表面的上方，其中所述第一电子组件上方的金属层的数量大于所述第二电子组件上方的金属层的数量。
2.根据权利要求1所述的衬底结构，其中所述第一电子组件和所述第二电子组件由所述衬底彼此分离。
3.根据权利要求1所述的衬底结构，其中所述第一电子组件的厚度小于所述第二电子组件的厚度。
4.根据权利要求1所述的衬底结构，其中所述金属层包括第一金属层和第二金属层，所述第一金属层覆盖所述第一电子组件，所述第二金属层覆盖所述第一电子组件、所述第一金属层和所述第二电子组件。
5.根据权利要求4所述的衬底结构，其中所述第一金属层的厚度大于所述第二金属层的厚度。
6.根据权利要求1所述的衬底结构，其中所述衬底的厚度基本上等于所述第一电子组件的厚度。
7.根据权利要求6所述的衬底结构，其中所述衬底的所述厚度小于所述第二电子组件的厚度。
8.根据权利要求1所述的衬底结构，其中所述第一电子组件上方的金属层的数量等于所述衬底上方的金属层的数量。
9.根据权利要求4所述的衬底结构，其中所述第二电子组件包括第一端子，所述第一端子安置在所述第二电子组件的上表面上，并且所述第二电子组件的所述第一端子与所述第一金属层基本上共面。
10.根据权利要求1所述的衬底结构，其中所述第一电子组件的水平中心轴线与所述第二电子组件的水平中心轴线基本上共面。
11.根据权利要求1所述的衬底结构，其中所述衬底结构具有第一部分，所述第一部分位于所述第一电子组件的垂直投影方向处，并且所述衬底结构的所述第一部分相对于所述第一电子组件的水平中心轴线对称。
12.根据权利要求11所述的衬底结构，其中所述衬底结构具有第二部分，所述第二部分位于所述第二电子组件的垂直投影方向处，并且所述衬底结构的所述第二部分相对于所述第二电子组件的水平中心轴线对称。
13.根据权利要求1所述的衬底结构，其中所述第一电子组件的上表面与所述衬底结构的上表面之间的距离基本上等于所述第一电子组件的下表面与所述衬底结构的下表面之间的距离。
14.一种半导体封装结构，其包括：
衬底结构，所述衬底结构包括：
衬底，
第一电子组件，所述第一电子组件安置在所述衬底内，以及
第二电子组件，所述第二电子组件安置在所述衬底内并且与所述第一电子组件在水平方向上排列，
其中所述第一电子组件的厚度小于所述第二电子组件的厚度；
第一重布结构，所述第一重布结构安置在所述衬底结构的上表面上；
第一半导体芯片，所述第一半导体芯片安置在所述第一重布结构上；以及
包封料，所述包封料覆盖所述第一半导体芯片和所述第一重布结构。
15.根据权利要求14所述的半导体封装结构，其进一步包括：
第二重布结构，所述第二重布结构安置在所述衬底结构的下表面上；
第二半导体芯片，所述第二半导体芯片安置在所述第二重布结构上；以及
多个焊球，所述多个焊球安置在所述第二重布结构上。
16.根据权利要求14所述的半导体封装结构，其中所述第一电子组件的水平中心轴线与所述第二电子组件的水平中心轴线基本上共面。
17.一种用于制造衬底结构的方法，所述方法包括：
提供具有第一空腔的核心衬底；
在所述第一空腔中安置第一电子组件；
形成覆盖并电连接到所述第一电子组件的第一金属层；
形成穿透所述核心衬底的第二空腔；
在所述第二空腔中安置第二电子组件；以及
形成覆盖并电连接到所述第一电子组件和所述第二电子组件的第二金属层。
18.根据权利要求17所述的方法，其中形成覆盖并电连接到所述第一电子组件的所述第一金属层包括：
形成覆盖所述核心衬底和所述第一电子组件并填充所述第一空腔的第一介电层；
在所述第一介电层中形成开口以暴露所述第一电子组件的端子；以及
在所述第一介电层上形成所述第一金属层并且在所述开口中形成第一导电通孔，其中所述第一金属层接触所述第一导电通孔。
19.根据权利要求17所述的方法，其中形成覆盖并电连接到所述第一电子组件和所述第二电子组件的所述第二金属层包括：
形成覆盖所述第一金属层并填充所述第二空腔的第二介电层；
在所述第二介电层中形成多个开口以暴露所述第一金属层和所述第二电子组件的端子；以及
在所述第二介电层上形成所述第二金属层并且在所述开口中形成多个第二导电通孔，其中所述第二金属层接触所述第二导电通孔。
20.根据权利要求18所述的方法，其进一步包括：
控制所述第一金属层的厚度，使得所述第一金属层和所述第二电子组件的端子位于同一高度。
CN202110648531.1A 2020-06-11 2021-06-10 衬底结构和其形成方法以及半导体封装结构 Pending CN113809059A (zh)

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