TWI523126B - 在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法 - Google Patents

在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法 Download PDF

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TWI523126B
TWI523126B TW099123389A TW99123389A TWI523126B TW I523126 B TWI523126 B TW I523126B TW 099123389 A TW099123389 A TW 099123389A TW 99123389 A TW99123389 A TW 99123389A TW I523126 B TWI523126 B TW I523126B
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substrate
semiconductor package
conductive layer
semiconductor
cte
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TW099123389A
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TW201133657A (en
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林耀劍
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史達晶片有限公司
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法
本發明一般有關於半導體裝置，以及更特別是有關於在包含封膠之印刷電路板或基板中、或在具有與大陣列晶圓級晶片尺寸封裝(WLCSP)之熱膨脹係數相似熱膨脹係數之空白晶粒上形成孔穴的半導體裝置和方法。
在現代電子產品中通常可以發現半導體裝置。半導體裝置電性組件之數目與密度可以改變。離散半導體裝置通常包括一種形式電性組件，例如：發光二極體(light emitting diode，LED)、小信號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效應電晶體(metal oxide semiconductor field effect transistor，MOSFET)。積體半導體裝置典型地包括數百個至數百萬個電性組件。積體半導體裝置之例包括：微控制器、微處理器、電荷耦合裝置(charged-coupled device，CCD)、太陽能電池以及數位微鏡裝置(digital micro-mirror device，DMD)。
半導體裝置實施廣大範圍之功能，例如：高速計算、發射與接收電磁信號、控制電子裝置、將陽光轉變成電力以及產生用於電視顯示之視覺投影。在娛樂、通訊、電力轉換、網路、電腦以及消費者產品之領域中可以發現半導體裝置。在軍事應用、航空、汽車、工業控制器以及辦公室設備中亦可以發現半導體裝置。
半導體裝置使用半導體材料之電氣性質。此半導體材料之原子結構允許其導電率藉由施加電場或基極電流、或經由掺雜過程而操控。掺雜會將雜質導入於半導體材料中，以操縱且控制半導體裝置之導電率。
半導體裝置包括主動與被動電性結構。主動結構包括雙載子電晶體與場效應電晶體，其控制電流之流動。藉由改變掺雜以及施加電場或基極電流之位準，電晶體可以增強或限制電流之流動。被動結構包括：電阻器、電容器以及電感器，其在實施各種所需電性功能之電壓與電流之間產生關係。將此等被動與主動結構電性連接以形成電路，其使得半導體裝置能夠實施高速計算與其他有用功能。
通常使用兩個複雜製造過程以製造半導體裝置，即前端製造過程與後端製造過程，其各可能涉及數百個步驟。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒(die)。各晶粒典型地相同，且包含藉由將主動與被動組件電性連接所形成之電路。後端製造過程涉及將所完成晶圓單一化成個別晶粒，且將此等晶粒封裝以提供結構支持與環境隔離。
半導體製造之一目標為產生較小半導體裝置。較小裝置典型地消耗較少功率，具有較高性能表現，且可以更有效率地製造。此外，較小半導體裝置具有較小佔用空間(footprint)，此對於較小終端產品為令人所欲。可以藉由在前端製造過程中之改善以達成較小晶粒尺寸，以導致具有較小尺寸且較高密度主動與被動組件之晶粒。後端製造過程可以藉由在電性互連與封裝材料中之改善，以導致具有較小佔用空間之半導體裝置封裝。
在晶圓級晶片尺寸封裝(WLCSP)與擴張晶圓級晶片尺寸封裝(fan-out WLCSP，FO-WLCSP)中，將半導體晶粒堆疊且在封裝中垂直互連。當所需要之信號處理能力增加時，通常將大陣列堆疊半導體晶粒安裝於WLCSP與FO-WLCSP之中。然後，將大陣列WLCSP/FO-WLCSP安裝至印刷電路板(PCB)。然而，大陣列WLCSP/FO-WLCSP特別是在溫度循環測試期間，會造成故障與降低之電路板位準可靠度，此部份是由於在PCB與大陣列WLCSP/FO-WLCSP之間熱膨脹係數(coefficient of thermal expansion，CTE)匹配不良所導致應力所造成。
因此對於在印刷電路板(PCB)上之大陣列WLCSP/FO-WLCSP存在一種需求，使其不會不利地影響電路板位準可靠度。因此，在一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：提供一基板；在基板之第一表面中形成一孔穴；將具有CTE之封膠沉積於此孔穴中；在此基板與封膠上形成一絕緣層；將此絕緣層之一部份去除以曝露封膠；在此封膠上形成一第一導電層；以及將此具有CTE之半導體封裝安裝於此孔穴上。將此半導體封裝電性地連接至第一導電層。選擇此封膠之CTE以類似於半導體封裝之CTE，以減少在半導體封裝與基板間之應力。
在另一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：提供一基板；在基板之第一表面中形成一孔穴；將具有CTE之應力補償結構安裝於此孔穴中；在此基板與應力補償結構上形成一絕緣層；將此絕緣層之一部份去除，以曝露應力補償結構；在此應力補償結構上形成一導電層；以及將此具有CTE之半導體封裝安裝於此孔穴上。將此半導體封裝電性地連接至此導電層。選擇此應力補償結構之CTE以類似於半導體封裝之CTE，以減少在半導體封裝與基板間之應力。
在另一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：提供一基板；在基板之第一表面中形成一孔穴；將具有CTE之應力補償結構沉積於此孔穴中；在應力補償結構上形成一導電層；以及將此具有CTE之半導體封裝安裝於此孔穴上。將此半導體封裝電性地連接至此導電層。選擇此應力補償結構之CTE以類似於半導體封裝之CTE，以減少在半導體封裝與基板間之應力。
在另一實施例中，本發明為一種半導體裝置，其包括：一基板，其具有在基板之第一表面中所形成之孔穴；一應力補償結構，其具有CTE而設置於此孔穴中；導電層，形成於應力補償結構上；以及半導體封裝，其具有CTE而安裝於此孔穴上。將此半導體封裝電性地連接至此導電層。選擇此應力補償結構之CTE以類似於半導體封裝之CTE，以減少在半導體封裝與基板間之應力。
本發明在以下一或更多實施例中參考所附圖式說明，其中，相同號碼代表相同或類似元件。雖然，本發明是以達成本發明目的之最佳模式說明，然而，熟習此技術人士瞭解，其用意為包含各種替代、修正以及等同，而此等替代、修正、等同是包含於由所附申請專利範圍與其等同物所界定本發明精神與範圍中，且由以下揭示內容與圖式所支持。
通常使用兩個複雜製造過程以製造半導體裝置：前端製造過程與後端製造過程。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒(die)。在晶圓上之各晶粒包含主動與被動電性組件，其電性連接以形成功能性電路。主動電性組件例如為電晶體與二極體，其具有能力以控制電流之流動。被動電性組件例如為電容器、電感器、電阻器以及變壓器，其在實施所須電路功能之電壓與電流之間產生關係。
此等被動與主動組件藉由一系列製程步驟形成於半導體晶圓之表面上，此等步驟包括：掺雜、沉積、微影術、蝕刻以及平坦化。掺雜藉由例如，離子植入或熱擴散之技術，將雜質導入於半導體材料中。此掺雜過程可以改變在主動元件中之半導體材料之導電率，將半導體材料轉換成絕緣體、導電體，或動態地改變半導體材料導電率，以響應於電場或基極電流。電晶體包括改變型式與掺雜程度之區域，其如同所需地配置，以使得在施加電場或基極電流時，電晶體可以增強或限制電流之流動。
主動與被動組件可以由具有不同電氣性質之材料層所形成。此等層可以藉由各種沉積技術所形成，此技術部份地由所沉積材料之型式所決定。例如，薄膜沉積可以涉及：化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解質電鍍以及無電極電鍍過程。通常將各層圖案化以形成：主動組件、被動組件或組件間電性連接之部份。
可以使用微影術將此等層圖案化，其涉及將光敏感材料例如光阻沉積在被圖案化之層上。使用光線將圖案由光罩移轉至光阻。使用溶劑將受光線照射之光阻圖案之部份去除，以曝露被圖案化下層之部份。將光阻之剩餘部份去除，以留下圖案化層。以替代方式，可以使用例如無電極與電解質電鍍技術，藉由將材料直接沉積於由先前沉積/蝕刻過程所形成區域或洞孔中，將一些形式材料圖案化。
將薄膜材料沉積於現有圖案上，會擴大下面圖案，且產生不均勻之平坦表面。通常需要均勻平坦表面，以產生較小且更密集封裝之主動與被動組件。可以使用平坦化(planarization)將材料從晶圓表面去除，以產生均勻平坦表面。平坦化涉及以拋光墊將晶圓表面拋光。在拋光期間，將研磨材料與腐蝕性化學物質添加至晶圓表面。此研磨之機械作用與化學物質之腐蝕作用之組合，將晶圓表面任何不規則形狀去除，以產生均勻平坦表面。
後端製造過程是指，將所完成晶圓切割或單一化成為個別晶粒，以及然後將此晶粒封裝用於結構支持與環境隔離。為了將此晶粒單一化，將晶圓沿著此稱為鋸道或劃線之晶圓無功能區域劃線且分開。使用雷射切割工具或鋸刀將晶圓單一化。在單一化之後，將個別晶粒安裝至封裝基板，此基板包括接腳或接觸墊，用於與其他系統組件互連。然後，將此半導體晶粒上所形成之接觸墊連接至此封裝中之接觸墊。此電性連接可以焊料突起、柱(stud)突起、導電漿或接線製成。將封膠或其他模製材料沉積在封裝上，以提供實體支持與電性隔離。然後，將此所完成封裝插入於電性系統中，且使得此半導體裝置功能可供其他系統組件使用。
圖1說明具有晶片載體基板或印刷電路板(PCB) 52之電子裝置50，此基板或電路板具有複數個安裝於其表面上之半導體封裝。取決於應用，此電子裝置50可以具有一種型式半導體封裝或多種型式半導體封裝。用於說明目的，圖1中顯示不同型式半導體封裝。
電子裝置50可以為獨立式(stand-alone)系統，其使用半導體封裝以實施一或更多電性功能。以替代方式，電子裝置50可以為一較大系統之次組件。例如，電子裝置50為可以插入於電腦中之圖形卡、網路介面卡、或其他信號處理卡。半導體封裝可以包括微處理器、記憶體、特殊用途積體電路(ASIC)、邏輯電路、類比電路、射頻(RF)電路、離散裝置或其他半導體晶粒或電性組件。
在圖1中，PCB 52提供一般基板，用於安裝在於PCB上半導體封裝之結構支持與電性互連。使用蒸鍍、電解質電鍍、無電極電鍍、絲網印刷、或其他適當金屬沉積過程，在PCB 52之表面上或層中形成導電信號跡線54。
信號跡線54提供在各半導體封裝、安裝組件以及其他外部系統組件之間之電性連通。跡線54亦提供功率與接地連接給各半導體封裝。
在一些實施例中，半導體裝置具有兩個封裝位準。第一位準封裝為一種技術，用於將半導體晶粒機械地與電性地裝附於一中間載體。第二位準封裝是關於將中間載體機械地與電性地裝附於PCB。在其他實施例中，半導體裝置僅具有第一位準封裝，而將晶粒機械地與電性地直接裝附於PCB。
為了說明目的而顯示，在PCB 52上數種型式第一位準封裝，其包括接線封裝56與覆晶58。此外，顯示在PCB 52上數種型式第二位準封裝，其包括：球格柵陣列(ball grid array，BGA)60、突起晶片載體(bump chip carrier，BCC)62、雙內線封裝(dual in-line package，DIP)64、平面格柵陣列(land grid package，LGA)66、多晶片模組(multi-chip module，MCM)68、四方形扁平無接腳封裝(quad flat non-leaded package，QFN)70以及四方形扁平封裝72。取決於系統需求，可以將半導體封裝之任何組合、以第一與第二位準封裝型式之任何組合而組態，而將其與其他電子組件一起連接至PCB 52。在一些實施例中，電子裝置50包括單一裝附半導體封裝，而其他實施例需要多個互連封裝。藉由將一或更多個半導體封裝組合於單一基板上，製造商可以將預製組件合併於電子裝置與系統中。因為半導體封裝包括複雜功能，可以使用較便宜組件與合理化製程以製造電子裝置。此所產生之裝置較不可能故障且可便宜製造，導致對於消費者較低成本。
圖2a-2c顯示典範半導體封裝。圖2a說明安裝於PCB 52上DIP 64之進一步細節。半導體晶粒74包括：一主動區域，其所包含類比或數位電路執行作為形成於晶粒中之主動元件、被動元件、導電層以及介電層，且根據晶粒之電性設計而電性互連。例如，電路可以包括：一或更多個電晶體、二極體、電感器、電容器、電阻器以及形成於半導體晶粒74主動區域中之其他電路元件。接觸墊76為一或更多層導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，且電性連接至形成於半導體晶粒74中之電路元件。在DIP 64組裝期間，使用金-矽共晶層或黏著材料例如熱環氧樹脂，將半導體晶粒74安裝至一中間載體78。封裝體包括絕緣封裝材料，例如聚合物或陶瓷。導線80與接線82提供半導體晶粒74與PCB 52間之電性互連。封膠84沉積在封裝上，其藉由防止濕氣與粒子進入封裝且污染晶粒74與接線82而作環境保護。
圖2b說明安裝在PCB 52上BCC 62之進一步細節。使用底部填料或環氧樹脂黏著材料92，將半導體晶粒88安裝在載體90上。接線94提供接觸墊96與98間之第一位準封裝互連。將模製複合物或封膠100沉積在半導體晶粒88與接線94上，以提供用於此裝置之實體支持與電性隔離。使用適當金屬沉積過程，例如電解質電鍍或無電極電鍍過程以防止氧化，於PCB 52之表面上形成接觸墊102。將接觸墊102電性連接至PCB 52中一或更多個導電信號跡線54。在BCC 62之接觸墊98與PCB 52之接觸墊102之間形成突起104。
在圖2c中，半導體晶粒58面向下安裝在具有覆晶型式第一位準封裝之中間載體106。半導體晶粒58之主動區域108包括類比或數位電路，其根據晶粒之電性設計，執行作為所形成之主動元件、被動元件、導電層以及介電層。例如，電路可以包括一或更多個電晶體、二極體、電感器、電容器、電阻器以及在主動區域108中之其他電路元件。半導體晶粒58經由突起110而電性地與機械地連接至載體106。
使用突起112，將BGA 60電性地且機械地連接至具有BGA型式第二位準封裝之PCB 52。經由突起110、信號線114以及突起112，將半導體晶粒58電性連接至在PCB 52中之導電信號跡線54。將模製複合物或封膠116沉積在半導體晶粒58與載體106上，以提供用於此裝置之實體支持與電性隔離。此覆晶半導體裝置提供從在半導體晶粒58上主動元件至在PCB 52上導電軌之短的導電路徑，以便縮短信號傳送距離、降低電容以及改善整個電路之性能表現。在另一實施例中，可以使用覆晶型式第一位準封裝而無需中間載體106，將半導體晶粒58電性地且機械地直接連接至PCB 52。
圖3a-3d說明有關於圖1與圖2a-2c之過程，而在PCB中形成孔穴或以封膠裝滿基板，此封膠之熱膨脹係數(CTE)實質上類似於或匹配安裝於此孔穴上WLCSP或FO-WLCSP之熱膨脹係數。在圖3a中，PCB或基板120為用於電子組件之機械支持結構，其具有根據PCB設計之點-至-點電性互連。PCB 120具有以一非導電或介電質基板而堆疊之一或多個導電層122，此基板可以為一或更多個預浸漬(prepreg)聚四氟乙烯之堆疊層，其具有酚醛棉紙、環氧樹脂、樹脂、編織玻璃、毛玻璃、聚脂以及其他加強纖維或織物之組合。PCB 120具有高的介電常數、低的損耗角正切、以及大約2.15g/cm3之密度。導電層122可以為由電解質電鍍或無電極電鍍所形成而由以下材料所構成之一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料，而用於電性互連。PCB 120與導電層122之佈局典型地使用絲網印刷、光蝕刻、PCB研磨、無電極電鍍或電解質電鍍過程。PCB 120可以具有以鑽頭或雷射鑽孔所切割之複數個通孔。導電層122從PCB 120之頂表面124延伸至底表面126。
在表面124中形成孔穴128，其所具有面積大約為稍後安裝於此孔穴上半導體封裝140之相同尺寸。孔穴128可以由雷射、鑽孔、槽刨(router)、切削或劃線所形成。在一實施例中，對於具有厚度為100-800微米(μm)之PCB 120，可以形成孔穴128之深度為50-600μm。
在圖3a中使用漿料印刷、壓擠模製、移轉模製、液體封膠模製、真空堆疊、旋轉塗佈或其他適當塗佈劑，將封膠或糢製複合物130沉積在孔穴128中。封膠130可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹脂丙烯酸脂、或具有適當填料之聚合物。在一實施例中，藉由在準確容量控制下之射出配置過程，配置適當數量封膠130，而將封膠130配置於孔穴128中。如同於圖3b中所示，將所配置之封膠模製至與PCB 120頂表面124共平面之位準。
在圖3c中，在PCB 120與封膠130上形成選擇性之絕緣或鈍化層132。絕緣層132可以為一或多層之光敏絕緣聚合物材料。此絕緣層132是使用堆疊、印刷、旋轉塗佈或噴灑塗佈而形成。藉由蝕刻過程或雷射鑽孔將絕緣層132之一部份去除，以曝露導電層122與封膠130。
使用圖案化與金屬沉積過程例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解質電鍍、無電極電鍍過程，在導電層122、封膠130以及絕緣層132上形成導電層134。導電層134可以為由以下材料所形成之一或多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料。將導電層134之一部份電性連接至導電層122。取決於半導體裝置之設計與功能，導電層134之其他部份可以為電性連接或電性隔離。
在PCB 120上形成焊料遮罩層136，其具有開孔以曝露導電層134，用於下一位準之互相連接。焊料遮罩層136中 之開孔並不會與絕緣層132之開孔準確地重疊。
使用蒸鍍、電解質電鍍、無電極電鍍、球滴或絲網印刷過程，將導電突起材料沉積在PCB 120之底表面126上，且電性連接至導電層122。此突起材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料以及其組合，而具有選擇性的助焊劑溶液。例如，此突起材料可以為共晶Sn/Pb、高鉛焊料或無鉛焊料。使用適當裝附或接合過程，將突起材料接合至導電層122。在一實施例中，藉由將材料加熱至其熔點以上而使得突起材料回焊，以形成球體或突起138。在一些應用中，此突起138第二次回焊，以改善至導電層122之電性接觸。突起亦可以被壓擠接合至導電層122。突起138代表可以形成於導電層122上之一種形式互連結構。此互連結構亦可使用在PCB 120頂表面或底表面上之接線、柱突起、微突起、或其他電性互連。
在圖3d中，半導體封裝或組件140安裝於孔穴128上。此孔穴包括封膠130而具有朝向PCB 120之接觸墊142。半導體封裝140為WLCSP或FO-WLCSP，其包含大陣列之堆疊半導體晶粒。各半導體晶粒包括類比或數位電路，其可以執行作為形成於晶粒中之主動元件、被動元件、導電層以及介電層，且根據晶粒之電性設計與功能而電性互連。例如，此電路可以包括形成於晶粒主動表面中之一或更多個電晶體、二極體以及其他電路元件，以執行類比電路或數位電路，例如：數位信號處理器(digital signal processor，DSP)、特殊用途積體電路(ASIC)、記憶體或其他信號處理電路。半導體封裝140亦包含整合式被動元件(IPD)，例如：電感器、電容器以及電阻器，用於射頻(RF)信號處理。典型的射頻(RF)系統需要在一或更多個半導體封裝中之多個IPD，以實施所需要之電性功能。突起146將接觸墊142電性連接至導電層134。突起146可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料以及其組合。
如同於圖3a-3d中說明，電子系統148具有安裝於PCB 120中孔穴128上之半導體封裝140。此半導體封裝140為WLCSP或FO-WLCSP，其包含大陣列之堆疊半導體晶粒，用於額外信號處理能力。半導體封裝140具有基礎材料例如：矽、鍺、砷化鎵、磷化銦或碳化矽，而用於結構支持。封膠130為一種應力補償結構，其被選擇具有熱膨脹係數(CTE)實質上類似或匹配半導體封裝140基礎材料之熱膨脹係數(CTE)，例如，矽之熱膨脹係數為2-10 x 10-6/℃。此電子系統148之可靠度可以藉由將半導體封裝140安裝在以封膠130所填入之孔穴128上而加強，因為選擇封膠之CTE類似於半導體封裝基礎材料之CTE。任何由於溫度變化之半導體封裝140之膨脹或收縮經由導電層134傳送，且藉由具有類似熱膨脹性質之封膠130而補償。半導體封裝140與封膠130實質上類似之CTE，特別是在溫度循環測試期間，可以減少應力與相關故障。
圖4顯示安裝於PCB或基板之孔穴中之空白晶粒。此空白晶粒所具有CTE實質上類似或匹配安裝於孔穴上WLCSP或FO-WLCSP之CTE。PCB或基板150對於電子組件提供機械支持結構，其根據PCB之設計具有點-對-點之電性互連。PCB 150具有一或多個導電層152，而與非導電或介電基板堆疊。此基板可以為一或更多個預浸漬(prepreg)聚四氟乙烯之堆疊層，其具有酚醛棉紙、環氧樹脂、樹脂、編織玻璃、毛玻璃、聚脂以及其他加強纖維或織物之組合。PCB 150具有高的介電常數、低的損耗角正切以及大約2.15g/cm3之密度。導電層152可以為藉由電解質電鍍或無電極電鍍所形成而由以下材料所構成之一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料，而用於電性互連。PCB 150與導電層152之布局典型地使用絲網印刷、光蝕刻、PCB研磨、無電極電鍍或電解質電鍍過程。PCB 150可以具有以鑽頭或雷射鑽孔所切割之複數個通孔。導電層152從PCB 150之頂表面154延伸至底表面156。
在表面154中形成孔穴158，其所具有面積大約為稍後安裝於此孔穴上半導體晶粒之相同尺寸。孔穴158可以由雷射、鑽孔、槽刨(router)、切削或劃線所形成。在一實施例中，對於具有厚度為100-800微米(μm)之PCB 150，可以形成孔穴158之深度為50-600μm。
空白晶粒160是以晶粒封裝黏著劑162安裝於孔穴158中。空白晶粒160可以具有主動表面或非主動表面。例如，空白晶粒可以僅具有在其表面上之電感器。可以使用漿料印刷、壓擠模製、移轉模製、液體封膠模製、真空堆疊、旋轉塗佈或其他適當塗佈劑，將選擇性封膠或糢製複合物沉積在空白晶粒160周圍。封膠130可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹脂丙烯酸脂或具有適當填料之聚合物。空白晶粒160之頂部表面是與頂部表面154共平面。
將絕緣層或鈍化層164形成於PCB 150與空白晶粒160上。絕緣層164可以為一或更多層之光敏絕緣聚合物材料。絕緣層164是使用堆疊、印刷、旋轉塗佈或噴灑塗佈所形成。藉由蝕刻過程或雷射鑽孔將絕緣層164之一部份去除，以曝露導電層152與空白晶粒160。
使用圖案化與金屬沉積過程例如：PVD、CVD、濺鍍、電解質電鍍、無電極電鍍過程，在導電層152、空白晶粒160以及絕緣層164上形成導電層166。導電層166可以為一或多層之鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料。將導電層166之一部份電性連接至導電層152。取決於半導體裝置之設計與功能，導電層166之其他部份可以為電性連接或電性隔離。
在PCB 160上形成焊料遮罩層168，其具有開孔以曝露導電層166，用於下一位準之互相連接。焊料遮罩層168中之開孔並不會與絕緣層164中之開孔準確地重疊。
使用蒸鍍、電解質電鍍、無電極電鍍、球滴(ball drop)或絲網印刷過程，將導電突起材料沉積在PCB 150之底表面156上，且電性連接至導電層152。此突起材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料以及其組合，而具有選擇性的助焊劑溶液。例如，此突起材料可以為共晶Sn/Pb、高鉛焊料、或無鉛焊料。使用適當裝附或接合過程，將突起材料接合至導電層152。在一實施例中，藉由將材料加熱至其熔點以上而使得突起材料回焊，以形成球體或突起170。在一些應用中，此突起170第二次回焊，以改善至導電層152之電性接觸。突起亦可以被壓擠接合至導電層152。突起170代表可以形成於導電層122上一種形式互連結構。此互連結構亦可使用接線、柱突起、微突起或其他電性互連。
半導體封裝或組件172安裝於孔穴158上，其包含空白晶粒160而具有朝向PCB 150之接觸墊174。半導體封裝172為WLCSP或FO-WLCSP，其包含複數個堆疊半導體晶粒。各半導體晶粒包括類比或數位電路，其可以執行作為主動元件、被動元件、導電層以及形成於晶粒中之介電層，且根據晶粒之電性設計與功能而電性互連。例如，此電路可以包括形成於晶粒主動表面中之一或更多個電晶體、二極體以及其他電路元件，以執行類比電路或數位電路，例如：數位信號處理器(DSP)、特殊用途積體電路(ASIC)、記憶體或其他信號處理電路。半導體封裝172亦包含IPD，例如：電感器、電容器、以及電阻器，用於射頻(RF)信號處理。典型的射頻(RF)系統需要在一或更多個半導體封裝中之多個IPD，以實施所需要之電性功能。突起178將接觸墊174電性連接至導電層166。突起178可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料以及其組合。
電子系統180具有安裝於PCB 150中孔穴158上之半導體封裝172。此半導體封裝172為WLCSP或FO-WLCSP，其包含大陣列之堆疊半導體晶粒，用於其他信號處理能力。半導體封裝172具有用於結構支持之基礎材料例如：矽、鍺、砷化鎵、硫化銦或碳化矽。具有選擇性封膠之空白晶粒160為一種應力補償結構，其被選擇而其具有熱膨脹係數(CTE)實質上類似或匹配半導體封裝172基礎材料之熱膨脹係數(CTE)，例如，矽之熱膨脹係數為2-10 x 10-6/℃。此電子系統180之可靠度可以藉由將半導體封裝172安裝在包含空白晶粒160之孔穴128上而加強，此因為選擇空白晶粒之CTE類似於半導體封裝基礎材料之CTE。任何由於溫度變化之半導體封裝172之膨脹或收縮經由導電層134傳送，且由具有類似熱膨脹性質之空白晶粒160而補償。半導體封裝172與空白晶粒160實質上類似之CTE，特別是在溫度循環測試期間，可以減少應力與相關故障。
以上已經詳細說明本發明之一或更多個實施例，熟習此技術人士瞭解，可以對於此等實施例作修正與調整，而不會偏離以下申請專利範圍中所設定本發明之範圍。
50‧‧‧電子裝置
52‧‧‧印刷電路板(PCB)
54‧‧‧信號跡線
56‧‧‧接線封裝
58‧‧‧覆晶
60‧‧‧球格柵陣列(BGA)
62‧‧‧突起晶片載體(BCC)
64‧‧‧雙內線封裝(DIP)
66‧‧‧平面格柵陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧四方形扁平無接腳封裝(QFN)
72‧‧‧四方形扁平封裝
76‧‧‧接觸墊
78‧‧‧中間載體
80．．．導線
82．．．接線
84．．．封膠
88．．．半導體晶粒
90．．．載體
92．．．底部填料
94．．．接線
96．．．接觸墊
98．．．接觸墊
100．．．模製複合物
102．．．接觸墊
104．．．突起
106．．．中間載體
108．．．主動區域
110．．．突起
112．．．突起
114．．．信號線
116．．．模製複合物
118．．．半導體晶圓
120．．．印刷電路板(PCB)
122．．．導電層
124．．．頂表面
126．．．底表面
128．．．孔穴
130．．．封膠
132．．．絕緣層
134．．．導電層
136．．．焊料遮罩層
138．．．球體
140．．．半導體封裝
142．．．接觸墊
146．．．突起
148．．．電子系統
150．．．印刷電路板(PCB)
152．．．導電層
154．．．頂表面
156．．．底表面
158．．．孔穴
160．．．空白晶粒
162．．．晶粒裝附黏著劑
164．．．絕緣層
166．．．導電層
168．．．焊料遮罩層
170．．．球體
172．．．半導體封裝
174．．．接觸墊
178．．．突起
180．．．電性系統
圖1說明一種印刷電路板(PCB)，其具有安裝至其表面之不同形式封裝； 圖2a-2c說明安裝至PCB之典範半導體封裝之進一步細節；圖3a-3d說明在裝有封膠之PCB中形成孔穴之過程，此封膠所具有CTE與在孔穴上所安裝FO-WLCSP之CTE匹配；以及圖4說明一種印刷電路板(PCB)，其具有孔穴包含一空白晶粒，此空白晶粒之CTE與在孔穴上所安裝FO-WLCSP之CTE匹配。
150．．．印刷電路板(PCB)
152．．．導電層
154．．．頂表面
156．．．底表面
158．．．孔穴
160．．．空白晶粒
162．．．晶粒裝附黏著劑
164．．．絕緣層
166．．．導電層
168．．．焊料遮罩層
170．．．球體
172．．．半導體封裝
174．．．接觸墊
178．．．突起
180．．．電性系統

Claims (14)

  1. 一種製造半導體裝置之方法，其包括以下步驟：提供一基板；在該基板之一第一表面中形成一孔穴；將非導電封膠沉積於該孔穴中；在該基板與該非導電封膠上形成一絕緣層；將該絕緣層之一部份去除，以曝露該非導電封膠；在該非導電封膠上形成一第一導電層；以及將一半導體封裝安裝於該孔穴上，將該半導體封裝電性地連接至該第一導電層，其中，選擇該非導電封膠之熱膨脹係數(CTE)以類似於該半導體封裝之該熱膨脹係數，以減少在該半導體封裝與該基板間之應力。
  2. 如申請專利範圍第1項之方法，更包括：在該第一導電層上形成一焊料遮罩層。
  3. 如申請專利範圍第1項之方法，更包括：在該半導體封裝與該第一導電層之間形成突起。
  4. 如申請專利範圍第1項之方法，更包括：在該基板中形成一第二導電層；以及該基板具有相對於該第一表面之一第二表面，在該第二表面上形成複數個突起，將該第二導電層電性連接至該等突起。
  5. 如申請專利範圍第1項之方法，更包括：以一射出配置過程沉積該非導電封膠；以及將該非導電封膠與該基板之該第一表面共平面地模 製。
  6. 一種製造半導體裝置之方法，其包括以下步驟：提供一基板；在該基板之一第一表面中形成一孔穴；將包含一絕緣材料或是一空白晶粒的一應力補償結構設置於該孔穴中；在該基板與該應力補償結構上形成一絕緣層；將該絕緣層之一部份去除，以曝露該應力補償結構；在該應力補償結構上形成一導電層；以及將一半導體封裝安裝於該孔穴上，將該半導體封裝電性地連接至該導電層，其中，選擇該應力補償結構之熱膨脹係數以類似於該半導體封裝之該熱膨脹係數，以減少在該半導體封裝與該基板間之應力。
  7. 如申請專利範圍第6項之方法，其中該應力補償結構包括一封膠。
  8. 如申請專利範圍第7項之方法，更包括：以一射出配置過程沉積該封膠；以及將該封膠與該基板之該第一表面共平面地模製。
  9. 如申請專利範圍第6項之方法，其中該應力補償結構是與該基板的該第一表面共平面。
  10. 一種半導體裝置，包括：一基板，其包含在該基板之一第一表面中所形成之一孔穴；一應力補償結構，其包含一絕緣材料或是一空白晶粒 且設置於該孔穴中；一導電層，形成於該應力補償結構上；以及一半導體封裝，其安裝於該孔穴上，將該半導體封裝電性地連接至該導電層，其中，選擇該應力補償結構之熱膨脹係數以類似於該半導體封裝之該熱膨脹係數，以減少在該半導體封裝與該基板間之應力。
  11. 如申請專利範圍第10項之半導體裝置，其中該應力補償結構包括一封膠。
  12. 如申請專利範圍第10項之半導體裝置，其中該空白晶粒包含在其頂表面上之電感器。
  13. 如申請專利範圍第10項之半導體裝置，更包括：該半導體封裝與該導電層之間所形成之突起。
  14. 如申請專利範圍第10項之半導體裝置，其中該應力補償結構是與該基板的該第一表面共平面。
TW099123389A 2009-09-11 2010-07-16 在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法 TWI523126B (zh)

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US8895358B2 (en) 2014-11-25
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US20110062575A1 (en) 2011-03-17
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