TWI499030B - 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法 - Google Patents

在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法 Download PDF

Info

Publication number
TWI499030B
TWI499030B TW099123391A TW99123391A TWI499030B TW I499030 B TWI499030 B TW I499030B TW 099123391 A TW099123391 A TW 099123391A TW 99123391 A TW99123391 A TW 99123391A TW I499030 B TWI499030 B TW I499030B
Authority
TW
Taiwan
Prior art keywords
semiconductor
semiconductor die
conductive
die
wafer
Prior art date
Application number
TW099123391A
Other languages
English (en)
Other versions
TW201133769A (en
Inventor
Heejo Chi
Namju Cho
Hangil Shin
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW201133769A publication Critical patent/TW201133769A/zh
Application granted granted Critical
Publication of TWI499030B publication Critical patent/TWI499030B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48158—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4816—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法
本發明一般有關於半導體裝置，以及更特別是有關於在矽穿孔(TSV)插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝(WLCSMP)中半導體晶粒之半導體裝置和方法。
在現代電子產品中通常可以發現半導體裝置。半導體裝置電性組件之數目與密度可以改變。離散半導體裝置通常包括一種形式電性組件，例如：發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器以及功率金屬氧化物半導體場效應電晶體(MOSFET)。積體半導體裝置典型地包括數百個至數百萬個電性組件。積體半導體裝置之例包括：微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池以及數位微鏡裝置(DMD)。
半導體裝置實施廣大範圍之功能，例如：高速計算、發射與接收電磁信號、控制電子裝置、將陽光轉變成電力以及產生用於電視顯示之視覺投影。在娛樂、通訊、電力轉換、網路、電腦、以及消費者產品之領域中可以發現半導體裝置。在軍事應用、航空、汽車、工業控制器以及辦公室設備中亦可以發現半導體裝置。
半導體裝置使用半導體材料之電氣性質。此半導體材料之原子結構允許其導電率藉由施加電場或基極電流、或經由掺雜過程而操控。掺雜會將雜質導入於半導體材料中，以操縱且控制半導體裝置之導電率。
半導體裝置包括主動與被動電性結構。主動結構包括雙載子電晶體與場效應電晶體，其控制電流之流動。藉由改變掺雜以及施加電場或基極電流之位準，電晶體可以增強或限制電流之流動。被動結構包括：電阻器、電容器以及電感器，其在實施各種所需電性功能之電壓與電流之間產生關係。將此等被動與主動結構電性連接以形成電路，其使得半導體裝置能夠實施高速計算與其他有用功能。
通常使用兩個複雜製造過程以製造半導體裝置，即前端製造過程與後端製造過程，其各可能涉及數百個步驟。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒(die)。各晶粒典型地相同且包含藉由將主動與被動組件電性連接所形成之電路。後端製造過程涉及將所完成晶圓單一化成個別晶粒，且將此等晶粒封裝以提供結構支持與環境隔離。
半導體製造之一目標為產生較小半導體裝置。較小裝置典型地消耗較少功率，具有較高性能表現，且可以更有效率地製造。此外，較小半導體裝置具有較小佔用空間(footprint)，此對於較小終端產品為令人所欲。可以藉由改善前端製造過程以達成較小晶粒尺寸，以導致具有較小且較高密度主動與被動組件之晶粒。後端製造過程可以藉由改善電性互連與封裝材料，以導致具有較小佔用空間之半導體裝置封裝。
在晶圓級晶片尺寸模組封裝(WLCSMP)典型地包含：在用於較高裝置整合程度之有機基板或插入物之上與之間之堆疊半導體晶粒。此具有上與下堆疊半導體晶粒之WLCSMP之例可以在美國專利案號6921968、5977640以及6906415中找到。此下半導體晶粒較有機基板為薄，因此包含於封膠中。因此，難以將下半導體晶粒所產生之熱適當地驅散。當處理時，此固定有機基板需要小心照顧，以避免對此薄的半導體晶粒造成損害。此外，由於在上與下半導體晶粒以及有機基板之間熱膨脹係數(CTE)匹配不良，會重複產生翹曲的問題。
目前對於具有良好散熱能力且結實堅固可以防止翹曲之較薄之WLCSMP存在一種需求。因此，在一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：將一半導體晶圓安裝至一暫時載體；經由此半導體晶圓形成複數個TSV；經由此半導體晶圓部份地形成一孔穴；將第一半導體晶粒安裝至第二半導體晶粒；將第一與第二半導體晶粒安裝至半導體晶圓，以致於第一半導體晶粒設置在半導體晶圓上且電性連接至TSV，且此第二半導體晶粒設置在此孔穴中；將封膠沉積在半導體晶圓上以及在第一與第二半導體晶粒周圍；將封膠之一部份去除，以曝露此第一半導體晶粒之第一表面；以及將此半導體晶圓之一部份去除，以曝露TSV與此第二半導體晶粒之第一表面。此半導體晶圓之其餘部份操作為用於第一與第二半導體晶粒之TSV插入物。此方法更包括步驟，以形成在TSV插入物上之第一互連結構。
在另一實施例中，本發明為一種製造半導體裝置之方法，其包括以下步驟：提供一半導體晶圓；經由此半導體晶圓形成複數個導電通孔；在此半導體晶圓中形成第一孔穴；將第一半導體晶粒安裝至第二半導體晶粒；將第一與第二半導體晶粒安裝至半導體晶圓，以致於第一半導體晶粒設置在半導體晶圓上且電性連接至導電通孔，且此第二半導體晶粒設置在第一孔穴中；將封膠沉積在半導體晶圓上以及在第一與第二半導體晶粒周圍；以及將半導體晶圓之一部份去除，以曝露此導電通孔與第二半導體晶粒之第一表面。此半導體晶圓之其餘部份操作為用於第一與第二半導體晶粒之插入物。此方法更包括步驟，在插入物上形成第一互連結構。
在另一實施例中，本發明為一種製造半導體裝置之方法，包括以下步驟：提供一半導體晶圓；經由此半導體晶圓形成複數個導電通孔；在此半導體晶圓中形成一孔穴；將第一半導體晶粒安裝至第二半導體晶粒；將第一與第二半導體晶粒安裝至半導體晶圓，以致於第一半導體晶粒設置在半導體晶圓上且電性連接至導電通孔，且此第二半導體晶粒設置在此孔穴中；將封膠沉積在半導體晶圓上以及在第一與第二半導體晶粒上；以及半導體晶圓之一部份去除，以曝露此導電通孔與第二半導體晶粒之第一表面。此半導體晶圓之其餘部份操作為用於第一與第二半導體晶粒之插入物。
在另一實施例中，本發明為一半導體裝置，其包括：一插入物，其具有經由此插入物所形成之複數個導電通孔，與在此插入物中所形成之孔穴；一第一半導體晶粒，安裝至此插入物；一第二半導體晶粒，安裝至此第一半導體晶粒且設置於此孔穴中；一封膠，沉積於此插入物以及第一與第二半導體晶粒上，由此封膠曝露第一半導體晶粒之第一表面，且此封膠曝露第二半導體晶粒之第一表面；以及第一互連結構，形成於此插入物上。
本發明在以下一或更多實施例中參考所附圖式說明，其中，相同號碼代表相同或類似元件。雖然，本發明是以達成本發明目的之最佳模式說明，然而，熟習此技術人士瞭解，其用意為包含各種替代、修正、以及等同，而此等替代、修正、等同是包含於由所附申請專利範圍與其等同物所界定本發明精神與範圍中，且由以下揭示內容與圖式所支持。
通常使用兩個複雜製造過程以製造半導體裝置：前端製造過程與後端製造過程。前端製造過程涉及在半導體晶圓表面上形成複數個晶粒(die)。在晶圓上之各晶粒包含主動與被動電性組件，其電性連接以形成功能性電路。主動電性組件例如為電晶體與二極體，其具有能力以控制電流之流動。被動電性組件例如為電容器、電感器、電阻器以及變壓器，其在實施所須電路功能之電壓與電流之間產生關係。
此等被動與主動組件藉由一系列製程步驟形成於半導體晶圓之表面上。此等步驟包括：掺雜、沉積、微影術、蝕刻以及平坦化。掺雜藉由例如離子植入或熱擴散技術，將雜質導入於半導體材料中。此掺雜過程可以改變在主動元件中之半導體材料之導電率，將半導體材料轉換成絕緣體、導電體，或動態地改變半導體材料導電率，以響應於電場或基極電流。電晶體包括改變型式與掺雜程度之區域，其如同所需地配置，以使得在施加電場或基極電流時，電晶體可以增強或限制電流之流動。
主動與被動組件可以由具有不同電氣性質之材料層所形成。此等層可以藉由各種沉積技術而形成，此技術部份由所沉積材料之型式所決定。例如，薄膜沉積可以涉及：化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解質電鍍以及無電極電鍍過程。通常將各層圖案化以形成：主動組件、被動組件、或組件間電性連接之部份。
可以使用微影術將此等層圖案化，其涉及將光敏感材料例如光阻沉積在被圖案化之層上。使用光線將圖案由光罩移轉至光阻。使用溶劑將受光線照射之光阻圖案之部份去除，以曝露被圖案化下層之部份。將光阻之剩餘部份去除，以留下圖案化層。以替代方式，可以使用例如無電極與電解質電鍍技術，藉由將材料直接沉積於由先前沉積/蝕刻過程所形成區域或洞孔中，將一些型式材料圖案化。
將薄膜材料沉積於現有圖案上，會擴大下面圖案，且產生不均勻之平坦表面。通常需要均勻平坦表面，以生產較小且更密集地封裝之主動與被動組件。可以使用平坦化將材料從晶圓表面去除，以產生均勻平坦表面。平坦化涉及以拋光墊將晶圓表面拋光。在拋光期間，將研磨材料與腐蝕性化學物質加至晶圓表面。此研磨之機械作用與化學物質之腐蝕作用之組合，可以去除任何不規則地形，以導致均勻平坦表面。
後端製造過程是指將所完成晶圓切割或單一化成為個別晶粒，以及然後將此等晶粒封裝用於結構支持與環境隔離。為了將此晶粒單一化，將晶圓沿著稱為鋸道或劃線之晶圓無功能區域劃線且分開。使用雷射切割工具或鋸刀將晶圓單一化。在單一化之後，將個別晶粒安裝至封裝基板，此基板包括接腳或接觸墊，用於與其他系統組件互連。然後，將此半導體晶粒上所形成之接觸墊連接至此封裝中之接觸墊。此電性連接可以焊料突起、柱(stud)突起、導電漿或接線製成。將封膠或其他模製材料沉積在封裝上，以提供實體支持與電性隔離。然後，將此所完成封裝插入於電性系統中，且使得此半導體裝置功能可供其他系統組件使用。
圖1說明具有晶片載體基板或印刷電路板(PCB) 52之電子裝置50，此基板或電路板具有複數個安裝於其表面上之半導體封裝。取決於應用，此電子裝置50可以具有一種型式半導體封裝或多種型式半導體封裝。用於說明目的，圖1中顯示不同型式半導體封裝。
電子裝置50可以為獨立式系統，其使用半導體封裝以實施一或更多個電性功能。以替代方式，電子裝置50可以為一較大系統之次組件。例如，電子裝置50為可以插入於電腦中之圖形卡、網路介面卡或其他信號處理卡。半導體封裝可以包括微處理器、記憶體、特殊用途積體電路(ASIC)、邏輯電路、類比電路、射頻(RF)電路、離散裝置或其他半導體晶粒或電性組件。
在圖1中，PCB 52提供一般基板，用於安裝在於PCB上半導體封裝之機械支持與電性互連。使用蒸鍍、電解質電鍍、無電極電鍍、絲網印刷或其他適當金屬沉積過程，在PCB 52之表面上或層中形成導電信號跡線54。
信號跡線54提供在各半導體封裝、安裝組件、以及其他外部系統組件之間之電性連通。跡線54亦將功率與接地連接提供給各半導體封裝。
在一些實施例中，半導體裝置具有兩個封裝位準。第一位準封裝為一種技術，用於將半導體晶粒機械地與電性地裝附於一中間載體。第二位準封裝是關於將中間載體機械地與電性地裝附於PCB。在其他實施例中，半導體裝置僅具有第一位準封裝，而將晶粒機械地與電性地直接安裝至PCB。
為了說明目的而顯示，在PCB 52上數種型式第一位準封裝，其包括接線封裝56與覆晶58。此外，顯示在PCB 52上數種型式第二位準封裝，其包括：球格柵陣列(BGA)60、突起晶片載體(BCC)62、雙內線封裝(DIP)64、平面格柵陣列(LGA)66、多晶片模組(MCM)68、四方形扁平無接腳封裝(QFN)70以及四方形扁平封裝72。取決於系統需求，可以將半導體封裝之任何組合、以第一與第二位準封裝型式之任何組合而組態，而將其與其他電子組件一起連接至PCB 52。在一些實施例中，電子裝置50包括單一裝附半導體封裝，而其他實施例需要多個互連封裝。藉由將一或更多個半導體封裝組合於單一基板上，製造商可以將預製組件合併於電子裝置與系統中。因為半導體封裝包括複雜功能，可以使用較便宜組件與合理化製程以製造電子裝置。此所產生之裝置較不可能故障且製造較便宜，導致對於消費者較低成本。
圖2a-2c顯示典範半導體封裝。圖2a說明安裝於PCB 52上DIP 64之進一步細節。半導體晶粒74包括：一主動區域，其所包含類比或數位電路執行作為主動元件、被動元件、導電層以及形成於晶粒中之介電層，且根據晶粒之電性設計而電性互連。例如，電路可以包括：一或更多個電晶體、二極體、電感器、電容器、電阻器以及形成於半導體晶粒74主動區域中之其他電路元件。接觸墊76為一或更多層導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)，且電性連接至形成於半導體晶粒74中之電路元件。在DIP 64組裝期間，使用金-矽共晶層或黏著材料例如熱環氧樹脂，將半導體晶粒74安裝至一中間載體78。封裝體包括絕緣封裝材料，例如聚合物或陶瓷。導線80與接線82提供半導體晶粒74與PCB 52間之電性互連。封膠84沉積在封裝上，其藉由防止濕氣與粒子進入封裝且污染晶粒74與接線82而作環境保護。
圖2b說明安裝在PCB 52上BCC 62之進一步細節。使用底部填料或環氧樹脂黏著材料92，將半導體晶粒88安裝在載體90上。接線94提供接觸墊96與98間之第一位準封裝互連。將模製複合物或封膠100沉積在半導體晶粒88與接線94上，以提供用於此裝置之實體支持與電性隔離。使用適當金屬沉積過程例如電解質電鍍或無電極電鍍過程以防止氧化，將接觸墊102形成於PCB 52之表面上。將接觸墊102電性連接至PCB 52中一或更多個導電信號跡線54。在BCC 62之接觸墊98與PCB 52之接觸墊102之間形成突起104。
在圖2c中，將半導體晶粒58面向下、以覆晶型式第一位準封裝安裝至中間載體106。半導體晶粒58之主動區域108包括類比或數位電路，其執行作為根據晶粒電性設計所形成之主動元件、被動元件、導電層、以及介電層。例如，電路可以包括一或更多個電晶體、二極體、電感器、電容器、電阻器以及在主動區域108中之其他電路元件。半導體晶粒58經由突起110而電性地與機械地連接至載體106。
使用突起112，將BGA 60以BGA型式第二位準封裝電性地且機械地連接至PCB 52。經由突起110、信號線114以及突起112，將半導體晶粒58電性連接至在PCB 52中之導電信號跡線54。將模製複合物或封膠116沉積在半導體晶粒58與載體106上，以提供用於此裝置之實體支持與電性隔離。此覆晶半導體裝置提供從在半導體晶粒58上主動元件至在PCB 52上導電軌之短的導電路徑，以便縮短信號傳送距離、降低電容以及改善整個電路之性能表現。在另一實施例中，可以使用覆晶型式第一位準封裝而無需中間載體106，將半導體晶粒58電性地且機械地直接連接至PCB 52。
圖3a-3i說明有關於圖1與圖2a-2c之過程，以形成一WLCSMP，其所具有開放孔穴用於容納半導體晶粒，且經由TSV插入物而互連。圖3a顯示一半導體晶圓118，其包含基礎基板材料，例如：矽、鍺、砷化鎵、磷化銦或碳化矽，而用於結構支持。基板或載體120包含暫時或犧牲基礎材料，例如用於結構支持之：矽、聚合物、聚合複合物、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹或其他適當低成本、堅硬材料、或塊半導體材料。在載體120上塗佈介面層或帶121作為暫時黏著接合薄膜或蝕刻停止層。將半導體晶圓118安裝至載體帶121，而以其表面123背向此帶。
在圖3b中，使用雷射鑽孔或蝕刻過程、例如深反應性離子蝕刻(DRIE)，部份地經由半導體晶圓118在表面123形成複數個通孔。使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、電解質電鍍、無電極電鍍或其他適當金屬沉積過程，將通孔填以鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鈦(Ti)、鎢(W)、多晶矽或其他合適導電材料，以形成導電矽穿孔(TSV) 122。在TSV 122周圍形成選擇性絕緣層。在半導體晶圓118之表面123上形成電路層124。電路層124包括由絕緣層126所分開之導電層125。絕緣層126可以為由以下材料所構成之一或更多層：二氧化矽(SiO2 )、氮化矽(Si3 N4 )、氮氧化矽(SiON)、過氧化鉭(Ta2 O5 )、三氧化二鋁(Al2 O3 )、光阻或具有類似絕緣與結構性質之其他材料。使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴灑覆蓋、燒結或熱氧化以形成絕緣層126。藉由蝕刻過程以去除絕緣層126之一部份。使用具有物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解質電鍍、無電極電鍍或其他適當金屬沉積過程之圖案化，在絕緣層126被去除部份中形成導電層125。導電層125可以為以下所形成之一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料。導電層125之一部份電性連接至TSV 122。取決於半導體裝置之設計與功能，導電層125之其他部份可以為電性連接或電性隔離。可以在電路層124中形成一或更多個(IPD)，例如：電感器、電容器以及電阻器，用於射頻(RF)信號處理。
溝渠128是從表面123部份地經由半導體晶圓118而形成，其具有足夠的寬度與深度以容納一半導體晶粒。可以鋸刀、雷射鑽孔或RDIE形成溝渠128。在一實施例中，溝渠128之寬度大於半導體晶粒134之x/y軸長度，且其深度大於半導體晶粒134之厚度。選擇性溝渠130是從表面123部份地經由半導體晶圓118而形成，用於切割鋸開空間。溝渠130允許半導體晶圓118之側面(稍後稱為TSV插入物)在單一化之後由封膠覆蓋。
圖3c顯示半導體晶粒或組件132，其所具有主動表面133包含類比或數位電路，其可以執行作為主動元件、被動元件、導電層，以及形成於晶粒中之介電層，且根據晶粒之電性設計與功能而電性地互連。例如，此電路可以包括：一或更多個電晶體、二極體、以及形成於主動表面133中之其他電路元件，以執行類比電路或數位電路，例如：數位信號處理器(DSP)、特殊用途積體電路(ASIC)、記憶體或其他信號處理電路。半導體晶粒132亦包含整合式被動元件(IPD)，例如：電感器、電容器以及電阻器，用於射頻(RF)信號處理。
可以使用蒸鍍、電解質電鍍、無電極電鍍、球滴或絲網印刷過程，將導電突起材料沉積在主動表面133上。此突起材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料以及其組合，而具有選擇性的助焊劑溶液。例如，此突起材料可以為共晶Sn/Pb、高鉛焊料或無鉛焊料。藉由將材料加熱至其熔點以上而使得突起材料回焊，以形成球體或突起136。突起136代表可以形成於主動表面133上之一種形式互連結構。此互連結構亦可使用柱突起、微突起、導電柱、導電漿或其他電性互連。
可以使用突起136安裝半導體晶粒或組件134，且電性連接至半導體晶粒132。半導體晶粒134具有主動表面135，其包含類比或數位電路，而可以執行作為主動元件、被動元件、導電層，以及形成於晶粒中之介電層，且根據晶粒之電性設計與功能而電性互連。例如，此電路可以包括形成於主動表面135中之一或更多個電晶體、二極體以及其他電路元件，以執行類比電路或數位電路，例如：數位信號處理器(DSP)、特殊用途積體電路(ASIC)、記憶體或其他信號處理電路。半導體晶粒134亦包含整合式被動元件(IPD)，例如：電感器、電容器以及電阻器，用於射頻(RF)信號處理。
此經組合半導體晶粒132-134可以設置在半導體晶圓118上，且將其對準而將半導體晶粒134設置在溝渠128上。然後，藉由將突起136回焊，將經組合半導體晶粒132-134安裝至半導體晶圓118，而將主動表面133冶金地且電性地連接至導電層125，如同於圖3d中顯示。半導體晶粒134包含於溝渠128中，以降低封裝高度。
在圖3e中，使用漿料印刷、壓擠模製、移轉模製、液體封膠模製、真空堆疊、旋轉塗佈或其他適當塗佈劑，將封膠或模製複合物140沉積在半導體晶圓118上以及半導體晶粒132與134周圍。封膠140可以為聚合物複合材料，例如：具有填料之環氧樹脂、具有填料之環氧樹脂丙烯酸脂或具有適當填料之聚合物。封膠140為不導電，且可以對半導體裝置提供環境保護，以防止外部元件與污染物之進入。
在圖3f中，藉由磨輪142去除封膠140之一部份，以曝露半導體晶粒132之後表面143，且降低封裝之高度。在另一實施例中，例如在圖9中說明，磨輪142可以留下封膠140之一部份，以覆蓋半導體晶粒132之表面143。
在圖3g中，基板或載體144包含暫時或犧牲基礎材料而用於結構支持，例如：矽、聚合物、聚合複合物、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹或其他適當低成本、堅硬材料或塊(bulk)半導體材料。可以將介面層或帶146塗佈於載體144上，作為暫時黏著接合薄膜或蝕刻停止層。將在圖3a-3f中所說明組裝反轉，且安裝至載體帶146。藉由化學蝕刻、機械剝離、化學機械拋光(CMP)、機械研磨、熱烘焙、雷射掃瞄或濕性剝除，以去除載體120與帶121。
在圖3h中，藉由磨輪142，將面對表面123之半導體晶圓118之表面147之一部份去除，以曝露TSV 122與半導體晶粒134之後表面148，且降低此封裝之高度。半導體晶圓118之其餘部份構成插入物149，其具有用於電性互連之TSV 122。
在圖3i中，在插入件149之表面151上形成互連結構150。互連結構150包括形成於表面151上之絕緣層或鈍化層152，其使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴灑覆蓋、燒結或熱氧化而形成。絕緣層152為由以下材料所形成之一或更多層：二氧化矽(SiO2 )、氮化矽(Si3 N4 )、氮氧化矽(SiON)、過氧化鉭(Ta2 O5 )、三氧化二鋁(Al2 O3 )以及具有類似絕緣與結構性質之其他材料。藉由蝕刻過程以去除絕緣層152之一部份，以曝露TSV 122。
使用圖案化與沉積過程例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解質電鍍以及無電極電鍍，在TSV 122與絕緣層152被去除部份上形成導電層154。導電層154可以為以下材料所形成之一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料。可以在導電層154上形成一下突起金屬化(UBM)層。可以將導電層154之一部份電性連接至TSV 122與電路層124。取決於半導體裝置之設計與功能，導電層154之其他部份可以為電性連接或電性隔離。
使用蒸鍍、電解質電鍍、無電極電鍍、球滴或絲網印刷過程，將導電突起材料沉積在建立式互連結構150上，且電性連接至導電層154。此突起材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料以及其組合，而具有選擇性的助焊劑溶液。例如，此突起材料可以為共晶Sn/Pb、高鉛焊料或無鉛焊料。使用適當裝附或接合過程，將突起材料接合至導電層154。在一實施例中，藉由將材料加熱至其熔點以上而使得突起材料回焊，以形成球體或突起156。在一些應用中，此突起156第二次回焊，以改善至導電層154之電性接觸。突起亦可以被壓擠接合至導電層154。突起156代表可以形成於導電層154上之一種形式互連結構。此互連結構亦可使用柱突起、微突起、導電柱、導電漿或其他電性互連。
藉由化學蝕刻、機械剝離、化學機械拋光(CMP)、機械研磨、熱烘焙、雷射掃瞄或濕性剝除，以去除載體144與帶146。可以鋸刀或雷射切割裝置160將半導體晶粒132與134單一化成個別WLCSMP。圖4顯示在單一化後之WLCSMP 162。將被動組件164例如：電阻器、電容器、電感器，或主動組件安裝至插入物149。半導體晶粒134經由突起136電性連接至半導體晶粒132。半導體晶粒132經由電路層124與包含TSV 122之插入物149而電性連接至互連結構150。WLCSMP 162具有一開放孔穴，用於容納半導體晶粒134，以降低封裝高度。此研磨過程亦降低WLCSMP 162之高度。在一實施例中，由於此由溝渠130所提供額外切割空間，此插入物149之側被封膠140覆蓋。以替代方式，並不設置溝渠130，可以曝露插入物149之側。半導體晶粒132之曝露表面143與半導體晶粒134之曝露表面148提供良好熱驅散。半導體晶粒132與134以及插入物149之類似基礎材料例如矽，提供熱應力解除，且使得WLCSMP 162結實堅固，以防止封裝組件之間熱膨脹係數(CTE)中任何匹配不良。因此，可以減少WLCSMP 162翹曲之發生。
在圖3h之後，在以上過程之變化中，如同於圖5中顯示可以在插入物149之表面151上形成互連結構170。互連結構170包括聚合物絕緣層172，其使用旋轉塗佈、薄膜堆疊、模製、或其他適當沉積過程，而形成於表面151上。聚合物絕緣層172可以為以下材料所形成之一或更多層：聚亞醯胺、苯環丁烯(BCB)、聚醚醯亞胺(PBO)或其他具有類似絕緣與結構性質之材料。藉由蝕刻過程以去除聚合物絕緣層172之一部份，以曝露TSV 122。
使用圖案化與沉積過程，例如物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍，電解質電鍍、無電極電鍍，在TSV 122上與聚合物絕緣層172被去除部份上形成導電層174。導電層174可以為以下材料所形成之一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料。導電層174之一部份電性連接至TSV 122與電路層124。取決於半導體裝置之設計與功能，導電層174之其他部份可以為電性連接或電性隔離。
使用蒸鍍、電解質電鍍、無電極電鍍、球滴或絲網印刷過程，將導電突起材料沉積在建立式互連結構170上，且電性連接至導電層174。此突起材料可以為鋁(Al)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、鉛(Pb)、鉍(Bi)、銅(Cu)、焊料以及其組合，而具有選擇性的助焊劑溶液。例如，此突起材料可以為共晶Sn/Pb、高鉛焊料、或無鉛焊料。使用適當裝附或接合過程，將突起材料接合至導電層174。在一實施例中，藉由將材料加熱至其熔點以上而使得突起材料回焊，以形成球體或突起176。在一些應用中，此突起176第二次回焊，以改善至導電層174之電性接觸。突起亦可以被壓擠接合至導電層174。突起176代表可以形成於導電層174上之一種形式互連結構。此互連結構亦可使用柱突起、微突起、導電柱、導電漿或其他電性互連。
圖6顯示WLCSMP 178，其包括在圖3a-3i與4中所說明特徵，且將金屬板180安裝至：半導體晶粒132之表面143、以及具有導熱黏著劑之封膠140。金屬板180亦可以藉由無電極電鍍或電解質電鍍過程形成。金屬板180亦可以操作為散熱器，將來自WLCSMP 178之熱能驅散。金屬板180可以為
鋁(Al)、銅(Cu)或具有高熱導率之另外材料。選擇性晶粒裝附黏著劑或熱介面層(TIM)182，將金屬板180牢固至半導體晶粒132與封膠140。金屬板180可以增加WLCSMP 178之硬度。
圖7顯示WLCSMP 190，其包括在圖3a-3i與4中所說明特徵，且將金屬板192安裝至：半導體晶粒132之表面143、以及具有黏著劑之封膠140。金屬板192亦可以藉由無電極電鍍或電解質電鍍過程形成。金屬板192亦可以操作為電磁干擾(EMI)屏蔽層或射頻干擾(RFI)屏蔽層。金屬板192可以由以下材料所製成：銅；鋁；肥粒鐵或羰基鐵；不銹鋼；鎳銀；低碳鋼；矽鐵鋼；錫箔；環氧樹脂；導電樹脂；以及其他金屬與複合物，其能夠阻擋或吸收電磁干擾(EMI)、射頻干擾(RFI)以及其他裝置間干擾。屏蔽層亦可以為非金屬材料，例如：碳烟粉或鋁片，以減少EMI或RFI效應。金屬板192可以經由導電柱(pillar)或柱(stud)194、電路層124、在插入物149中TSV 122、以及互連結構150而接地。導電柱194可以為金柱、或銅柱或焊料。金屬板192亦可以操作為散熱器，將來自WLCSMP 190之熱能驅散。
圖8顯示WLCSMP 196，其包括在圖3a-3i與4中所說明特徵，以及在封膠140中形成導電柱或柱198。導電柱198可以藉由以下方式形成：在封膠140中雷射鑽孔或蝕刻通孔，且將通孔以導電材料例如銅、金、或焊料填滿而形成。導電柱198提供用於堆疊半導體封裝之額外互連能力。
圖9顯示WLCSMP 200，其包括在圖3a-3i與4中所說明特徵，其所例外不同者為在圖3f中所說明之研磨操作留下封膠140，以覆蓋半導體晶粒132之表面143。導電柱或柱202可以藉由以下方式形成：在封膠140中雷射鑽孔或蝕刻通孔，且將通孔填滿導電材料例如銅、金、或焊料而形成。在封膠140中形成導電層204。導電柱202與導電層204提供用於輸入(fan-in)堆疊半導體封裝之額外互連能力。
圖10顯示WLCSMP 210，其包括在圖3a-3i與4中所說明特徵。此外，導電柱或柱212可以藉由以下方式形成：在封膠140中雷射鑽孔或蝕刻通孔，且將通孔填滿導電材料例如銅、金、或焊料而形成。半導體晶粒132之表面143、以及在封膠140上形成互連結構214。互連結構214包括絕緣或鈍化層216，其藉由使用使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴灑覆蓋、燒結或熱氧化而形成。絕緣層216可以為由以下材料所構成之一或更多層：二氧化矽(SiO2 )、氮化矽(Si3 N4 )、氮氧化矽(SiON)、過氧化鉭(Ta2 O5 )、三氧化二鋁(Al2 O3 )、以及具有類似絕緣與結構性質之其他材料。使用圖案化與沉積過程例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解質電鍍以及無電極電鍍，在絕緣層216中形成導電層218。導電層218可以為以下所形成之一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料。導電層218之一部份電性連接至導電柱212。取決於半導體裝置之設計與功能，導電層218之其他部份可以為電性連接或電性隔離。導電柱212與互連結構214提供用於輸入(fan-in)堆疊半導體封裝之額外互連能力。
圖11顯示WLCSMP 220，其包括在圖3a-3i與4中所說明特徵。此外，導電柱222可以藉由以下方式形成：在半導體晶粒132中雷射鑽孔或蝕刻通孔，且將通孔填滿導電材料例如銅或金而形成。半導體晶粒132之表面143上形成互連結構224。互連結構224包括絕緣或鈍化層226，其藉由使用物理氣相沉積(PVD)、化學氣相沉積(CVD)、印刷、旋轉塗佈、噴灑覆蓋、燒結或熱氧化以形成。絕緣層226可以為由以下材料所構成之一或更多層：二氧化矽(SiO2 )、氮化矽(Si3 N4 )、氮氧化矽(SiON)、過氧化鉭(Ta2 O5 )、三氧化二鋁(Al2 O3 )以及具有類似絕緣與結構性質之其他材料。藉由蝕刻過程以去除絕緣層226之一部份。使用圖案化與沉積過程例如：物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍、電解質電鍍以及無電極電鍍，在絕緣層226被去除部份中形成導電層228。導電層228可以為以下所形成之一或更多層：鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)或其他合適導電材料。導電柱222與導電層226提供用於堆疊半導體封裝之額外互連能力。
圖12顯示WLCSMP 230，其包括在圖3a-3i與4中所說明特徵。此外，導電柱232可以藉由以下方式形成：在半導體晶粒134中雷射鑽孔或蝕刻通孔，且將通孔填滿導電材料例如銅或金而形成。互連結構150在半導體晶粒134之表面148上延伸。在半導體晶粒134之表面158上之導電柱232與互連結構150，提供用於堆疊半導體封裝之額外互連能力。
以上已經詳細說明本發明之一或更多個實施例，熟習此技術人士瞭解，可以對於此等實施例作修正與調整，而不會偏離以下申請專利範圍中所設定本發明之範圍。
50．．．電性裝置
52．．．印刷電路板(PCB)
54．．．信號跡線
56．．．接線封裝
58．．．覆晶
60．．．球格柵陣列(BGA)
62．．．突起晶片載體(BCC)
64．．．雙內線封裝(DIP)
66．．．平面格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．四方形扁平無接腳封裝(QFN)
72．．．四方形扁平封裝
76．．．接觸墊
78．．．中間載體
80．．．導線
82．．．接線
84．．．封膠
88．．．半導體晶粒
90．．．載體
92．．．底部填料
94．．．接線
96．．．接觸墊
98．．．接觸墊
100．．．模製複合物
102．．．接觸墊
104．．．突起
106．．．中間載體
108．．．主動區域
110．．．突起
112．．．突起
114．．．信號線
116．．．模製複合物
118．．．半導體晶圓
120．．．載體
121．．．帶
122．．．矽穿孔
123．．．表面
124．．．電路層
125．．．導電層
126．．．絕緣層
128．．．溝渠
130．．．溝渠
132．．．半導體晶粒
133．．．主動表面
134．．．半導體晶粒
135．．．主動表面
136．．．突起
140．．．模製複合物
142．．．磨輪
143．．．表面
144．．．基板
146．．．介面層
147．．．表面
148．．．後表面
149．．．插入物
150．．．互連結構
151．．．表面
152．．．絕緣層
154．．．導電層
156．．．球體
160．．．雷射切割裝置
162．．．晶圓級晶片尺寸模組封裝(WLCSMP)
164．．．被動組件
170．．．互連結構
172．．．聚合物絕緣層
174．．．導電層
176．．．球體
178．．．晶圓級晶片尺寸模組封裝
180．．．金屬板
182．．．熱介面層
190．．．晶圓級晶片尺寸模組封裝
192．．．金屬板
194．．．導電柱
196．．．晶圓級晶片尺寸模組封裝
198．．．導電柱
200．．．晶圓級晶片尺寸模組封裝
202．．．導電柱
204．．．導電層
210．．．晶圓級晶片尺寸模組封裝
212．．．導電柱
214．．．互連結構
216．．．絕緣層
218．．．導電層
220．．．晶圓級晶片尺寸模組封裝
222．．．導電柱
224．．．互連結構
226．．．絕緣層
228．．．導電層
230．．．晶圓級晶片尺寸模組封裝
232．．．導電柱
圖1說明一種印刷電路板(PCB)，其具有安裝至其表面之不同形式封裝；
圖2a-2c說明安裝至PCB之典範半導體封裝之進一步細節；
圖3a-3i說明形成WLCSMP之過程，其具有一開放孔穴用於包含半導體晶粒且經由一TSV插入物而互連；
圖4說明WLCSMP，其具有一開放孔穴用於包含半導體晶粒，且經由一TSV插入物而互連；
圖5說明具有一聚合物絕緣層之TSV插入物；
圖6說明WLCSMP，其具有一散熱器與形成於上半導體晶粒上之TIM層；
圖7說明WLCSMP，其具有形成於上半導體晶粒上之EMI與RFI屏蔽層；
圖8說明WLCSMP，其具有經由封膠所形成之導電柱；
圖9說明WLCSMP，其具有經由封膠所形成之導電柱、以及形成於封膠上之導電層；
圖10說明WLCSMP，其具有經由封膠所形成之導電柱、以及形成於上半導體晶粒上之互連結構；
圖11說明WLCSMP，其具有經由上半導體晶粒所形成之TSV、以及形成於上半導體晶粒上之互連結構；以及
圖12說明WLCSMP，其具有經由下半導體晶粒所形成之TSV、以及形成於下半導體晶粒上之互連結構。
122‧‧‧矽穿孔
124‧‧‧電路層
125‧‧‧導電層
126‧‧‧絕緣層
132‧‧‧半導體晶粒
133‧‧‧主動表面
134‧‧‧半導體晶粒
135‧‧‧主動表面
136‧‧‧突起
143‧‧‧表面
148‧‧‧後表面
149‧‧‧插入物
150‧‧‧互連結構
152‧‧‧絕緣層
154‧‧‧導電層
156‧‧‧球體
162‧‧‧晶圓級晶片尺寸模組封裝(WLCSMP)
164‧‧‧被動組件

Claims (15)

  1. 一種製造半導體裝置之方法，其包括：提供一半導體晶圓，其包含複數第一導電通孔；經由該半導體晶圓部份地形成一第一孔穴；將一第一半導體晶粒安裝至一第二半導體晶粒；將該第一半導體晶粒與該第二半導體晶粒安裝至該半導體晶圓，以致於該第一半導體晶粒設置在該半導體晶圓上，且電性連接至該第一導電通孔，以及該第二半導體晶粒設置於該第一孔穴中；將封膠沉積在該半導體晶圓上，以及在該第一半導體晶粒與該第二半導體晶粒周圍；自該第一半導體晶粒上將該封膠之一部份去除；將該半導體晶圓之一部份去除，以曝露該導電通孔與該第二半導體晶粒之一第一表面，以致於該半導體晶圓之其餘部份操作為用於該第一半導體晶粒與該第二半導體晶粒之一插入物；以及在該插入物上形成一第一互連結構。
  2. 如申請專利範圍第1項之方法，更包括在該半導體晶圓中形成一第二孔穴，以曝露在單一化之後的該插入物之側上的該封膠。
  3. 如申請專利範圍第1項之方法，更包括在該第一半導體晶粒上形成一第二互連結構。
  4. 如申請專利範圍第1項之方法，更包括經由該第一半導體晶粒或該第二半導體晶粒形成複數個第二導電通 孔。
  5. 如申請專利範圍第1項之方法，更包括在該第一半導體晶粒上形成一金屬板。
  6. 一種製造半導體裝置之方法，其包括：提供一半導體晶圓，其包含複數個導電通孔；在該半導體晶圓中形成一孔穴；將一第一半導體晶粒安裝至該半導體晶圓；將一第二半導體晶粒安裝至該孔穴中；將封膠沉積在該半導體晶圓以及在該第一半導體晶粒與該第二半導體晶粒上；將該半導體晶圓之一部份去除，以曝露該導電通孔與該第二半導體晶粒之一第一表面。
  7. 如申請專利範圍第6項之方法，更包括在該導電通孔上形成一互連結構。
  8. 如申請專利範圍第6項之方法，更包括將該封膠之一部份去除，以曝露該第一半導體晶粒之一第一表面。
  9. 如申請專利範圍第6項之方法，更包括經由該第一半導體晶粒周圍之該封膠形成複數個導電柱。
  10. 如申請專利範圍第6項之方法，更包括在該第一半導體晶粒之一表面上形成一互連結構。
  11. 一種半導體裝置，包括：一插入物，其具有經由該插入物的一表面所形成之複數個導電通孔以及經由該插入物所部份形成之孔穴；一半導體構件，其設置於該孔穴中； 一第一半導體晶粒，其安裝至該半導體構件和該插入物且電性連接至該導電通孔；以及一封膠，其沉積在該插入物以及該第一半導體晶粒上，並且該封膠覆蓋該插入物之外邊。
  12. 如申請專利範圍第11項之半導體裝置，更包括一互連結構，其形成在面對該第一半導體晶粒之該插入物上且電性連接至該導電通孔。
  13. 如申請專利範圍第11項之半導體裝置，更包括一互連結構，其形成在該第一半導體晶粒和該封膠上。
  14. 如申請專利範圍第11項之半導體裝置，其中該第一半導體晶粒和該半導體構件及該插入物包含類似基礎材料以提供熱應力解除。
  15. 如申請專利範圍第11項之半導體裝置，其中該半導體構件包括一第二半導體晶粒。
TW099123391A 2009-09-23 2010-07-16 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法 TWI499030B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/565,380 US8143097B2 (en) 2009-09-23 2009-09-23 Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

Publications (2)

Publication Number Publication Date
TW201133769A TW201133769A (en) 2011-10-01
TWI499030B true TWI499030B (zh) 2015-09-01

Family

ID=43755904

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099123391A TWI499030B (zh) 2009-09-23 2010-07-16 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法

Country Status (4)

Country Link
US (3) US8143097B2 (zh)
CN (1) CN102034718B (zh)
SG (2) SG169931A1 (zh)
TW (1) TWI499030B (zh)

Families Citing this family (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200522293A (en) * 2003-10-01 2005-07-01 Koninkl Philips Electronics Nv Electrical shielding in stacked dies by using conductive die attach adhesive
US8169058B2 (en) * 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
USRE48111E1 (en) 2009-08-21 2020-07-21 JCET Semiconductor (Shaoxing) Co. Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US10297550B2 (en) * 2010-02-05 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC architecture with interposer and interconnect structure for bonding dies
US20110193235A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8455995B2 (en) 2010-04-16 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. TSVs with different sizes in interposers for bonding dies
KR101765473B1 (ko) * 2010-06-21 2017-08-24 삼성전자 주식회사 인쇄 회로 기판 및 이를 포함하는 반도체 패키지
US20120001339A1 (en) * 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8076184B1 (en) * 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
US8288201B2 (en) * 2010-08-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US9059187B2 (en) 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same
US8895380B2 (en) 2010-11-22 2014-11-25 Bridge Semiconductor Corporation Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby
US8367475B2 (en) * 2011-03-25 2013-02-05 Broadcom Corporation Chip scale package assembly in reconstitution panel process format
US20130075892A1 (en) * 2011-09-27 2013-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Three Dimensional Integrated Circuit Fabrication
US20130082383A1 (en) * 2011-10-03 2013-04-04 Texas Instruments Incorporated Electronic assembly having mixed interface including tsv die
WO2013054408A1 (ja) * 2011-10-12 2013-04-18 日本碍子株式会社 大容量モジュールの周辺回路用の回路基板、及び当該回路基板を用いる周辺回路を含む大容量モジュール
US9190391B2 (en) * 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US9006889B2 (en) * 2011-11-11 2015-04-14 Skyworks Solutions, Inc. Flip chip packages with improved thermal performance
US9123700B2 (en) 2012-01-06 2015-09-01 Micron Technology, Inc. Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias
US9548251B2 (en) * 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
JP2013160942A (ja) 2012-02-06 2013-08-19 Sony Corp 半導体装置およびその製造方法、並びに電子機器
KR20130105175A (ko) * 2012-03-16 2013-09-25 삼성전자주식회사 보호 층을 갖는 반도체 패키지 및 그 형성 방법
TWI528876B (zh) 2012-03-22 2016-04-01 矽品精密工業股份有限公司 中介板及其電性測試方法
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US20130256895A1 (en) * 2012-03-30 2013-10-03 Michael Su Stacked semiconductor components with universal interconnect footprint
US10269863B2 (en) * 2012-04-18 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for via last through-vias
US8765549B2 (en) 2012-04-27 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US9040346B2 (en) 2012-05-03 2015-05-26 Infineon Technologies Ag Semiconductor package and methods of formation thereof
JP5474127B2 (ja) * 2012-05-14 2014-04-16 株式会社野田スクリーン 半導体装置
US8878338B2 (en) 2012-05-31 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor for interposers and methods of manufacture thereof
US8853058B2 (en) * 2012-06-22 2014-10-07 Freescale Semiconductor, Inc. Method of making surface mount stacked semiconductor devices
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
TWI503928B (zh) * 2012-09-10 2015-10-11 矽品精密工業股份有限公司 半導體封裝件及其製法與中介板結構
US10192796B2 (en) * 2012-09-14 2019-01-29 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dual-sided interconnect structures in FO-WLCSP
US9443797B2 (en) * 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US9818734B2 (en) * 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
KR101989516B1 (ko) * 2012-09-24 2019-06-14 삼성전자주식회사 반도체 패키지
US10269676B2 (en) * 2012-10-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced package-on-package (PoP)
US8975726B2 (en) 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
CN103165543B (zh) * 2013-02-08 2015-11-18 日月光半导体制造股份有限公司 半导体元件及其制造方法与封装构造
US9177903B2 (en) 2013-03-29 2015-11-03 Stmicroelectronics, Inc. Enhanced flip-chip die architecture
JP2014222728A (ja) * 2013-05-14 2014-11-27 凸版印刷株式会社 半導体パッケージ
KR102077153B1 (ko) 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
CN103346131A (zh) * 2013-06-25 2013-10-09 华进半导体封装先导技术研发中心有限公司 一种细间距pop式封装结构和封装方法
US9847315B2 (en) * 2013-08-30 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Packages, packaging methods, and packaged semiconductor devices
US9293409B2 (en) 2013-09-11 2016-03-22 Infineon Technologies Ag Method for manufacturing a semiconductor device, and semiconductor device
US9252054B2 (en) 2013-09-13 2016-02-02 Industrial Technology Research Institute Thinned integrated circuit device and manufacturing process for the same
US9299650B1 (en) * 2013-09-25 2016-03-29 Stats Chippac Ltd. Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9793242B2 (en) * 2013-12-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with die stack including exposed molding underfill
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US11291146B2 (en) 2014-03-07 2022-03-29 Bridge Semiconductor Corp. Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same
US10121768B2 (en) 2015-05-27 2018-11-06 Bridge Semiconductor Corporation Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same
US10354984B2 (en) 2015-05-27 2019-07-16 Bridge Semiconductor Corporation Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
KR102258743B1 (ko) * 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9402312B2 (en) 2014-05-12 2016-07-26 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
KR101563909B1 (ko) 2014-08-19 2015-10-28 앰코 테크놀로지 코리아 주식회사 패키지 온 패키지 제조 방법
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
FI126380B (en) * 2014-10-27 2016-11-15 Kone Corp The drive unit
TWI566339B (zh) * 2014-11-11 2017-01-11 矽品精密工業股份有限公司 電子封裝件及其製法
US9589936B2 (en) * 2014-11-20 2017-03-07 Apple Inc. 3D integration of fanout wafer level packages
US9941226B2 (en) 2014-12-15 2018-04-10 Industrial Technology Research Institute Integrated millimeter-wave chip package
RU2584575C1 (ru) * 2014-12-25 2016-05-20 Общество с ограниченной ответственностью "ЗЕЛНАС" Интерпозер и способ его изготовления
US9893017B2 (en) 2015-04-09 2018-02-13 STATS ChipPAC Pte. Ltd. Double-sided semiconductor package and dual-mold method of making same
KR20160122022A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 인터포저를 갖는 반도체 패키지 및 제조 방법
US9437536B1 (en) * 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US20160365334A1 (en) * 2015-06-09 2016-12-15 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US20170170109A1 (en) * 2015-06-25 2017-06-15 Intel Corporation Integrated circuit structures with interposers having recesses
JP6773367B2 (ja) 2015-06-25 2020-10-21 インテル・コーポレーション パッケージオンパッケージのため凹型導電性コンタクトを有する集積回路構造及び方法
CN105140211A (zh) * 2015-07-14 2015-12-09 华进半导体封装先导技术研发中心有限公司 一种fan-out的封装结构及其封装方法
DE112015006937T5 (de) * 2015-09-25 2018-09-06 Intel Corporation Verpackte integrierte Schaltkreisvorrichtung mit Vertiefungsstruktur
WO2017142978A1 (en) * 2016-02-15 2017-08-24 Transsip Inc Emi shielded integrated circuit packages and methods of making the same
US9941186B2 (en) 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US10600679B2 (en) * 2016-11-17 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US9935079B1 (en) 2016-12-08 2018-04-03 Nxp Usa, Inc. Laser sintered interconnections between die
WO2018125055A1 (en) * 2016-12-27 2018-07-05 Intel IP Corporation Packages of stacking integrated circuits
KR20220056880A (ko) * 2016-12-29 2022-05-06 인텔 코포레이션 시스템 인 패키지 장치를 위해 구리 필러와 연결된 베어 다이 스마트 브리지
US20200083180A1 (en) * 2016-12-31 2020-03-12 Intel Corporation Electronic package assembly with stiffener
US9892920B1 (en) * 2017-01-05 2018-02-13 Lam Research Corporation Low stress bonding of silicon or germanium parts
JP6640780B2 (ja) * 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
CN107910315B (zh) * 2017-11-10 2020-09-25 深圳市盛路物联通讯技术有限公司 芯片封装
US10546817B2 (en) * 2017-12-28 2020-01-28 Intel IP Corporation Face-up fan-out electronic package with passive components using a support
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
CN110660805B (zh) * 2018-06-28 2023-06-20 西部数据技术公司 包含分支存储器裸芯模块的堆叠半导体装置
KR102615701B1 (ko) 2018-06-14 2023-12-21 삼성전자주식회사 관통 비아를 포함하는 반도체 장치, 반도체 패키지 및 이의 제조 방법
US10985109B2 (en) 2018-12-27 2021-04-20 STATS ChipPAC Pte. Ltd. Shielded semiconductor packages with open terminals and methods of making via two-step process
CN110211946A (zh) * 2019-06-17 2019-09-06 上海先方半导体有限公司 一种芯片封装结构及其制造方法
CN110211954A (zh) * 2019-06-17 2019-09-06 上海先方半导体有限公司 一种多芯片封装结构及其制造方法
US11145638B2 (en) 2019-09-16 2021-10-12 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
KR20210043103A (ko) 2019-10-11 2021-04-21 삼성전자주식회사 반도체 패키지
US11404380B2 (en) * 2019-12-19 2022-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11205629B2 (en) * 2020-01-21 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11291106B2 (en) * 2020-01-29 2022-03-29 Dell Products L.P. System and method for enhanced cooling
US11557565B2 (en) 2020-10-06 2023-01-17 Nxp Usa, Inc. Semiconductor device assembly and method therefor
US11502054B2 (en) 2020-11-11 2022-11-15 Nxp Usa, Inc. Semiconductor device assembly and method therefor
US20220157732A1 (en) * 2020-11-13 2022-05-19 Mediatek Inc. Semiconductor package and method of forming the same
JP2022102371A (ja) 2020-12-25 2022-07-07 国立大学法人東京工業大学 半導体装置及びその製造方法
CN112908867A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 2.5d封装结构及其制作方法
CN115020369A (zh) * 2021-03-03 2022-09-06 华为技术有限公司 电路板组件及其制造方法和电子设备
US11854922B2 (en) * 2021-06-21 2023-12-26 Texas Instruments Incorporated Semicondutor package substrate with die cavity and redistribution layer
US20230014046A1 (en) * 2021-07-13 2023-01-19 Mediatek Inc. Semiconductor devices with in-package PGS for coupling noise suppression
CN113764288A (zh) * 2021-08-02 2021-12-07 苏州通富超威半导体有限公司 一种芯片封装方法及封装结构
CN115547998A (zh) * 2022-10-21 2022-12-30 华进半导体封装先导技术研发中心有限公司 一种六面保护的2.5d模组结构及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870289A (en) * 1994-12-15 1999-02-09 Hitachi, Ltd. Chip connection structure having diret through-hole connections through adhesive film and wiring substrate
US6448661B1 (en) * 2001-02-09 2002-09-10 Samsung Electornics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
US6798049B1 (en) * 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
TW200901411A (en) * 2007-06-20 2009-01-01 Stats Chippac Ltd Wafer level integration package

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
EP0732107A3 (en) 1995-03-16 1997-05-07 Toshiba Kk Screen device for circuit substrate
US5620928A (en) 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
JP2001077293A (ja) 1999-09-02 2001-03-23 Nec Corp 半導体装置
US6452278B1 (en) 2000-06-30 2002-09-17 Amkor Technology, Inc. Low profile package for plural semiconductor dies
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US6798055B2 (en) 2001-03-12 2004-09-28 Micron Technology Die support structure
TW523887B (en) 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US6680529B2 (en) 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US6659512B1 (en) 2002-07-18 2003-12-09 Hewlett-Packard Development Company, L.P. Integrated circuit package employing flip-chip technology and method of assembly
JP2004214249A (ja) * 2002-12-27 2004-07-29 Renesas Technology Corp 半導体モジュール
US6838776B2 (en) 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
TWI225299B (en) * 2003-05-02 2004-12-11 Advanced Semiconductor Eng Stacked flip chip package
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
DE102004022884B4 (de) 2004-05-06 2007-07-19 Infineon Technologies Ag Halbleiterbauteil mit einem Umverdrahtungssubstrat und Verfahren zur Herstellung desselben
US7745918B1 (en) * 2004-11-24 2010-06-29 Amkor Technology, Inc. Package in package (PiP)
JP2006190767A (ja) * 2005-01-05 2006-07-20 Shinko Electric Ind Co Ltd 半導体装置
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
JP2008016508A (ja) * 2006-07-03 2008-01-24 Nec Electronics Corp 半導体装置およびその製造方法
JP2008141059A (ja) 2006-12-04 2008-06-19 Nec Electronics Corp 半導体装置
KR100840788B1 (ko) * 2006-12-05 2008-06-23 삼성전자주식회사 칩 적층 패키지 및 그 제조 방법
US20080174008A1 (en) * 2007-01-18 2008-07-24 Wen-Kun Yang Structure of Memory Card and the Method of the Same
US20080197469A1 (en) * 2007-02-21 2008-08-21 Advanced Chip Engineering Technology Inc. Multi-chips package with reduced structure and method for forming the same
US7863090B2 (en) 2007-06-25 2011-01-04 Epic Technologies, Inc. Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system
US7863096B2 (en) * 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
US8115292B2 (en) 2008-10-23 2012-02-14 United Test And Assembly Center Ltd. Interposer for semiconductor package
US8624370B2 (en) 2009-03-20 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with an interposer and method of manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5870289A (en) * 1994-12-15 1999-02-09 Hitachi, Ltd. Chip connection structure having diret through-hole connections through adhesive film and wiring substrate
US6798049B1 (en) * 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6448661B1 (en) * 2001-02-09 2002-09-10 Samsung Electornics Co., Ltd. Three-dimensional multi-chip package having chip selection pads and manufacturing method thereof
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
TW200901411A (en) * 2007-06-20 2009-01-01 Stats Chippac Ltd Wafer level integration package

Also Published As

Publication number Publication date
US20130299974A1 (en) 2013-11-14
US9263332B2 (en) 2016-02-16
SG183027A1 (en) 2012-08-30
US20120168916A1 (en) 2012-07-05
US8143097B2 (en) 2012-03-27
US20110068444A1 (en) 2011-03-24
CN102034718A (zh) 2011-04-27
TW201133769A (en) 2011-10-01
SG169931A1 (en) 2011-04-29
US9048306B2 (en) 2015-06-02
CN102034718B (zh) 2015-12-16

Similar Documents

Publication Publication Date Title
TWI499030B (zh) 在矽穿孔插入物中形成開放孔穴以包含在晶圓級晶片尺寸模組封裝的半導體晶粒之半導體裝置和方法
US11688612B2 (en) Semiconductor device and method of forming interposer with opening to contain semiconductor die
US9443829B2 (en) Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure
US9305897B2 (en) Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US8367480B2 (en) Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US8642381B2 (en) Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die
US9177901B2 (en) Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
TWI552265B (zh) 形成孔穴於增進互連結構中以縮短晶粒之間訊號路徑之半導體裝置和方法
US8999760B2 (en) Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure
US9865482B2 (en) Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
TWI528465B (zh) 半導體元件和形成具有嵌入半導體晶粒的預先製備散熱框之方法
TWI579977B (zh) 使用引線架體以形成用於半導體晶粒的垂直互連的通過密封物的開口之半導體裝置和方法
US8288201B2 (en) Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die
TWI523126B (zh) 在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法
US20120049334A1 (en) Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die