US20130075892A1 - Method for Three Dimensional Integrated Circuit Fabrication - Google Patents

Method for Three Dimensional Integrated Circuit Fabrication Download PDF

Info

Publication number
US20130075892A1
US20130075892A1 US13246553 US201113246553A US2013075892A1 US 20130075892 A1 US20130075892 A1 US 20130075892A1 US 13246553 US13246553 US 13246553 US 201113246553 A US201113246553 A US 201113246553A US 2013075892 A1 US2013075892 A1 US 2013075892A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
wafer
plurality
side
forming
method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13246553
Inventor
Jing-Cheng Lin
Weng-Jin Wu
Ying-Ching Shih
Jui-Pin Hung
Szu Wei Lu
Shin-puu Jeng
Chen-Hua Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Description

    BACKGROUND
  • The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
  • As semiconductor technologies evolve, multi-chip wafer level package based semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a wafer level package based semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated on different wafers and each wafer die is stacked on top of another wafer die using pick-and-place techniques. Much higher density can be achieved by employing multi-chip semiconductor devices. Furthermore, multi-chip semiconductor devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
  • A three-dimensional (3D) integrated circuit (IC) may comprise a top active circuit layer, a bottom active circuit layer and a plurality of inter-layers. In a 3D IC, two dies may be bonded together through a plurality of micro bumps and electrically coupled to each other through a plurality of through-substrate vias. The micro bumps and through-substrate vias provide an electrical interconnection in the vertical axis of the 3D IC. As a result, the signal paths between two semiconductor dies are shorter than those in a traditional 3D IC in which different dies are bonded together using interconnection technologies such as wire bonding based chip stacking packages. A 3D IC may comprise a variety of semiconductor dies stacked together. The multiple semiconductor dies are packaged before the wafer has been diced. The wafer level package technology has some advantages. One advantageous feature of packaging multiple semiconductor dies at the wafer level is multi-chip wafer level package techniques may reduce fabrication costs. Another advantageous feature of wafer level package based multi-chip semiconductor devices is that parasitic losses are reduced by employing micro bumps and through-substrate vias.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
  • FIGS. 1-5 are cross sectional views of intermediate stages in the making of a three-dimensional (3D) integrated circuit (IC) in accordance with an embodiment;
  • FIGS. 6-10 are cross sectional views of intermediate stages in the making of a 3D IC in accordance with another embodiment; and
  • FIGS. 11-15 are cross sectional views of intermediate stages in the making of a 3D IC in accordance with yet another embodiment.
  • Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.
  • DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • The making and using of the presently embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.
  • The present disclosure will be described with respect to embodiments in a specific context, a method for fabricating three-dimensional (3D) integrated circuits (ICs). The disclosure may also be applied, however, to the semiconductor fabrication of a variety of integrated circuits.
  • FIGS. 1-5 are cross sectional views of intermediate stages in the making of a 3D IC in accordance with an embodiment. A wafer stack 100 may comprise a wafer 102 and a plurality of semiconductor dies mounted on top of the wafer 102. In accordance with an embodiment, the wafer 102 is a silicon wafer. As shown in FIG. 1, the plurality of semiconductor dies may include a first semiconductor die 154, a second semiconductor die 156, a third semiconductor die 164 and a fourth semiconductor die 166. The wafer 102 may be a standard wafer having a thickness more than 100 um. In accordance with an embodiment, the wafer 102 may be of a thickness of about 770 um. The wafer 102 may comprise a plurality of integrated circuits (not shown), each of which may comprise various layers such as active circuit layers, substrate layers, inter-layer dielectric (ILD) layers and inter-metal dielectric (IMD) layers (not shown). The wafer 102 may further comprise a plurality of micro bumps 134 formed between the wafer 102 and the plurality of semiconductor dies (e.g., the first semiconductor die 154). Furthermore, the connections of the plurality of micro bumps 134 may be redistributed through a redistribution layer 132 formed on top of the wafer 102.
  • The wafer 102 may further comprise a plurality of through vias. In some embodiments, the through vias are through-substrate vias (TSVs) or through-silicon vias (TSVs), such as TSVs 112, 114, 116, 118, 122, 124, 126 and 128. The active circuit layers (not shown) of the wafer 102 may be coupled to micro bumps 134 and/or one or more of the plurality of TSVs (e.g., TSV 112). The active circuit layers are further connected to the first semiconductor die 154, the second semiconductor die 156, the third semiconductor die 164 and the fourth semiconductor die 166 through the plurality of micro bumps 134.
  • An underfill material 152 may be formed in the gap between the wafer 102 and the plurality of semiconductor dies (e.g., the first semiconductor die 154) mounted on top of the wafer 102. In accordance with an embodiment, the underfill material 152 may be an epoxy, which is dispensed at the gap between the wafer 102 and the first semiconductor die 154. The epoxy may be applied in a liquid form, and may harden after a curing process. In accordance with another embodiment, the underfill layer 152 may be formed of curable materials such as polymer based materials, resin based materials, polyimide, epoxy and any combinations of thereof. The underfill layer 152 can be formed by a spin-on coating process, dry film lamination process and/or the like. An advantageous feature of having an underfill material (e.g., underfill material 152) is that the underfill material 152 helps to prevent the micro bumps 134 from cracking. In addition, the underfill material 152 may help to reduce the mechanical and thermal stresses during the fabrication process of the wafer stack 100.
  • FIG. 2 illustrates a cross sectional view of a 3D IC structure having a molding compound layer formed on top of the wafer 102. As shown in FIG. 2, the first semiconductor die 154, the second semiconductor die 156, the third semiconductor die 164 and the fourth semiconductor die 166 are embedded in the molding compound layer 202. The molding compound layer 202 may be formed of curable materials such as polymer based materials, resin based materials, polyimide, epoxy and any combinations of thereof. The molding compound layer 202 can be formed by a spin-on coating process, an injection molding process and/or the like. In order to reliably handle the wafer 102 and the semiconductor dies (e.g., the first semiconductor die 154) mounted on top of the wafer 102 during process steps such as dicing the wafer stack 100 into separate chip packages, the molding compound layer 202 is employed to keep the wafer 102 and the semiconductor dies on top of wafer from cracking, bending, warping and/or the like.
  • FIG. 3 illustrates a process of backside grinding. The backside of the wafer 102 undergoes a thinning process. The thinning process can employ a mechanical grinding process, a chemical polishing process, an etching process or the like. By employing the thinning process, the backside of the wafer 102 can be ground so that the wafer 102 may have a thickness of approximately sub-100 um. In accordance with an embodiment, the thickness of the wafer 102 may be reduced to a range from about 20 um to about 50 um. It should be noted that by grinding the wafer 102 to a thickness as low as 20 um, such a thin wafer may enable small via feature size such as via diameter and depth. An advantageous feature of forming small TSVs is that the performance and power consumption of the wafer stack 100 can be further improved.
  • Alternatively, the thickness of the wafer 102 may be ground until the embedded ends of the TSVs (e.g., TSV 112) become exposed. Subsequently, a redistribution layer 304 is formed on top of the newly ground backside of the wafer 102. Furthermore, a plurality of bumps 302 are formed on top of the exposed ends of the TSVs. It should be noted the bumps 302 may be formed somewhere other than the exposed ends of the TSVs and reconnected with the TSVs (e.g., TSV 116) through the redistribution layer 304.
  • FIG. 4 illustrates a process of attaching the wafer stack 100 to a tape frame 400. The wafer stack 100 is mounted on top of a tape frame 400. The tape frame 400 may comprise a carrier on which a temporary adhesive is coated. The bonding process may be performed in a chamber in which the wafer stack 100 is bonded on top of the tape frame 400. The bonding process of attaching a wafer stack to a tape frame is well known in the art, and hence is not discussed in further detail herein.
  • FIG. 4 further illustrates a process of separating the wafer stack 100 into a plurality of individual packages using a dicing process. As shown in FIG. 4, a plurality of individual packages such as a first package 402 and a second package 404 are formed by sawing the wafer stack 100 into individual packages. Each individual package may include at least one semiconductor die bonded on a die (e.g., die 102 a). The dicing process is well known in the art, and hence is not discussed in detail herein. It should be noted while FIG. 4 shows the side having a plurality of semiconductor dies of the wafer stack 100 (opposite to the flip chip bump side) is attached to the tape frame 400, and then a sawing process is performed, a person skilled in the art will recognize that there can be many variations of an embodiment of this disclosure. For example, the flip chip bump side of the wafer stack 100 can be attached to the tape frame 400. A sawing process can also be performed from the semiconductor die side of the wafer stack 100.
  • FIG. 5 illustrates a cross sectional view of the 3D IC after the dicing process. As shown in FIG. 5, the packages 402 and 404 (not shown but illustrated in FIG. 4) have been removed from the tape frame 400 (not shown) by employing a pick-and-place process. The pick-and-place process is well known in the art, and hence is not discussed in further detail to avoid repetition. The surfaces of both the first package 402 and the second 404 may be further polished by a chemical solvent, and then are flipped again. Subsequently, the individual packages such as the first package 402 are mounted on a substrate 502 to form a 3D IC. In accordance with an embodiment, the substrate 502 may be an organic based substrate. Furthermore, in order to reduce mechanical and thermal stresses, an underfill material 504 is formed in the gap between the first package 402 and the substrate 502.
  • FIGS. 6-10 are cross sectional views of intermediate stages in the making of a 3D IC in accordance with another embodiment. FIGS. 6-10 are similar to FIGS. 1-5 except that the molding compound layer 702 in FIG. 7 is extended to cover the edge of the wafer 102. In order to protect the edge of the wafer 102 during process steps such as dicing the wafer stack 100 into separate chip packages, the molding compound layer 702 is employed to keep the edge from cracking. The process of forming the molding compound layer 702 is similar to that of forming the molding compound layer 202, and hence is not discussed in further detail to avoid unnecessary repetition. The process procedures of grinding the backside of the wafer 102, attaching the wafer stack 100 to a tape frame 400 and sawing the wafer stack 100 into a plurality of individual packages have been described with respect to FIGS. 3-5, and hence are not discuss again to avoid repetition.
  • FIGS. 11-15 are cross sectional views of intermediate stages in the making of a 3D IC in accordance with yet another embodiment. FIGS. 11-15 are similar to FIGS. 1-5 except that an additional protection material 1202 are formed between the edge of the molding compound layer 202 and the edge of the wafer 102. In order to protect the edge of the wafer 102 during process steps such as dicing the wafer into separate chip packages, the molding compound layer 702 is employed to keep the edges from cracking. In addition, an additional protection material 1202 is employed to provide a cushion region absorbing mechanical and thermal stresses during the process of fabricating the 3D IC. The additional protection material 1202 may be formed by dispensing, laminating and/or printing the additional protection material between the edge of the molding compound layer 202 and the edge of the wafer 102. In accordance with an embodiment, the protection material 1202 may a polymer material such as polyimide (PI), epoxy and/or the like. The process procedures of grinding the backside of the wafer 102, attaching the wafer stack 100 to a tape frame 400 and sawing the wafer stack 100 into a plurality of individual packages have been described with respect to FIGS. 3-5, and hence are not discuss again to avoid repetition.
  • In accordance with an embodiment, a method comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first side of a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises thinning a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
  • In accordance with another embodiment, a method comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first side of a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the first molding compound layer and extending the molding compound layer covering an outer edge of the first semiconductor die. The method further comprises thinning a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
  • In accordance with yet another embodiment, a structure comprises a substrate layer and a first semiconductor die mounted on the substrate layer. The first semiconductor die comprises a plurality of bumps on a first side of the first semiconductor die, a plurality of micro bumps on a second side of the first semiconductor die and a redistribution layer formed on top of the second side of the first semiconductor die. The structure further comprises a plurality of semiconductor dies mounted on top of the second side of the first semiconductor die.
  • Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
  • Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (19)

    What is claimed is:
  1. 1. A method comprising:
    providing a stack wherein a plurality of semiconductor dies are mounted on a first side of a wafer;
    forming a molding compound layer on the first side of the wafer, wherein the plurality of semiconductor dies are embedded in the molding compound layer;
    thinning a second side of the wafer until a plurality of through vias become exposed;
    attaching the stack to a tape frame; and
    dicing the stack to separate the stack into a plurality of individual packages.
  2. 2. The method of claim 1, further comprising:
    forming a first underfill layer between the wafer and the plurality of semiconductor dies.
  3. 3. The method of claim 1, further comprising:
    forming the plurality of through vias in the wafer;
    forming a plurality of first bumps on the first side of the wafer; and
    forming a first redistribution layer on the first side of the wafer.
  4. 4. The method of claim 3, wherein the plurality of semiconductor dies are connected to the wafer through the plurality of first bumps and the first redistribution layer.
  5. 5. The method of claim 1, further comprising:
    forming a plurality of second bumps on the second side of the wafer; and
    forming a second redistribution layer on the second side of the wafer.
  6. 6. The method of claim 1, further comprising:
    detaching each individual package from the tape frame.
  7. 7. The method of claim 6, further comprising:
    attaching the individual package on a substrate.
  8. 8. The method of claim 1, further comprising:
    forming a protection layer between an outer edge of the molding compound layer and an outer edge of the stack.
  9. 9. A method comprising:
    providing a stack wherein a plurality of semiconductor dies are mounted on a first side of a wafer, wherein the wafer comprises a plurality of through vias;
    forming a molding compound layer on the first side of the wafer, wherein the plurality of semiconductor dies are embedded in the first molding compound layer;
    extending the molding compound layer covering an outer edge of the wafer;
    thinning a second side of the wafer to expose the plurality of through vias;
    attaching the stack to a tape frame; and
    dicing the stack to separate the stack into a plurality of individual packages.
  10. 10. The method of claim 9, further comprising:
    detaching each individual package from the tape frame; and
    attaching the individual package to a substrate.
  11. 11. The method of claim 10, further comprising:
    forming a first underfill layer between the wafer and the plurality of semiconductor dies; and
    forming a second underfill layer between the individual package and the substrate.
  12. 12. The method of claim 9, further comprising:
    cleaning a surface of the individual package; and
    cleaning the outer edge of the wafer.
  13. 13. The method of claim 9, further comprising:
    chemically polishing the second side of the wafer;
    forming a second redistribution layer on the second side of the wafer; and
    forming a plurality of bumps on the second side of the wafer.
  14. 14. The method of claim 13, further comprising:
    forming a first redistribution layer on the first side of the wafer; and
    forming a plurality of bumps electrically coupled to the first redistribution layer on the first side of the wafer.
  15. 15. A structure comprising:
    a substrate; and
    a stack mounted on the substrate comprising:
    a plurality of semiconductor dies bonded on a first side of a die; and
    a molding compound layer formed on the first side of the die and covering an outer edge of the die, wherein the plurality of semiconductor dies are embedded in the molding compound layer.
  16. 16. The structure of claim 15, further comprising a plurality of bumps formed between the substrate and the stack.
  17. 17. The structure of claim 15, wherein the plurality of semiconductor dies are coupled to the die using a plurality of first bumps.
  18. 18. The structure of claim 15, further comprising:
    a first underfill layer formed between the plurality of semiconductor dies and the die; and
    a second underfill layer formed between the die and the substrate.
  19. 19. The structure of claim 15, further comprising:
    a plurality of through vias in the die.
US13246553 2011-09-27 2011-09-27 Method for Three Dimensional Integrated Circuit Fabrication Abandoned US20130075892A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13246553 US20130075892A1 (en) 2011-09-27 2011-09-27 Method for Three Dimensional Integrated Circuit Fabrication

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13246553 US20130075892A1 (en) 2011-09-27 2011-09-27 Method for Three Dimensional Integrated Circuit Fabrication
CN 201210189854 CN103021960B (en) 2011-09-27 2012-06-08 A method for producing a three-dimensional integrated circuit
CN 201510438633 CN105118788A (en) 2011-09-27 2012-06-08 Method for three dimensional integrated circuit fabrication
CN 201510438514 CN105118810A (en) 2011-09-27 2012-06-08 Method for three dimensional integrated circuit fabrication

Publications (1)

Publication Number Publication Date
US20130075892A1 true true US20130075892A1 (en) 2013-03-28

Family

ID=47910369

Family Applications (1)

Application Number Title Priority Date Filing Date
US13246553 Abandoned US20130075892A1 (en) 2011-09-27 2011-09-27 Method for Three Dimensional Integrated Circuit Fabrication

Country Status (2)

Country Link
US (1) US20130075892A1 (en)
CN (3) CN105118810A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870052A (en) * 2015-01-21 2016-08-17 无锡超钰微电子有限公司 Manufacturing method of ultrathin semiconductor element encapsulation structure

Citations (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5268065A (en) * 1992-12-21 1993-12-07 Motorola, Inc. Method for thinning a semiconductor wafer
US5292686A (en) * 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US20020081771A1 (en) * 2000-12-22 2002-06-27 Yi-Chuan Ding Flip chip process
US6426545B1 (en) * 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US20030009864A1 (en) * 2001-07-12 2003-01-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter package
US20030109077A1 (en) * 2001-12-07 2003-06-12 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter packages
US20050181543A1 (en) * 2002-08-28 2005-08-18 Shih-Chang Lee Semiconductor package module and manufacturing method thereof
US20060208352A1 (en) * 2005-03-17 2006-09-21 Hsin-Hui Lee Strain silicon wafer with a crystal orientation (100) in flip chip BGA package
US7112467B2 (en) * 2000-02-10 2006-09-26 Epic Technologies, Inc. Structure and method for temporarily holding integrated circuit chips in accurate alignment
US20060272676A1 (en) * 2005-06-01 2006-12-07 Masao Iwase Cleaning method and a cleaning device for cleaning an edge portion and back face of a wafer
US20080289651A1 (en) * 2007-05-25 2008-11-27 International Business Machines Corporation Method and apparatus for wafer edge cleaning
US7553752B2 (en) * 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US20090200662A1 (en) * 2008-02-12 2009-08-13 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US20100047970A1 (en) * 2007-06-25 2010-02-25 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US20100117226A1 (en) * 2008-11-07 2010-05-13 Ku-Feng Yang Structure and method for stacked wafer fabrication
US20100159643A1 (en) * 2008-12-19 2010-06-24 Texas Instruments Incorporated Bonding ic die to tsv wafers
US20100233855A1 (en) * 2006-12-12 2010-09-16 Siliconware Precision Industries Co., Ltd. Method for fabricating chip scale package structure with metal pads exposed from an encapsulant
US20100244284A1 (en) * 2009-03-27 2010-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for ultra thin wafer handling and processing
US7820487B2 (en) * 2006-09-27 2010-10-26 Fujitsu Semiconductor Limited Manufacturing method of semiconductor device
US20100320587A1 (en) * 2009-06-22 2010-12-23 Lee Kyunghoon Integrated circuit packaging system with underfill and method of manufacture thereof
US20110000503A1 (en) * 2009-07-06 2011-01-06 Lai Hon Keung Acoustic cleaning system for electronic components
US20110006404A1 (en) * 2009-07-08 2011-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of wafer level chip molded packaging
US7883991B1 (en) * 2010-02-18 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Temporary carrier bonding and detaching processes
US20110062596A1 (en) * 2009-09-14 2011-03-17 Shinko Electric Industries Co., Ltd. Semiconductor chip stacked structure and method of manufacturing same
US20110193221A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Interposer for Bonding Dies
US20110217812A1 (en) * 2008-02-22 2011-09-08 Harry Hedler Integrated circuit device and method for fabricating same with an interposer substrate
US20110272825A1 (en) * 2009-11-04 2011-11-10 Vertical Circuits, Inc. Stacked die assembly having reduced stress electrical interconnects
US20110278736A1 (en) * 2008-12-12 2011-11-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US8105875B1 (en) * 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US20120040500A1 (en) * 2010-08-16 2012-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Molding Chamber
US20120074585A1 (en) * 2010-09-24 2012-03-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer
US20120074587A1 (en) * 2010-09-29 2012-03-29 Stats Chippac, Ltd. Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level
US8304891B2 (en) * 2008-05-28 2012-11-06 Siliconware Precision Industries Co., Ltd. Semiconductor package device, semiconductor package structure, and fabrication methods thereof
US20130032946A1 (en) * 2011-08-04 2013-02-07 Texas Instruments Incorporated Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
US20130037990A1 (en) * 2011-08-11 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Molding Wafer Chamber
US20130037935A1 (en) * 2011-08-09 2013-02-14 Yan Xun Xue Wafer level package structure and the fabrication method thereof
US20130049195A1 (en) * 2011-08-23 2013-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-Dimensional Integrated Circuit (3DIC) Formation Process
US20130049234A1 (en) * 2011-08-24 2013-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate Dicing
US20130056865A1 (en) * 2011-09-02 2013-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Three Dimensional Integrated Circuit Assembly
US20130078767A1 (en) * 2011-09-23 2013-03-28 Globalfoundries Inc. Methods for fabricating integrated circuit systems including high reliability die under-fill
US8446000B2 (en) * 2009-11-24 2013-05-21 Chi-Chih Shen Package structure and package process
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001024260A1 (en) * 1999-09-24 2001-04-05 Virginia Tech Intellectual Properties, Inc. Low cost 3d flip-chip packaging technology for integrated power electronics modules
US6949822B2 (en) * 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
US7098544B2 (en) * 2004-01-06 2006-08-29 International Business Machines Corporation Edge seal for integrated circuit chips
KR100640580B1 (en) * 2004-06-08 2006-10-31 삼성전자주식회사 Semiconductor package covered with a encapsulant in a side portion and method of manufacturing the same
CN102024798A (en) * 2009-09-17 2011-04-20 胡泉凌 Packaging structure used for integrating surface adhesive type assembly
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US9136144B2 (en) * 2009-11-13 2015-09-15 Stats Chippac, Ltd. Method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates

Patent Citations (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5292686A (en) * 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
US5268065A (en) * 1992-12-21 1993-12-07 Motorola, Inc. Method for thinning a semiconductor wafer
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6426545B1 (en) * 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US7112467B2 (en) * 2000-02-10 2006-09-26 Epic Technologies, Inc. Structure and method for temporarily holding integrated circuit chips in accurate alignment
US20020081771A1 (en) * 2000-12-22 2002-06-27 Yi-Chuan Ding Flip chip process
US20030009864A1 (en) * 2001-07-12 2003-01-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter package
US20030109077A1 (en) * 2001-12-07 2003-06-12 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter packages
US6670206B2 (en) * 2001-12-07 2003-12-30 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter packages
US6928719B2 (en) * 2001-12-07 2005-08-16 Samsung Electro-Mechanics Co., Ltd. Method for fabricating surface acoustic wave filter package
US20050181543A1 (en) * 2002-08-28 2005-08-18 Shih-Chang Lee Semiconductor package module and manufacturing method thereof
US20060208352A1 (en) * 2005-03-17 2006-09-21 Hsin-Hui Lee Strain silicon wafer with a crystal orientation (100) in flip chip BGA package
US20060272676A1 (en) * 2005-06-01 2006-12-07 Masao Iwase Cleaning method and a cleaning device for cleaning an edge portion and back face of a wafer
US7820487B2 (en) * 2006-09-27 2010-10-26 Fujitsu Semiconductor Limited Manufacturing method of semiconductor device
US20100233855A1 (en) * 2006-12-12 2010-09-16 Siliconware Precision Industries Co., Ltd. Method for fabricating chip scale package structure with metal pads exposed from an encapsulant
US20080289651A1 (en) * 2007-05-25 2008-11-27 International Business Machines Corporation Method and apparatus for wafer edge cleaning
US7553752B2 (en) * 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
US20090261460A1 (en) * 2007-06-20 2009-10-22 Stats Chippac, Ltd. Wafer Level Integration Package
US20100047970A1 (en) * 2007-06-25 2010-02-25 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US20090200662A1 (en) * 2008-02-12 2009-08-13 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US7948095B2 (en) * 2008-02-12 2011-05-24 United Test And Assembly Center Ltd. Semiconductor package and method of making the same
US20110217812A1 (en) * 2008-02-22 2011-09-08 Harry Hedler Integrated circuit device and method for fabricating same with an interposer substrate
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US8304891B2 (en) * 2008-05-28 2012-11-06 Siliconware Precision Industries Co., Ltd. Semiconductor package device, semiconductor package structure, and fabrication methods thereof
US20100117226A1 (en) * 2008-11-07 2010-05-13 Ku-Feng Yang Structure and method for stacked wafer fabrication
US7955895B2 (en) * 2008-11-07 2011-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for stacked wafer fabrication
US20110278736A1 (en) * 2008-12-12 2011-11-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
US20100159643A1 (en) * 2008-12-19 2010-06-24 Texas Instruments Incorporated Bonding ic die to tsv wafers
US20100244284A1 (en) * 2009-03-27 2010-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for ultra thin wafer handling and processing
US20100320587A1 (en) * 2009-06-22 2010-12-23 Lee Kyunghoon Integrated circuit packaging system with underfill and method of manufacture thereof
US20110000503A1 (en) * 2009-07-06 2011-01-06 Lai Hon Keung Acoustic cleaning system for electronic components
US20110006404A1 (en) * 2009-07-08 2011-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of wafer level chip molded packaging
US20110062596A1 (en) * 2009-09-14 2011-03-17 Shinko Electric Industries Co., Ltd. Semiconductor chip stacked structure and method of manufacturing same
US20110272825A1 (en) * 2009-11-04 2011-11-10 Vertical Circuits, Inc. Stacked die assembly having reduced stress electrical interconnects
US8446000B2 (en) * 2009-11-24 2013-05-21 Chi-Chih Shen Package structure and package process
US20110193221A1 (en) * 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Interposer for Bonding Dies
US7883991B1 (en) * 2010-02-18 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Temporary carrier bonding and detaching processes
US8540506B2 (en) * 2010-08-16 2013-09-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor molding chamber
US20120040500A1 (en) * 2010-08-16 2012-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Molding Chamber
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US20120074585A1 (en) * 2010-09-24 2012-03-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer
US20120074587A1 (en) * 2010-09-29 2012-03-29 Stats Chippac, Ltd. Semiconductor Device and Method of Bonding Different Size Semiconductor Die at the Wafer Level
US20120104578A1 (en) * 2010-10-14 2012-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for Bonding Dies onto Interposers
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8105875B1 (en) * 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8319349B2 (en) * 2010-10-14 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US20130032946A1 (en) * 2011-08-04 2013-02-07 Texas Instruments Incorporated Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
US20130037935A1 (en) * 2011-08-09 2013-02-14 Yan Xun Xue Wafer level package structure and the fabrication method thereof
US20130037990A1 (en) * 2011-08-11 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Molding Wafer Chamber
US20130049195A1 (en) * 2011-08-23 2013-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-Dimensional Integrated Circuit (3DIC) Formation Process
US8557684B2 (en) * 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
US20130049234A1 (en) * 2011-08-24 2013-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate Dicing
US8569086B2 (en) * 2011-08-24 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of dicing semiconductor devices
US20130056865A1 (en) * 2011-09-02 2013-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Three Dimensional Integrated Circuit Assembly
US9418876B2 (en) * 2011-09-02 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of three dimensional integrated circuit assembly
US20130078767A1 (en) * 2011-09-23 2013-03-28 Globalfoundries Inc. Methods for fabricating integrated circuit systems including high reliability die under-fill

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105870052A (en) * 2015-01-21 2016-08-17 无锡超钰微电子有限公司 Manufacturing method of ultrathin semiconductor element encapsulation structure

Also Published As

Publication number Publication date Type
CN105118810A (en) 2015-12-02 application
CN103021960A (en) 2013-04-03 application
CN103021960B (en) 2015-11-04 grant
CN105118788A (en) 2015-12-02 application

Similar Documents

Publication Publication Date Title
US8426961B2 (en) Embedded 3D interposer structure
US8802504B1 (en) 3D packages and methods for forming the same
US8361842B2 (en) Embedded wafer-level bonding approaches
US8421193B2 (en) Integrated circuit device having through via and method for preparing the same
US8519537B2 (en) 3D semiconductor package interposer with die cavity
US20090243045A1 (en) Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
US8643148B2 (en) Chip-on-Wafer structures and methods for forming the same
US20140252646A1 (en) Interconnect Structure for Package-on-Package Devices
US20110193235A1 (en) 3DIC Architecture with Die Inside Interposer
US20140015131A1 (en) Stacked fan-out semiconductor chip
US20130307140A1 (en) Packaging with interposer frame
US8803306B1 (en) Fan-out package structure and methods for forming the same
US8975726B2 (en) POP structures and methods of forming the same
US20140217610A1 (en) 3D Semiconductor Package Interposer with Die Cavity
US20140091473A1 (en) Novel three dimensional integrated circuits stacking approach
US20140252572A1 (en) Structure and Method for 3D IC Package
US8105875B1 (en) Approach for bonding dies onto interposers
US20130217188A1 (en) Structures and Formation Methods of Packages with Heat Sinks
US20120049364A1 (en) Emebedded structures and methods of manufacture thereof
US20140001645A1 (en) 3DIC Stacking Device and Method of Manufacture
US20090004777A1 (en) Stacked die semiconductor package and method of assembly
US8754514B2 (en) Multi-chip wafer level package
US20110193221A1 (en) 3DIC Architecture with Interposer for Bonding Dies
US20130040423A1 (en) Method of Multi-Chip Wafer Level Packaging
US20130062760A1 (en) Packaging Methods and Structures Using a Die Attach Film

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, JING-CHENG;WU, WENG-JIN;SHIH, YING-CHING;AND OTHERS;SIGNING DATES FROM 20110830 TO 20110909;REEL/FRAME:026977/0201