CN102543772A - 结合晶片级不同尺寸半导体管芯的方法和半导体器件 - Google Patents

结合晶片级不同尺寸半导体管芯的方法和半导体器件 Download PDF

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CN102543772A
CN102543772A CN2011103491779A CN201110349177A CN102543772A CN 102543772 A CN102543772 A CN 102543772A CN 2011103491779 A CN2011103491779 A CN 2011103491779A CN 201110349177 A CN201110349177 A CN 201110349177A CN 102543772 A CN102543772 A CN 102543772A
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semiconductor element
semiconductor
conductive
carrier
conductive layer
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CN102543772B (zh
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具俊谟
P·C·马里穆图
S·W·尹
沈一权
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及结合晶片级不同尺寸半导体管芯的方法和半导体器件。半导体晶片具有第一和第二相对的表面。形成部分地穿过所述半导体晶片的第一表面的多个导电通孔。将所述半导体晶片单体化成多个第一半导体管芯。安装所述第一半导体管芯到载体。安装第二半导体管芯到所述第一半导体管芯。第二半导体管芯的占位面积比第一半导体管芯的占位面积大。在所述第一和第二半导体管芯以及载体上沉积密封剂。去除所述载体。去除第二表面的一部分以暴露导电通孔。在第一半导体管芯的与所述第二半导体管芯相对的表面上形成互连结构。可替换地，在第一半导体管芯和载体上沉积第一密封剂，并且在第二半导体管芯上沉积第二密封剂。

Description

结合晶片级不同尺寸半导体管芯的方法和半导体器件
要求国内优先权
本申请要求于2010年9月29日提交的临时申请No.61/387,595的优先权，并且根据35U.S.C.§120要求上述申请的优先权。
技术领域
本申请总体上涉及半导体器件，并且更具体地说涉及一种结合晶片级不同尺寸半导体管芯的方法和半导体器件。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件(CCD)、太阳能电池、以及数字微镜器件(DMD)。
半导体器件执行多种功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流(base current)或者通过掺杂工艺来操纵(manipulated)它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构(包括双极和场效应晶体管)控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器、和电感器)产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个半导体管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化(singulating)单个半导体管芯并且封装管芯以提供结构支撑和环境隔离。在此使用的术语“半导体管芯”不仅指词的单数形式而且指词的复数形式，并且因此不仅可以指单个半导体器件而且可以指多个半导体器件。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占位面积(footprint)，其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的半导体管芯的前端工艺可以实现更小的半导体管芯尺寸。通过改善电互连和密封剂，后端工艺可以产生具有更小占位面积的半导体器件封装。
图1示出了一种传统的半导体封装10，其中半导体管芯12利用凸块16安装在衬底14上。多个导电通孔18形成为穿过半导体管芯12。半导体管芯20利用凸块22安装在半导体管芯12上。密封剂24沉积在半导体管芯12和20和衬底14上。多个凸块26形成在与半导体管芯12和20相对的衬底14的表面上。
半导体管芯12可以是逻辑器件，且半导体管芯20可以是大储存存储器件。所以，半导体管芯20通常大于半导体管芯12。不同尺寸的半导体管芯使得晶片级结合困难。结合半导体管芯20到单个半导体管芯12增加了制造成本，并且在操作中可能产生裂缝缺陷。
发明内容
存在对在晶片级结合不同尺寸的半导体管芯的需要。相应地，在一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供具有第一和第二相对表面的半导体晶片，形成部分地穿过半导体晶片的第一表面的多个导电通孔，将半导体晶片单体化为多个第一半导体管芯，提供载体，安装所述第一半导体管芯到所述载体，安装第二半导体管芯到所述第一半导体管芯，在第一和第二半导体管芯以及载体上沉积密封剂，去除所述载体以及第二表面的一部分以暴露导电通孔，在第一半导体管芯的与所述第二半导体管芯相对的表面上形成互连结构。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供多个第一半导体管芯，形成穿过所述第一半导体管芯的多个导电通孔，提供载体，安装所述第一半导体管芯到所述载体，安装第二半导体管芯到所述第一半导体管芯，在第一和第二半导体管芯以及载体上沉积密封剂。第二半导体管芯的占位面积大于第一半导体管芯的占位面积。
在另一个实施例中，本发明是一种制造半导体器件的方法，该方法包括以下步骤：提供多个第一半导体管芯，形成穿过所述第一半导体管芯的多个导电通孔，提供载体，安装所述第一半导体管芯到所述载体，在第一半导体管芯和载体上沉积第一密封剂，去除所述载体，安装第二半导体管芯到第一半导体管芯，在第二半导体管芯上沉积第二密封剂。
在另一个实施例中，本发明是一种半导体器件，其包括第一半导体管芯，该第一半导体管芯具有被形成为穿过所述第一半导体管芯的多个导电通孔。第二半导体管芯被安装到第一半导体管芯。第二半导体管芯的占位面积大于第一半导体管芯的占位面积。密封剂被沉积在第一和第二半导体管芯上。互连结构与第二半导体管芯相对地形成在第一半导体管芯上。
附图说明
图1示出了具有不同尺寸半导体管芯的传统的Fo-WLCSP；
图2示出了具有安装到其表面的不同类型封装的印刷电路板(PCB)；
图3a-3c示出了示出安装到PCB的典型半导体封装的更多细节；
图4a-4c示出了具有被划片街区(saw street)分开的多个半导体管芯的半导体晶片；
图5a-5p示出了在晶片级结合不同尺寸半导体管芯的工艺；
图6示出了具有根据图5a-5p被结合在一起的不同尺寸半导体管芯的Fo-WLCSP；
图7a-7q示出了在晶片级结合不同尺寸半导体管芯的另一个工艺；
图8示出了具有根据图7a-7q被结合在一起的不同尺寸半导体管芯的Fo-WLCSP；
图9示出了被安装到TSV半导体管芯的三个叠置半导体管芯；以及
图10示出了被形成为穿过围绕TSV半导体管芯的密封剂的导电通孔。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积(CVD)、物理汽相沉积(PVD)、电解电镀、以及无电极电镀(electroless plating)工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。在一个实施例中，利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。在另一个实施例中，利用溶剂将未经受光的光致抗蚀剂(负性光致抗蚀剂)图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌(topography)，产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化半导体管芯，沿被叫做划片街区或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个半导体管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块(stud bump)、导电胶、或线结合(wirebond)来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图2示出具有芯片载体衬底或印刷电路板(PCB)52的电子器件50，所述芯片载体衬底或印刷电路板(PCB)52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图2中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是蜂窝式电话、个人数字助理(PDA)、数码摄像机(DVC)或其它电子通信装置的一部分。可替换地，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。对于将被市场接受的这些产品而言，小型化和减轻重量是必需的。半导体器件之间的距离必须被减小以实现更高的密度。
在图2中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线(trace)54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括接合线封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列(BGA)60、凸块芯片载体(BCC)62、双列直插式封装(DIP)64、岸面栅格阵列(land grid array，LGA)66、多芯片模块(MCM)68、四侧无引脚扁平封装(quad flat non-leadedpackage，QFN)70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图3a-3c示出示范性半导体封装。图3a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是一层或多层的导电材料，例如铝(AL)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、或银(Ag)，并且电连接到形成在半导体管芯74内的电路元件。在DIP 64的组装期间，利用金硅共晶层或粘附材料(例如热的环氧或环氧树脂)将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和接合线82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染半导体管芯74或接合线82来进行环境保护。
图3b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。接合线94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和接合线94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB 52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图3c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
图4a示出具有用于结构支撑的基底衬底材料122(例如硅、锗、砷化镓、磷化铟、或碳化硅)的半导体晶片120。多个半导体管芯或部件124形成在晶片120上，被管芯间的晶片区域或划片街区126分开，如上所述。划片街区126提供切割区域以将半导体晶片120单体化成单个半导体管芯124。
图4b示出半导体晶片120的一部分的截面图。每个半导体管芯124具有后表面128和有源表面130，所述有源表面130包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器(DSP)、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括集成无源器件(IPD)，例如电感器、电容器、和电阻器，用于RF信号处理。在一个实施例中，半导体管芯124是倒装芯片型半导体管芯。
利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面130上形成导电层132。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层132用作电连接到有源表面130上的电路的接触焊盘。可以离半导体管芯124的边缘第一距离并排设置接触焊盘132，如图4b中所示。可替换地，接触焊盘132可以多行偏移使得第一行接触焊盘被设置得离管芯的边缘为第一距离，并且与第一行交替的第二行接触焊盘被设置得离管芯的边缘为第二距离。
在图4c中，利用锯条或激光切割工具134，通过划片街区126，半导体晶片120被单体化成单个半导体管芯124。
相对于图2和图3a-3c，图5a-5p示出了在晶片级结合不同尺寸半导体管芯的工艺。图5a示出包含基底材料(例如硅、锗、砷化镓、磷化铟、或碳化硅)的半导体晶片或衬底140，用于结构支撑。多个半导体管芯或部件142形成在晶片140上，如上所述地被管芯间的晶片区域或划片街区143分离。划片街区143提供将半导体晶片140单体化为单个半导体管芯142的切割区域。
每一个半导体管芯142具有后表面145和有源表面144，所述有源表面144包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面144内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯142也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
在图5b中，利用机械钻孔、激光钻孔、或深反应离子刻蚀(DRIE)形成部分地穿过衬底140的多个盲通孔146。通孔146从有源表面144延伸，部分地但不完全地穿过衬底140。在一个实施例中，通孔146贯通衬底140的厚度的60％。在通孔146和后表面145之间的衬底140的剩余部分在随后的制造工艺期间为衬底提供结构支撑。
在图5c中，利用电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、钛(Ti)、钨(W)、多晶硅、或其它合适的导电材料填充通孔146以形成z方向导电直通硅通孔(TSV)148。
在图5d中，利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在衬底140的有源表面144上形成导电层150。导电层150可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层150充当用于电互连的接触焊盘或凸块下金属化(UBM)层。导电层150也包括用于水平和垂直地路由电信号的再分配层(RDL)和z方向导电通孔。导电层150的一部分电连接到导电通孔148。导电层150的其它部分可以根据半导体管芯124和142的设计和功能是电共有的(electrically common)或被电隔离。
利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在衬底140的有源表面144上以及导电层150的周围形成绝缘或钝化层152。绝缘层152包括一层或多层的二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、或具有类似绝缘和结构特性的其它材料。通过光致抗蚀剂层(未示出)借助刻蚀工艺除去绝缘层152的一部分以暴露导电层150。可替换地，绝缘层152可以在导电层150之前形成。
在图5e中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在导电层150的暴露部分上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层150。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块154。在一些应用中，凸块154被二次回流以改善到导电层150的电接触。凸块154也可以被压缩结合到导电层150。凸块154表示一种可以形成在导电层150上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
在图5f中，利用锯条或激光切割工具158，通过划片街区143，TSV衬底140被单体化成单个TSV半导体管芯142。在一个实施例中，TSV半导体管芯142包含逻辑电路。
在图5g中，临时衬底或载体162包括牺牲基底材料，例如硅、聚合物、氧化铍、或其它合适的低成本、刚性材料，用于结构支撑。界面层或双面胶带164形成在载体162上作为临时粘附结合膜或刻蚀停层。利用拾取和放置操作将TSV半导体管芯142放置在界面层164和载体162上并且安装到界面层164和载体162，其中凸块154取向远离载体。被安装到载体162的TSV半导体管芯142构成重新配置的晶片168，如图5h所示。
在图5i中，使用拾取和放置操作将图4a-4c的半导体管芯124安装到TSV半导体管芯142，其中有源表面130面向TSV半导体管芯。在低于220℃的低温下，凸块154被回流以将TSV半导体管芯142的导电层150电连接到半导体管芯124的导电层132。图5j示出了在重新构成的晶片级用冶金的方法并且电性地连接到TSV半导体管芯142的半导体管芯124。半导体管芯124可以是具有大存储容量的存储器件，而TSV半导体管芯142包括与存储器件相互作用的逻辑电路。由于大存储容量存储器件的性质，半导体管芯124具有比包含逻辑电路的TSV半导体管芯142大得多的占位面积。在一个实施例中，半导体管芯124在存储器应用中具有10mm×10mm的占位面积，而TSV管芯142在移动CPU、GPU和基带信号处理应用中具有8mm×8mm的占位面积。
TSV半导体管芯142以足够的间距被放置在载体162上，以便为半导体管芯124的安装留出余地，其中在半导体管芯之间具有开口区域，用于将密封剂向下沉积到载体162和界面层164。可选的底部填充材料166围绕凸块154沉积在半导体管芯124和TSV半导体管芯142之间。
在图5k中，利用浆料印刷(paste printing)、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器(applicator)在半导体管芯124、TSV半导体管芯142和载体162上以及周围以重新构成的晶片级沉积密封剂或模塑料170。在没有底部填充材料166的情况下，密封剂170沉积在半导体管芯124和TSV半导体管芯142之间。密封剂170可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂170不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在另一个实施例中，利用底部填充(MUF)工艺在半导体管芯124和TSV半导体管芯142上以及周围以重新构成的晶片级沉积模塑底部填充材料172，如图5l所示。模套(chase mold)174具有上模支撑176和下模支撑178，它们在一起将半导体管芯124和TSV半导体管芯142围住，其中具有开放空间180。利用注口182将液态的MUF材料172注入到模套174的一侧中，同时可选的真空辅助器184从相对的一侧抽压，以利用MUF材料均匀地填充围绕半导体管芯124和TSV半导体管芯142的开放空间180。MUF材料172可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。MUF材料172形成在半导体管芯124和TSV半导体管芯142周围和之间并被固化，如图5m所示。
从图5k继续，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来去除载体162和界面层164，以暴露半导体管芯142的后表面145，如图5n所示。利用研磨器190去除一部分的衬底140的基底材料和密封剂170或MUF材料172，以暴露导电通孔148。
图5o示出了在研磨操作之后被密封剂170或MUF材料172覆盖的半导体管芯124和TSV半导体管芯142。装配互连结构194与半导体管芯124相对地形成在TSV半导体管芯142的表面上。装配互连结构194包括利用图案化和金属沉积工艺(例如溅射、电解电镀、和无电极电镀)形成的导电层或RDL 196。导电层196可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层196包括用于电互连的水平和垂直部分。导电层196的一部分电连接到导电通孔148。导电层196的其它部分可以根据半导体管芯124和142的设计和功能是电共有的或被电隔离。
利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在导电层196周围和之间形成绝缘或钝化层198用于电隔离。绝缘层198包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。可以通过光致抗蚀剂层借助刻蚀工艺除去绝缘层198的一部分以暴露导电层196，用于凸块形成或另外的封装互连。装配互连结构194借助导电层150、凸块154和导电通孔148电连接到半导体管芯124。
在图5p中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺，导电凸块材料被沉积在装配互连结构194的暴露的导电层196上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层196。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块200。在一些应用中，凸块200被二次回流以改善到导电层196的电接触。UBM层可以形成在凸块200下面。凸块200也可以被压缩结合到导电层196。凸块200表示一种可以形成在导电层196上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具202，穿过密封剂170和装配互连结构194，半导体管芯124被单体化成单个扇出型晶片级芯片规模封装(Fo-WLCSP)或嵌入式晶片级球栅阵列(eWLB)204。图6示出了单体化之后的Fo-WLCSP 204。半导体管芯124可以大于TSV半导体管芯142，尤其是在半导体管芯为具有大存储容量和用于高节点技术(例如32-40纳米(nm))的存储器件的情况下。通过形成重新构成的晶片并以足够的间距将TSV半导体管芯142安装到载体162，较大的半导体管芯124可以在重新构成的晶片级被结合到TSV半导体管芯，其中在半导体管芯和TSV半导体管芯之间具有开口区域，用于沉积密封剂170或MUF材料172。装配互连结构194也是在重新构成的晶片级形成。具有密封剂170的重新构成的晶片保护半导体管芯124，并且为装配互连结构194的形成提供支撑。重新构成的晶片级密封和互连结构形成还减小了操作损伤和破裂的风险，以及提供了一种简单且低成本的制造工艺。TSV半导体管芯142的背部研磨暴露了用于垂直互连的导电通孔148，并且减小了Fo-WLCSP 204的厚度。
半导体管芯124通过凸块154、导电层150和导电通孔148电连接到装配互连结构194。具有导电通孔148、导电层150、绝缘层152和凸块154的TSV半导体管芯142提供了一种用于半导体管芯124的垂直互连的简单且节省成本的结构，也提供了穿过TSV半导体管芯的导电层和装配互连结构194的有效封装堆叠。由于TSV半导体管芯142可以使用与半导体管芯124类似的材料制造并且装配互连结构194形成在与半导体管芯124和密封剂170相对的TSV半导体管芯142的表面上，因此TSV半导体管芯142消除了半导体管芯和装配互连结构之间的CTE失配。TSV半导体管芯142用作在TSV半导体管芯的一侧的半导体管芯124和在TSV半导体管芯的相对侧的装配互连结构194之间的缓冲，以减小翘曲。TSV半导体管芯142为半导体管芯124提供适合于高I/O数应用的细间距垂直互连。
相对于图2和图3a-3c，图7a-7q示出了在晶片级结合不同尺寸半导体管芯的另一个工艺。图7a示出包含基底材料(例如硅、锗、砷化镓、磷化铟、或碳化硅)的半导体晶片或衬底210，用于结构支撑。多个半导体管芯或部件212形成在晶片210上，如上所述地被管芯间的晶片区域或划片街区213分离。划片街区213提供将半导体晶片210单体化为单个半导体管芯212的切割区域。
每一个半导体管芯212具有后表面215和有源表面214，所述有源表面214包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面214内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯212也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。
在图7b中，利用机械钻孔、激光钻孔、或DRIE形成部分地穿过衬底210的多个盲通孔216。通孔216从表面212延伸，部分地但不完全地穿过衬底210。在一个实施例中，通孔216贯通衬底210的厚度的60％。在通孔216和后表面215之间的衬底210的剩余部分在随后的制造工艺期间为衬底提供结构支撑。
在图7c中，利用电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料填充通孔216以形成z方向导电TSV218。
在图7d中，利用锯条或激光切割工具219，通过划片街区213，TSV衬底210被单体化成单个TSV半导体管芯212。在一个实施例中，TSV半导体管芯212包含逻辑电路。
在图7e中，临时衬底或载体222包括牺牲基底材料，例如硅、聚合物、氧化铍、或其它合适的低成本、刚性材料，用于结构支撑。界面层或双面胶带224形成在载体222上作为临时粘附结合膜或刻蚀停层。利用拾取和放置操作将TSV半导体管芯212放置在界面层224和载体222上并且安装到界面层224和载体222，其中后表面215面向载体。被安装到载体162的TSV半导体管芯212构成重新配置的晶片226，如图7f所示。
在图7g中，利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器在TSV半导体管芯212和载体222上以重新构成的晶片级沉积密封剂或模塑料228。密封剂228可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂228不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图7h中，通过化学腐蚀、机械剥离、CMP、机械研磨、热烘、UV光、激光扫描、或湿法脱模来去除载体222和界面层224，以暴露衬底210的后表面215。利用研磨器229去除一部分的衬底210的基底材料和密封剂228，以暴露导电通孔218。
在图7i中，利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在TSV半导体管芯212的表面227上形成导电层230。导电层230可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层230充当用于电互连的接触焊盘或UBM层。导电层230也包括用于水平和垂直地路由电信号的再分配层和z方向导电通孔。导电层230的一部分电连接到导电通孔218。导电层230的其它部分可以根据半导体管芯124和212的设计和功能是电共有的或被电隔离。
利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在TSV半导体管芯212的表面227上以及导电层230的周围形成绝缘或钝化层232。绝缘层232包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。通过光致抗蚀剂层借助刻蚀工艺除去绝缘层232的一部分以暴露导电层230。可替换地，绝缘层232可以在导电层230之前形成。
在图7j中，在利用凸块234的情况下，使用拾取和放置操作将图4a-4c的半导体管芯124安装到TSV半导体管芯212，其中有源表面130面向TSV半导体管芯。在低于220℃的低温下，凸块234被回流以将导电层230电连接到半导体管芯124的导电层132。图7k示出了在重新构成的晶片级用冶金的方法并且电性地连接到TSV半导体管芯212的半导体管芯124。半导体管芯124可以是具有大存储容量的存储器件，而TSV半导体管芯212包括与存储器件相互作用的逻辑电路。由于大存储容量存储器件的性质，半导体管芯124具有比包含逻辑电路的TSV半导体管芯212大得多的占位面积。在一个实施例中，半导体管芯124在存储器应用中具有10mm×10mm的占位面积，而TSV管芯212在移动CPU、GPU和基带信号处理应用中具有8mm×8mm的占位面积。TSV半导体管芯212以足够的间距被放置以便为半导体管芯124的安装留出余地，其中在半导体管芯之间具有开口区域，用于将密封剂向下沉积到导电层230和界面层232。可选的底部填充材料236围绕凸块234沉积在半导体管芯124和TSV半导体管芯212之间。
在图7l中，利用浆料印刷、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器在半导体管芯124和TSV半导体管芯212上以及周围以重新构成的晶片级沉积密封剂或模塑料240。在没有底部填充材料236的情况下，密封剂240沉积在半导体管芯124和TSV半导体管芯212之间。密封剂240可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂240不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在另一个实施例中，利用MUF工艺在半导体管芯124和TSV半导体管芯212上以及周围以重新构成的晶片级沉积MUF材料242，如图7m所示。模套244具有上模支撑246和下模支撑248，它们在一起将半导体管芯124和TSV半导体管芯212围住，其中具有开放空间250。利用注口252将液态的MUF材料242注入到模套244的一侧中，同时可选的真空辅助器254从相对的一侧抽压，以利用MUF材料均匀地填充围绕半导体管芯124和TSV半导体管芯212的开放空间250。MUF材料242可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。MUF材料242形成在半导体管芯124和TSV半导体管芯212周围和之间并被固化，如图7n所示。
在图7o中，利用研磨器258去除一部分的密封剂240或MUF材料242，以暴露导电通孔218。
图7p示出了在研磨操作之后被密封剂240或MUF材料242包围的半导体管芯124和TSV半导体管芯212。装配互连结构260与半导体管芯124相对地形成在TSV半导体管芯212的有源表面214上。装配互连结构260包括利用图案化和金属沉积工艺(例如溅射、电解电镀、和无电极电镀)形成的导电层或RDL 262。导电层262可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层262包括用于电互连的水平和垂直部分。导电层262的一部分电连接到导电通孔218。导电层262的其它部分可以根据半导体管芯124和212的设计和功能是电共有的或被电隔离。
利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在导电层262周围和之间形成绝缘或钝化层264用于电隔离。绝缘层264包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。可以通过光致抗蚀剂层借助刻蚀工艺除去绝缘层264的一部分以暴露导电层262，用于凸块形成或另外的封装互连。装配互连结构260借助导电层230、凸块234和导电通孔218电连接到半导体管芯124。
在图7q中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺，导电凸块材料被沉积在装配互连结构260的暴露的导电层262上。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层262。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块266。在一些应用中，凸块266被二次回流以改善到导电层262的电接触。UBM层可以形成在凸块266下面。凸块266也可以被压缩结合到导电层262。凸块266表示一种可以形成在导电层262上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具268，穿过密封剂240和装配互连结构260，半导体管芯124被单体化成单个Fo-WLCSP或eWLB 270。图8示出了单体化之后的Fo-WLCSP 270。半导体管芯124可以大于TSV半导体管芯212，尤其是在半导体管芯为具有大存储容量和用于高节点技术(例如32-40纳米(nm))的存储器件的情况下。通过形成重新构成的晶片并以足够的间距将TSV半导体管芯212安装到载体222，较大的半导体管芯124可以在重新构成的晶片级被结合到TSV半导体管芯212，其中在半导体管芯124和TSV半导体管芯212之间具有开口区域，用于沉积密封剂240或MUF材料242。装配互连结构260也是在重新构成的晶片级形成。具有密封剂240的重新构成的晶片保护半导体管芯124，并且为装配互连结构260的形成提供支撑。重新构成的晶片级密封和互连结构形成还减小了操作损伤和破裂的风险，以及提供了一种简单且低成本的制造工艺。衬底210的背部研磨暴露了用于垂直互连的导电通孔218，并且减小了Fo-WLCSP 270的厚度。
半导体管芯124通过凸块234、导电层230和导电通孔218电连接到装配互连结构260。具有导电通孔218、导电层230、绝缘层232和凸块234的TSV半导体管芯212提供了一种用于半导体管芯124的垂直互连的简单且节省成本的结构，也提供了穿过TSV半导体管芯的导电层和装配互连结构260的有效封装堆叠。由于TSV半导体管芯212可以使用与半导体管芯124类似的材料制造并且装配互连结构260形成在与半导体管芯124和密封剂240相对的TSV半导体管芯212的有源表面214上，因此TSV半导体管芯212消除了半导体管芯124和装配互连结构260之间的CTE失配。TSV半导体管芯212用作在TSV半导体管芯的一侧的半导体管芯124和在TSV半导体管芯的相对侧的装配互连结构260之间的缓冲，以减小翘曲。TSV半导体管芯212为半导体管芯124提供适合于高I/O数应用的细间距垂直互连。
图9示出了类似于图6的Fo-WLCSP 272的实施例，其中多个半导体管芯堆叠在TSV半导体管芯212上。半导体管芯274和276来源于类似于图4a-4c的半导体晶片。每一个半导体管芯274-276具有后表面和有源表面，所述有源表面包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面190内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯274-276也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘形成在有源表面上并且电连接到有源表面上的电路。多个凸块形成在半导体管芯274-276的接触焊盘上。在一个实施例中，半导体管芯半导体管芯274-276是倒装芯片型半导体管芯。
穿过图4a-4b中的通常处于晶片级的半导体管芯124形成多个导电通孔278，用于z方向垂直互连。同样地，穿过半导体管芯274形成多个导电通孔280，用于z方向垂直互连。半导体管芯274被安装到半导体管芯124，其中将凸块282用冶金的方法并且电性地连接到导电通孔278。半导体管芯276被安装到半导体管芯274，其中将凸块284用冶金的方法并且电性地连接到导电通孔280。在一个实施例中，TSV半导体管芯142是逻辑器件或DSP，并且半导体管芯124和274-276为存储器件。密封剂286沉积在半导体管芯124、274和276之上以及周围。
图10示出了类似于图6的Fo-WLCSP 290的实施例，其中穿过密封剂170形成导电通孔292，用于到装配互连结构194的垂直电互连。利用激光钻孔、机械钻孔、刻蚀、或DRIE形成穿过密封剂170的多个通孔。利用电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶硅、或其它合适的导电材料填充所述通孔以形成z方向垂直互连导电通孔292。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (25)

1.一种制造半导体器件的方法，包括：
提供具有第一和第二相对表面的半导体晶片；
形成部分地穿过半导体晶片的第一表面的多个导电通孔；
将半导体晶片单体化为多个第一半导体管芯；
提供载体；
安装所述第一半导体管芯到所述载体；
安装第二半导体管芯到所述第一半导体管芯；
在第一和第二半导体管芯以及载体上沉积密封剂；
去除所述载体以及第二表面的一部分以暴露导电通孔；以及
在第一半导体管芯的与所述第二半导体管芯相对的表面上形成互连结构。
2.根据权利要求1所述的方法，其中，第二半导体管芯的占位面积比第一半导体管芯的占位面积大。
3.根据权利要求1所述的方法，进一步包括：
在安装所述第二半导体管芯之前，在所述衬底的所述第一表面上形成导电层，所述导电层电连接到所述导电通孔；并且
在所述衬底的所述第一表面上形成绝缘层。
4.根据权利要求1所述的方法，进一步包括，在所述第一和第二半导体管芯之间沉积模塑底部填充材料。
5.根据权利要求1所述的方法，其中，所述第二半导体管芯包括存储器件。
6.根据权利要求1所述的方法，进一步包括，在所述第一半导体管芯上堆叠多个第二半导体管芯。
7.一种制造半导体器件的方法，包括：
提供多个第一半导体管芯；
形成穿过所述第一半导体管芯的多个导电通孔；
提供载体；
安装所述第一半导体管芯到所述载体；
安装第二半导体管芯到所述第一半导体管芯，其中第二半导体管芯的占位面积大于第一半导体管芯的占位面积；以及
在第一和第二半导体管芯以及载体上沉积密封剂。
8.根据权利要求7所述的方法，进一步包括：
去除所述载体；以及
与所述第二半导体管芯相对地在第一半导体管芯上形成互连结构。
9.根据权利要求7所述的方法，进一步包括：
形成部分地穿过所述第一半导体管芯的第一表面的所述多个导电通孔；
去除所述载体；以及
去除与所述第一半导体管芯的所述第一表面相对的所述第一半导体的第二表面的一部分，以暴露导电通孔。
10.根据权利要求7所述的方法，进一步包括：
在安装所述第二半导体管芯之前，在所述第一半导体管芯上形成导电层，所述导电层电连接到所述导电通孔；并且
在所述第一半导体管芯上形成绝缘层。
11.根据权利要求7所述的方法，进一步包括；在所述第一和第二半导体管芯之间沉积模塑底部填充材料。
12.根据权利要求7所述的方法，进一步包括，在所述第一半导体管芯上堆叠多个第二半导体管芯。
13.根据权利要求7所述的方法，进一步包括，形成穿过密封剂的多个导电通孔。
14.一种制造半导体器件的方法，包括：
提供多个第一半导体管芯；
形成穿过所述第一半导体管芯的多个导电通孔；
提供载体；
安装所述第一半导体管芯到所述载体；
在第一半导体管芯和载体上沉积第一密封剂；
去除所述载体；
安装第二半导体管芯到第一半导体管芯；以及
在第二半导体管芯上沉积第二密封剂
15.根据权利要求14所述的方法，其中，第二半导体管芯的占位面积比第一半导体管芯的占位面积大。
16.根据权利要求14所述的方法，其中，所述第二半导体管芯包括存储器件。
17.根据权利要求14所述的方法，进一步包括，与所述第二半导体管芯相对地在第一半导体管芯上形成互连结构。
18.根据权利要求14所述的方法，进一步包括：
形成部分地穿过所述第一半导体管芯的第一表面的所述多个导电通孔；以及
去除与所述第一半导体管芯的所述第一表面相对的所述第一半导体的第二表面的一部分，以暴露导电通孔。
19.根据权利要求14所述的方法，进一步包括，去除所述第一密封剂的一部分以暴露导电通孔。
20.根据权利要求14所述的方法，进一步包括，在所述第一和第二半导体管芯之间沉积模塑底部填充材料。
21.一种半导体器件，包括：
第一半导体管芯，其具有穿过所述第一半导体管芯形成的多个导电通孔；
安装到所述第一半导体管芯的第二半导体管芯，其中，第二半导体管芯的占位面积比第一半导体管芯的占位面积大；
沉积在所述第一和第二半导体管芯上的密封剂；和
与第二半导体管芯相对地形成在第一半导体管芯上的互连结构。
22.根据权利要求21所述的半导体器件，其中，所述第二半导体管芯包括存储器件。
23.根据权利要求21所述的半导体器件，进一步包括在所述第一和第二半导体管芯之间沉积的模塑底部填充材料。
24.根据权利要求21所述的半导体器件，进一步包括形成于所述第一半导体管芯上并电连接到所述导电通孔的导电层；以及
形成于第一半导体管芯上的绝缘层。
25.根据权利要求21所述的半导体器件，进一步包括叠置于所述第一半导体管芯上的多个第二半导体管芯。
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