CN102420180B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN102420180B
CN102420180B CN201110285507.2A CN201110285507A CN102420180B CN 102420180 B CN102420180 B CN 102420180B CN 201110285507 A CN201110285507 A CN 201110285507A CN 102420180 B CN102420180 B CN 102420180B
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semiconductor element
substrate
conductive
semiconductor
layer
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CN102420180A (zh
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具俊谟
P.C.马里穆图
J.H.库
S.W.雍
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及半导体器件及其制造方法。一种半导体器件包括具有第一和第二相对表面的衬底。多个导电通孔被形成为部分地穿过衬底的第一表面。第一导电层形成在衬底的第一表面上，并电连接到导电通孔。第一半导体管芯被安装到衬底的第一表面上。第一半导体管芯和衬底被安装到载体。密封剂被沉积在第一半导体管芯、衬底和载体上。衬底的第二表面的一部分被除去以暴露导电通孔。互连结构被形成在衬底的第二表面上，与第一半导体管芯相对。第二半导体管芯可以被堆叠在第一半导体管芯上。第二半导体管芯可以被安装到衬底的第一表面上，与第一半导体管芯相邻。

Description

半导体器件及其制造方法
要求国内优先权
本申请要求2010年9月24日提交的临时申请No. 61/386,423的优先权，并且根据35 U.S.C. § 120要求上述申请的优先权。
技术领域
本发明总体上涉及半导体器件，并且更具体地说涉及半导体器件以及形成TSV插入机构（interposer）的方法，其中半导体管芯和装配互连结构位于该插入机构的相对表面上。
背景技术
在现代电子产品中通常会发现有半导体器件。半导体器件在电部件的数量和密度上有变化。分立的半导体器件一般包括一种电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包括数百到数百万的电部件。集成半导体器件的实例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池、以及数字微镜器件（DMD）。
半导体器件执行多种功能，例如信号处理、高速计算、发射和接收电磁信号、控制电子器件、将日光转换成电、以及为电视显示器生成可视投影。在娱乐、通信、功率转换、网络、计算机、以及消费品领域中有半导体器件的存在。在军事应用、航空、汽车、工业控制器、以及办公设备中也有半导体器件的存在。
半导体器件利用半导体材料的电特性。半导体材料的原子结构允许通过施加电场或基极电流（base current）或者通过掺杂工艺来操纵（manipulated）它的导电性。掺杂把杂质引入半导体材料中以操纵和控制半导体器件的导电性。
半导体器件包括有源和无源电结构。有源结构（包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平并且施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（包括电阻器、电容器、和电感器）产生执行多种电功能所必需的电压和电流之间的关系。无源和有源结构被电连接以形成电路，所述电路能够使半导体器件执行高速计算和其它有用的功能。
通常利用两个复杂的制造工艺来制造半导体器件，即前端制造和后端制造，每个可能包括数百个步骤。前端制造包括在半导体晶片的表面上形成多个管芯。每个半导体管芯通常相同并且包括通过电连接有源和无源部件形成的电路。后端制造包括从已完成的晶片单体化（singulating）单个半导体管芯并且封装管芯以提供结构支撑和环境隔离。在此使用的术语“半导体管芯”不仅指词的单数形式而且指词的复数形式，并且因此不仅可以指单个半导体器件而且可以指多个半导体器件。
半导体制造的一个目标是制造更小的半导体器件。更小的半导体器件通常消耗更少功率、具有更高的性能、并且能够被更有效地制造。另外，更小的半导体器件具有更小的占位空间（footprint），其对于更小的最终产品而言是期望的。通过改善导致产生具有更小、更高密度的有源和无源部件的半导体管芯的前端工艺可以实现更小的半导体管芯尺寸。通过改善电互连和封装材料，后端工艺可以产生具有更小占位空间的半导体器件封装。
在扇出型晶片级芯片规模封装（Fo-WLCSP）中，半导体管芯通常被密封剂包住。在半导体管芯和密封剂上形成底部装配互连结构用于电互连。半导体管芯、密封剂、和装配互连结构通常均具有不同的热膨胀系数（CTE）。半导体管芯、密封剂、和装配互连结构之间的不同CTE在密封期间以及之后引起热应力并且导致翘曲。另外，在半导体管芯和装配互连结构之间的电互连限制互连间距并且减少输入/输出（I/O）数。
发明内容
存在减小半导体管芯、密封剂、和装配互连结构之间的热应力、以及减小互连间距和增加I/O数的需要。因此，在一个实施例中，本发明是一种制作半导体器件的方法，所述方法包括以下步骤：提供具有第一和第二相对表面的衬底，形成多个部分地穿过衬底的第一表面的导电通孔，在衬底的第一表面上形成电连接到导电通孔的第一导电层，在衬底的第一表面上安装电连接到第一导电层的第一半导体管芯，提供载体，将第一半导体管芯和衬底安装到载体，在第一半导体管芯、衬底、和载体上沉积密封剂，除去衬底的第二表面的一部分以暴露导电通孔，以及在衬底的表面上形成与第一半导体管芯相对的互连结构。
在另一个实施例中，本发明是一种制作半导体器件的方法，所述方法包括以下步骤：提供具有第一和第二相对表面的衬底，在衬底内形成多个导电通孔，在衬底的第一表面上安装第一半导体管芯，提供载体，将第一半导体管芯和衬底安装到载体，在第一半导体管芯、衬底、和载体上沉积密封剂，以及在衬底的第二表面上形成与第一半导体管芯相对的互连结构。
在另一个实施例中，本发明是一种制作半导体器件的方法，所述方法包括以下步骤：提供衬底，在衬底内形成多个导电通孔，在衬底的第一表面上安装第一半导体管芯，在第一半导体管芯和衬底上沉积密封剂，以及在衬底的第二表面上形成与第一半导体管芯相对的互连结构。
在另一个实施例中，本发明是一种半导体器件，所述半导体器件包括衬底和形成在衬底内的多个导电通孔。第一半导体管芯安装在衬底的第一表面上。密封剂沉积在第一半导体管芯和衬底上。互连结构形成在衬底的第二表面上，与第一半导体管芯相对。
附图说明
图1示出具有安装到其表面的不同类型封装的印刷电路板（PCB）；
图2a-2c示出安装到PCB的典型半导体封装的更多细节；
图3a-3c示出具有被划片街区（saw street）分开的多个半导体管芯的半导体晶片；
图4a-4o示出形成TSV插入机构的过程，其中半导体管芯和装配互连结构位于该插入机构的相对表面上；
图5示出eWLB，其中半导体管芯和装配互连结构位于TSV插入机构的相对表面上；
图6示出比TSV插入机构具有更大占位空间的半导体管芯；
图7示出安装到TSV插入机构的两个堆叠半导体管芯，其中上面的管芯比TSV插入机构具有更大的占位空间；
图8示出安装到TSV插入机构的四个堆叠半导体管芯，其中上面的管芯比TSV插入机构具有更大的占位空间；
图9示出安装到TSV插入机构的三个堆叠半导体管芯，其中密封剂向下延伸到插入机构；
图10示出安装到TSV插入机构的三个堆叠半导体管芯，其中密封剂沿插入机构的侧表面向下延伸；
图11示出并排安装到TSV插入机构的两个半导体管芯；
图12示出安装到TSV插入机构的三个堆叠半导体管芯和一个并排半导体管芯；以及
图13a-13b示出半导体管芯安装到TSV插入机构的PoP布置。
具体实施方式
参考附图在下列描述中的一个或多个实施例中描述本发明，在附图中相似的数字表示相同或类似的元件。虽然根据用来实现本发明的目的的最佳方式描述本发明，但是本领域技术人员将理解的是，它旨在覆盖可以被包含在由被下列公开和各图所支持的所附权利要求及其等效物限定的本发明的精神和范围内的替代物、变型、和等效物。
一般利用两个复杂的制造工艺制造半导体器件：前端制造和后端制造。前端制造包括在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包括有源和无源电部件，所述有源和无源电部件被电连接以形成功能电路。有源电部件，例如晶体管和二极管，具有控制电流的流动的能力。无源电部件，例如电容器、电感器、电阻器、和变压器，产生执行电路功能所必需的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、刻蚀、和平面化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过例如离子注入或热扩散的技术将杂质引入到半导体材料中。所述掺杂工艺改变有源器件中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流动态改变半导体材料导电性。晶体管包括有变化的掺杂类型和程度的区域，所述区域根据需要被设置为使晶体管能够在施加电场或基极电流时促进或限制电流的流动。
通过具有不同电特性的材料的层形成有源和无源部件。所述层可以通过部分地由被沉积的材料的类型决定的多种沉积技术形成。例如，薄膜沉积可以包括化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀、以及无电极电镀（electroless plating）工艺。每个层通常被图案化以形成有源部件、无源部件、或部件之间的电连接的各部分。
可以利用光刻图案化所述层，所述光刻包括在将被图案化的层上沉积光敏材料，例如光致抗蚀剂。利用光将图案从光掩模转移到光致抗蚀剂。在一个实施例中，利用溶剂将经受光的光致抗蚀剂图案部分除去，暴露将被图案化的下层的各部分。在另一个实施例中，利用溶剂将未经受光的光致抗蚀剂（负性光致抗蚀剂）图案部分除去，暴露将被图案化的下层的各部分。光致抗蚀剂的剩余物被除去，留下被图案化的层。可替换地，利用例如无电极电镀或电解电镀的技术通过直接将材料沉积到通过先前的沉积/刻蚀工艺形成的区域或空隙中来图案化一些类型的材料。
在现有图案上沉积材料的薄膜可能会放大下面的图案并且引起不均匀的平面。需要均匀的平面来制造更小和更密集包装的有源和无源部件。可以利用平面化从晶片的表面除去材料和制造均匀平面。平面化包括利用抛光垫抛光晶片的表面。在抛光期间，磨料和腐蚀性化学品被添加到晶片的表面。组合的磨料机械作用和化学品腐蚀作用除去了任何不规则的表面形貌（topography），产生均匀的平面。
后端制造指的是将已完成的晶片切割或单体化成单个管芯，并且然后封装管芯用于结构支撑和环境隔离。为单体化半导体管芯，沿被叫做划片街区或划线的晶片非功能区域刻划和断开所述晶片。利用激光切割工具或锯条来单体化晶片。在单体化之后，单个半导体管芯被安装到封装衬底，所述封装衬底包括用来与其它系统部件互连的引脚或接触焊盘。形成在半导体管芯上的接触焊盘然后被连接到封装内的接触焊盘。可以利用焊料凸块、柱形凸块（stud bump）、导电胶、或线结合（wirebond）来制作电连接。密封剂或其它成型材料被沉积到封装上以提供物理支撑和电隔离。已完成的封装然后被插入电系统中并且半导体器件的功能可以用到其它系统部件。
图1示出具有芯片载体衬底或印刷电路板（PCB）52的电子器件50，所述芯片载体衬底或印刷电路板（PCB）52具有多个安装在它的表面上的半导体封装。电子器件50可以具有一种半导体封装、或多种半导体封装，这取决于应用。为了说明的目的，在图1中示出不同类型的半导体封装。
电子器件50可以是利用半导体封装来执行一个或多个电功能的独立系统。可替换地，电子器件50可以是更大系统的子部件。例如，电子器件50可以是蜂窝式电话、个人数字助理（PDA）、数码摄像机（DVC）或其它电子通信装置的一部分。可替换地，电子器件50可以是能被插入计算机中的图形卡、网络接口卡、或其它信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件、或其它半导体管芯或电部件。对于将被市场接受的这些产品而言，小型化和减轻重量是必需的。半导体器件之间的距离必须被减小以实现更高的密度。
在图1中，PCB 52提供普通的衬底用于安装在PCB上的半导体封装的结构支撑和电互连。利用蒸发、电解电镀、无电极电镀、丝网印刷、或其它合适的金属沉积工艺将导电信号迹线（trace）54形成在PCB 52的表面上或各层内。信号迹线54提供半导体封装、安装的部件、以及其它外部系统部件中的每一个之间的电通信。迹线54也将电源和地连接提供给半导体封装中的每一个。
在一些实施例中，半导体器件可以具有两个封装级。第一级封装是用来将半导体管芯以机械和电的方式附着到中间载体的技术。第二级封装包括将所述中间载体以机械和电的方式附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中管芯被以机械和电的方式直接安装到PCB。
为了说明的目的，几种第一级封装，包括接合线封装56和倒装芯片58，被示出在PCB 52上。另外，几种第二级封装，包括球栅阵列（BGA）60、凸块芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（land grid array，LGA）66、多芯片模块（MCM）68、四侧无引脚扁平封装（quad flat non-leaded package，QFN）70、以及四侧扁平封装72被示出安装在PCB 52上。根据系统要求，利用第一和第二级封装形式的任何组合配置的半导体封装的任何组合、以及其它电子部件，可以被连接到PCB 52。在一些实施例中，电子器件50包括单个附着的半导体封装，虽然其它实施例要求多互连封装。通过在单个衬底上组合一个或多个半导体封装，制造商可以将预先制作的部件并入电子器件和系统中。因为所述半导体封装包括复杂功能，所以可以利用更便宜的部件和流水线制造工艺来制造电子器件。所得到的器件较少可能失效并且制造起来花费较少，对用户而言导致更低的成本。
图2a-2c示出示范性半导体封装。图2a示出安装在PCB 52上的DIP 64的更多细节。半导体管芯74包括包含模拟或数字电路的有源区，所述模拟或数字电路被实现为根据管芯的电设计形成在管芯内并且被电互连的有源器件、无源器件、导电层、和介电层。例如，电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及形成在半导体管芯74的有源区内的其它电路元件。接触焊盘76是一层或多层的导电材料，例如铝（AL）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、或银（Ag），并且电连接到形成在半导体管芯74内的电路元件。在DIP64的组装期间，利用金硅共晶层或粘附材料（例如热的环氧或环氧树脂）将半导体管芯74安装到中间载体78。封装体包括绝缘封装材料，例如聚合物或陶瓷。导体引线80和接合线82在半导体管芯74和PCB 52之间提供电互连。密封剂84被沉积在封装上用于通过防止湿气与粒子进入所述封装以及污染半导体管芯74或接合线82来进行环境保护。
图2b示出安装在PCB 52上的BCC 62的更多细节。半导体管芯88利用底层填充材料或环氧树脂粘附材料92被安装到载体90上。接合线94在接触焊盘96和98之间提供第一级封装互连。模塑料或密封剂100被沉积在半导体管芯88和接合线94上以为所述器件提供物理支撑和电隔离。接触焊盘102利用电解电镀或无电极电镀这样合适的金属沉积形成在PCB52的表面上以防止氧化。接触焊盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸块104被形成在BCC 62的接触焊盘98与PCB 52的接触焊盘102之间。
在图2c中，利用倒装芯片型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区108包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计形成的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、电感器、电容器、电阻器、以及在有源区108内的其它电路元件。半导体管芯58通过凸块110被电连接和机械连接到载体106。
BGA 60 利用凸块112电连接和机械连接到具有BGA型第二级封装的PCB 52。半导体管芯58通过凸块110、信号线114、以及凸块112电连接到导电信号迹线54。模塑料或密封剂116被沉积在半导体管芯58和载体106上以为所述器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB 52上的导电轨迹的短导电路径以便减小信号传播距离、降低电容、并且改善总的电路性能。在另一个实施例中，半导体管芯58可以在没有中间载体106的情况下利用倒装芯片型第一级封装被以机械和电的方式直接连接到PCB 52。
图3a示出具有用于结构支撑的基底衬底材料122（例如硅、锗、砷化镓、磷化铟、或碳化硅）的半导体晶片120。多个半导体管芯或部件124形成在晶片120上，被管芯间的晶片区域或划片街区126分开，如上所述。划片街区126提供切割区域以将半导体晶片120单体化成单个半导体管芯124。
图3b示出半导体晶片120的一部分的截面图。每个半导体管芯124具有后表面128和有源表面130，所述有源表面130包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面130内的其它电路元件以实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器、或其它信号处理电路。半导体管芯124也可以包括集成无源器件（IPD），例如电感器、电容器、和电阻器，用于RF信号处理。在一个实施例中，半导体管芯124是倒装芯片型半导体管芯。
利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在有源表面130上形成导电层132。导电层132可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层132用作电连接到有源表面130上的电路的接触焊盘。可以离半导体管芯124的边缘第一距离并排设置接触焊盘132，如图3b中所示。可替换地，接触焊盘132可以多行偏移使得第一行接触焊盘被设置得离管芯的边缘为第一距离，并且与第一行交替的第二行接触焊盘被设置得离管芯的边缘为第二距离。
在图3c中，利用锯条或激光切割工具134，通过划片街区126，半导体晶片120被单体化成单个半导体管芯124。
相对于图1和图2a-2c，图4a-4o示出形成TSV插入机构的过程，其中半导体管芯和装配互连结构位于该插入机构的相对表面上。图4a示出包含用于结构支撑的基底材料（例如硅、锗、砷化镓、磷化铟、或碳化硅）的半导体晶片或衬底140。可替换地，衬底140可以是聚合物、氧化铍、或用于结构支撑的其它合适的低成本、刚性材料。。衬底140具有相对的表面142和144。
在图4b中，利用机械钻孔、激光钻孔、或深反应离子刻蚀（DRIE）形成部分地穿过衬底140的多个盲孔146。通孔146从表面142延伸，部分地但不完全地穿过衬底140。在一个实施例中，通孔146贯通衬底140的厚度的60％。在通孔146和后表面144之间的衬底140的剩余部分在随后的制造工艺期间为衬底提供结构支撑。
在图4c中，利用电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺，利用Al、Cu、Sn、Ni、Au、Ag、钛（Ti）、钨（W）、多晶硅、或其它合适的导电材料填充通孔146以形成z方向导电通孔148。
在图4d中，利用PVD、CVD、电解电镀、无电极电镀工艺、或其它合适的金属沉积工艺在衬底140的表面142上形成导电层150。导电层150可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层150充当用于电互连的接触焊盘或凸块下金属化（UBM）层。导电层150也包括用于通过衬底140水平和垂直地路由电信号的再分配层（RDL）和z方向导电通孔。导电层150的一部分电连接到导电通孔148。导电层150的其它部分可以根据半导体管芯124的设计和功能是电共有的（electrically common）或被电隔离。
利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在衬底140的表面142上以及导电层150的周围形成绝缘或钝化层152。绝缘层152包括一层或多层的二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、或具有类似绝缘和结构特性的其它材料。通过光致抗蚀剂层（未示出）借助刻蚀工艺除去绝缘层152的一部分以暴露导电层150。
在图4e中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺在导电层150的暴露部分上沉积导电凸块材料。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层150。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块154。在一些应用中，凸块154被二次回流以改善到导电层150的电接触。凸块154也可以被压缩结合到导电层150。凸块154表示一种可以形成在导电层150上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
衬底140、导电通孔148、导电层150、绝缘层152、和凸块154的组合构成直通硅通孔（TSV）插入机构156。
在图4f中，利用拾取和放置操作将图3a-3c的半导体管芯124安装到插入机构156，其中有源表面130面向插入机构。凸块154被回流以将插入机构156的导电层150电连接到半导体管芯124的导电层132。图4g示出用冶金的方法并且电性地连接到插入机构156的半导体管芯124。在半导体管芯124下面沉积可选的底部填充材料157。
在图4h中，利用锯条或激光切割工具158将插入机构156单体化成单个管芯/插入机构组件160，每个管芯/插入机构组件包括一个半导体管芯124和部分插入机构156。
在图4i中，临时衬底或载体162包括用于结构支撑的牺牲基底材料，例如硅、聚合物、氧化铍、或其它合适的低成本、刚性材料。界面层或双面胶带163形成在载体162上作为临时粘附结合膜或刻蚀停层。利用拾取和放置操作将管芯/插入机构组件160放置在界面层163和载体162上并且安装到界面层163和载体162，其中半导体管芯124取向远离载体。图4j示出安装到界面层163和载体162的管芯/插入机构组件160。安装到载体162的管芯/插入机构组件160构成了重新配置的晶片。
在图4k中，利用浆料印刷（paste printing）、压缩模塑、传递模塑、液体密封剂模塑、真空层压、旋涂、或其它合适的施加器（applicator）在管芯/插入机构组件160和载体162上以及周围晶片级地沉积密封剂或模塑料164。密封剂164可以是聚合物复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有合适填充物的聚合物。密封剂164不导电并且在环境上保护半导体器件免受外部元件和污染物的影响。
在图4l中，通过研磨器166除去衬底140的基底材料的一部分以暴露导电通孔148。图4m示出在研磨操作后被密封剂164覆盖的管芯/插入机构组件160，其中导电通孔148从衬底140暴露。
在图4n中，装配互连结构168与半导体管芯124相对地形成在插入机构156的表面上。装配互连结构168包括利用图案化和金属沉积工艺（例如溅射、电解电镀、和无电极电镀）形成的导电层或RDL 170。导电层170可以是一层或多层的Al、Cu、Sn、Ni、Au、Ag、或其它合适的导电材料。导电层170包括用于电互连的水平和垂直部分。导电层170的一部分电连接到导电通孔148。导电层170的其它部分可以根据半导体管芯124的设计和功能是电共有的或被电隔离。
利用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在导电层周围和之间形成绝缘或钝化层172用于电隔离。绝缘层170包括一层或多层的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或具有类似绝缘和结构特性的其它材料。可以通过光致抗蚀剂层借助刻蚀工艺除去绝缘层170的一部分以暴露导电层170，用于凸块形成或另外的封装互连。装配互连结构168借助导电通孔148电连接到导电层150、凸块154、和半导体管芯124。
在图4o中，使用蒸发、电解电镀、无电极电镀、球滴或丝网印刷工艺，导电凸块材料被沉积在装配互连结构168上并且电连接到导电层170的暴露部分。凸块材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料，及其组合，带有可选的焊剂溶液。例如，凸块材料可以是共晶Sn/Pb、高铅焊料、或无铅焊料。利用合适的附着或结合工艺将凸块材料结合到导电层170。在一个实施例中，通过将凸块材料加热到它的熔点以上，所述凸块材料回流以形成球或凸块174。在一些应用中，凸块174被二次回流以改善到导电层170的电接触。UBM层可以形成在凸块174下面。凸块174也可以被压缩结合到导电层170。凸块174表示一种可以形成在导电层170上的互连结构。所述互连结构也可以使用柱形凸块、微凸块、或其它电互连。
利用锯条或激光切割工具176，穿过密封剂164和装配互连结构168，半导体管芯124被单体化成单个Fo-WLCSP或嵌入式晶片级球栅阵列（eWLB）178。图5示出单体化之后的eWLB 178。半导体管芯124通过凸块154、导电层150、和导电通孔148电连接到装配互连结构168。具有导电通孔148、导电层150、绝缘层152、和凸块154的插入机构156为半导体管芯124的垂直互连提供简单和节省成本的结构，以及穿过插入机构的导电层和装配互连结构168提供有效的封装堆叠。由于插入机构156可以利用与半导体管芯124类似的材料制作，并且装配互连结构168与半导体管芯和密封剂164相对地形成在插入机构的表面上，因此插入机构消除了半导体管芯和装配互连结构之间的CTE失配。插入机构156充当在插入机构一侧上的半导体管芯124与在插入机构的相对侧上的装配互连结构168之间的缓冲器以减小翘曲。插入机构156为半导体管芯124提供适合于高I/O数应用的细间距垂直互连。
图6示出类似于图5的eWLB 180的实施例，其中半导体管芯124具有比插入机构156更大的占位空间。半导体管芯124在插入机构156的外部尺寸上延伸。密封剂164向下延伸到插入机构156的侧表面。
图7示出类似于图5的eWLB 182的实施例，其中半导体管芯184被安装到半导体管芯124。半导体管芯184来源于类似于图3a-3c的半导体晶片，并且具有比半导体管芯124和插入机构156更大的占位空间。半导体管芯184具有后表面188和有源表面190，所述有源表面190包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面190内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯184也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘192形成在有源表面190上并且电连接到有源表面上的电路。多个凸块194形成在接触焊盘192上。在一个实施例中，半导体管芯184是倒装芯片型半导体管芯。
穿过图3a-3b中的通常处于晶片级的半导体管芯124形成多个导电通孔196，用于z方向垂直互连。半导体管芯184被安装到半导体管芯124，其中将凸块194用冶金的方法并且电性地连接到导电通孔196。在一个实施例中，半导体管芯124是逻辑器件或DSP，并且半导体管芯184是存储器件。半导体管芯184在半导体管芯124和插入机构156的外部尺寸上延伸。密封剂164向下延伸到插入机构156的侧表面。
图8示出类似于图5的eWLB 200的实施例，其中半导体管芯202、204、和206堆叠在半导体管芯124上。半导体管芯202-206来源于类似于图3a-3c的半导体晶片，并且具有比半导体管芯124和插入机构156更大的占位空间。每个半导体管芯202-206具有后表面和有源表面，所述有源表面包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯202-206也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘形成在有源表面上并且电连接到有源表面上的电路。多个凸块形成在用于半导体管芯202-206的接触焊盘上。在一个实施例中，半导体管芯202-206是倒装芯片型半导体管芯。
穿过图3a-3b中的通常处于晶片级的半导体管芯124形成多个导电通孔208，用于z方向垂直互连。类似地，穿过半导体管芯202形成多个导电通孔210，并且穿过半导体管芯204形成多个导电通孔212，用于z方向垂直互连。半导体管芯202被安装到半导体管芯124，其中将凸块214用冶金的方法并且电性地连接到导电通孔208。半导体管芯204被安装到半导体管芯202，其中将凸块216用冶金的方法并且电性地连接到导电通孔210。半导体管芯206被安装到半导体管芯204，其中将凸块218用冶金的方法并且电性地连接到导电通孔212。在一个实施例中，半导体管芯124是逻辑器件或DSP，并且半导体管芯202-206是存储器件。半导体管芯202-206在半导体管芯124和插入机构156的外部尺寸上延伸。密封剂164向下延伸到插入机构156的侧表面。
图9示出类似于图5的eWLB 220的实施例，其中半导体管芯222和224堆叠在半导体管芯124上。半导体管芯222和224来源于类似于图3a-3c的半导体晶片。每个半导体管芯222-224具有后表面和有源表面，所述有源表面包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯222-224也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘形成在有源表面上并且电连接到有源表面上的电路。多个凸块形成在用于半导体管芯222-224的接触焊盘上。在一个实施例中，半导体管芯222-224是倒装芯片型半导体管芯。
穿过图3a-3b中的通常处于晶片级的半导体管芯124形成多个导电通孔228，用于z方向垂直互连。类似地，穿过半导体管芯222形成多个导电通孔230，用于z方向垂直互连。半导体管芯222被安装到半导体管芯124，其中将凸块232用冶金的方法并且电性地连接到导电通孔228。半导体管芯224被安装到半导体管芯222，其中将凸块234用冶金的方法并且电性地连接到导电通孔230。在一个实施例中，半导体管芯124是逻辑器件或DSP，并且半导体管芯222-224是存储器件。在该实施例中，密封剂164向下延伸到插入机构156的侧表面。
图10示出类似于图5的eWLB 240的实施例，其中半导体管芯242和244堆叠在半导体管芯124上。半导体管芯242和244来源于类似于图3a-3c的半导体晶片。每个半导体管芯242-244具有后表面和有源表面，所述有源表面包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯242-244也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘形成在有源表面上并且电连接到有源表面上的电路。多个凸块形成在用于半导体管芯242-244的接触焊盘上。在一个实施例中，半导体管芯242-244是倒装芯片型半导体管芯。
穿过图3a-3b中的通常处于晶片级的半导体管芯124形成多个导电通孔248，用于z方向垂直互连。类似地，穿过半导体管芯242形成多个导电通孔250，用于z方向垂直互连。半导体管芯242被安装到半导体管芯124，其中将凸块252用冶金的方法并且电性地连接到导电通孔248。半导体管芯244被安装到半导体管芯242，其中将凸块254用冶金的方法并且电性地连接到导电通孔250。在一个实施例中，半导体管芯124是逻辑器件或DSP，并且半导体管芯242-244是存储器件。在该实施例中，插入机构156的一侧从eWLB 240暴露。
图11示出类似于图5的eWLB 260的实施例，其中半导体管芯262和264被并排安装到插入机构156。半导体管芯262和264来源于类似于图3a-3c的半导体晶片。每个半导体管芯262-264具有后表面和有源表面，所述有源表面包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯262-264也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘266形成在半导体管芯262的有源表面上并且电连接到有源表面上的电路。多个接触焊盘268形成在半导体管芯264的有源表面上并且电连接到有源表面上的电路。在一个实施例中，半导体管芯262-264是倒装芯片型半导体管芯。
半导体管芯262被安装到插入机构156，其中将接触焊盘266用冶金的方法并且电性地连接到凸块154。半导体管芯264被安装到插入机构156，邻近半导体管芯262，其中将接触焊盘268用冶金的方法并且电性地连接到凸块154。密封剂164向下延伸到插入机构156的侧表面。
图12示出类似于图5的eWLB 270的实施例，其中半导体管芯272、274和276堆叠在插入机构156上。另外，半导体管芯278相对于半导体管芯272并排安装在插入机构156上，并且分立的半导体器件280被安装到插入机构156的导电层150。分立的半导体器件280可以是有源器件（例如晶体管或二极管）或无源器件（例如电感器、电容器、或电阻器）。
半导体管芯272-278来源于类似于图3a-3c的半导体晶片。每个半导体管芯272-278具有后表面和有源表面，所述有源表面包含模拟或数字电路，所述模拟或数字电路被实现为根据管芯的电设计和功能形成在管芯内并且电互连的有源器件、无源器件、导电层、和介电层。例如，该电路可以包括一个或多个晶体管、二极管、和形成在有源表面内的其它电路元件以实现模拟电路或数字电路，例如DSP、ASIC、存储器、或其它信号处理电路。半导体管芯272-278也可以包括IPD，例如电感器、电容器、和电阻器，用于RF信号处理。多个接触焊盘形成在有源表面上并且电连接到有源表面上的电路。多个凸块形成在用于半导体管芯274和276的接触焊盘上。在一个实施例中，半导体管芯272-278是倒装芯片型半导体管芯。
穿过通常处于晶片级的半导体管芯272形成多个导电通孔282，用于z方向垂直互连。类似地，穿过半导体管芯274形成多个导电通孔284，用于z方向垂直互连。半导体管芯272被安装到插入机构156，其中将接触焊盘286用冶金的方法并且电性地连接到凸块154。半导体管芯274被安装到半导体管芯272，其中将凸块288用冶金的方法并且电性地连接到导电通孔282。半导体管芯276被安装到半导体管芯274，其中将凸块290用冶金的方法并且电性地连接到导电通孔284。半导体管芯278被安装到插入机构156，其中将接触焊盘292用冶金的方法并且电性地连接到凸块154。在一个实施例中，半导体管芯272和278是逻辑器件或DSP，并且半导体管芯274-276是存储器件。
图13a-13b示出层叠封装（PoP）布置300的实施例，其中图5的eWLB 178堆叠在图7的eWLB 182上。在图13a中，eWLB 178位于eWLB 182上。穿过eWLB 182的密封剂164形成多个导电通孔302。图13b示出被安装到eWLB 182的eWLB 178，其中将eWLB 178的凸块174用冶金的方法并且电性地连接到导电通孔302。
虽然已经详细说明本发明的一个或多个实施例，但是本领域技术人员将理解的是，在不脱离由下列权利要求所阐述的本发明的范围的情况下可以对那些实施例进行变型和修改。

Claims (8)

1.一种制作半导体器件的方法，包括：
提供包括相对的第一表面和第二表面的衬底；
形成部分地穿过衬底的第一表面的多个通孔；
利用导电材料完全地填充所述多个通孔以形成多个导电通孔；
在所述衬底的第一表面上形成导电层，该导电层电连接到导电通孔；
在所述导电层周围设置第一绝缘层以完全覆盖所述导电层的侧表面；
在所述衬底的第一表面上设置第一半导体管芯，该第一半导体管芯电连接到所述导电层；
在所述第一半导体管芯和衬底上、包括在所述衬底的侧表面上沉积密封剂；
在将第一半导体管芯设置在衬底上之后，除去衬底的第二表面的一部分，以暴露与所述衬底的第二表面共面的导电通孔；
与第一半导体管芯相对地在所述衬底和密封剂上形成再分配层(RDL)，该再分配层电连接到所述第一半导体管芯；以及
穿过密封剂形成导电通孔，该导电通孔电连接到所述再分配层。
2.根据权利要求1所述的方法，还在所述衬底的第二表面上形成互连结构。
3.根据权利要求1所述的方法，还包括在第一半导体管芯上设置第二半导体管芯。
4.根据权利要求1所述的方法，还包括在所述衬底上设置分立的半导体器件。
5.一种半导体器件，包括：
衬底；
完全穿过所述衬底形成的多个导电通孔；
在所述衬底的第一表面上形成的导电层，该导电层电连接到所述导电通孔；
在所述导电层周围形成的第一绝缘层，该第一绝缘层完全覆盖所述导电层的侧表面；
设置在所述衬底的第一表面上的第一半导体管芯，该第一半导体管芯电连接到所述导电层；
在所述第一半导体管芯和衬底上、包括在所述衬底的侧表面上沉积的密封剂；
与第一半导体管芯相对地在所述衬底和密封剂上形成再分配层，该再分配层电连接到所述第一半导体管芯；和
穿过所述密封剂形成的导电通孔，该导电通孔电连接到所述再分配层。
6.根据权利要求5所述的半导体器件，还包括设置在所述衬底上的第二半导体管芯。
7.根据权利要求5所述的半导体器件，还包括包含设置在衬底上的存储器电路的第二半导体管芯。
8.根据权利要求5所述的半导体器件，还包括：
在与第一表面相对的衬底的第二表面上形成的互连结构。
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