TWI594380B - 封裝結構及三維封裝結構 - Google Patents
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Description
本發明係關於一種封裝結構及三維封裝結構,尤指一種可降低高頻損耗之封裝結構及三維封裝結構。
一般而言,高頻或超高頻行動通訊係指操作於數十GHz之無線通訊系統,而目前常見之封裝技術在數十GHz的頻帶下具有顯著的損耗。舉例來說,目前常見的封裝技術為表面黏著技術(Surface Mount Technology,SMT),採用SMT封裝技術的元件可大量的組裝製造成各類行動裝置。然而,習知以SMT封裝技術的元件之高頻特性不佳,當操作頻率高於6GHz時,元件內之損耗隨著操作頻率高而逐漸顯著,進而影響整體效能。
詳細來說,請參考第1圖,第1圖為習知一封裝結構10之剖面示意圖。封裝結構10包含一晶片100及接腳102,透過一打線接合(Wire Bonding)製程,將晶片100與接腳102之透過金屬線104相互接合,最後,透過一模封製程,形成一模封蓋106以包覆晶片100及金屬線104。需注意的是,金屬線104包覆於模封蓋106中,當操作頻率高於6GHz時,因金屬線104與模封蓋106相互接觸而產生寄生電感效應,且當操作頻率越高,寄生電感之電感值越大,造成高頻損耗增加,進而影響封裝結構10之效能。
因此,如何降低於高頻時所產生之損耗,就成了業界所努力的目標之一。
因此,本發明之主要目的之一在於提供一種封裝結構及三維封裝結構,其可降低於高頻時所產生之損耗。
本發明揭露一種封裝結構,包含有至少一接腳,用來傳遞至少一訊號;至少一走線層,連接於該至少一接腳,該至少一走線層中形成有至少一第一通孔;一晶片,設置於該至少一走線層之上,該晶片形成有至少一第二通孔,該晶片產生或接收該至少一訊號;以及一模封蓋,用來包覆該至少一走線層及該晶片;其中,該至少一第一通孔用來提供該晶片與該至少一接腳之間之走線。
本發明另揭露一種三維(3D)封裝結構,包含有至少一接腳,用來傳遞至少一訊號;至少一走線層,連接於該至少一接腳,該至少一走線層中形成有至少一第一通孔;複數個晶片,相互堆疊而設置於該至少一走線層之上,該複數個晶片中至少一晶片中各自形成有至少一第二通孔,該至少一晶片產生或接收該至少一訊號;以及一模封蓋,用來包覆該至少一走線層及該複數個晶片;其中,該至少一第一通孔及該至少一第二通孔用來提供該複數個晶片之間或該複數個晶片與該至少一走線層之間之走線。
請參考第2圖,第2圖為本發明實施例一封裝結構20之剖面示意圖。在此例中,封裝結構20為包含接腳202_1~202_N之一四方扁平無引腳封裝(Quad Flat No-lead Package,QFN),接腳202_1~202_N設置於封裝結構20之下方,為求簡潔,第2圖僅繪示接腳202_1~202_N中之二接腳202_a、202_b。如第2圖所示,封裝結構20包含有一晶片200、走線層208_1、208_2、接腳202_1~202_N及一模封蓋206,晶片200設置於走線層208a、208b之上,其可為未經封裝之一晶粒(Die,或稱裸晶),其用來實現一單晶微波積體電路(Monolithic Microwave Integrated Circuit,MMIC)之功能,換句話說,晶片200產生或接收複數個訊號。封裝結構20可透過接腳202_1~202_N以焊接的方式耦接於一外部電路板(未繪示於第2圖),接腳202_1~202_N分別用來傳遞複數個訊號至外部電路板。其中,訊號RF_a、RF_b為複數個訊號中具有高頻特性之訊號,在一實施例中,接腳202_a、202_b分別用來傳遞高頻訊號RF_a、RF_b至外部電路板。走線層208_1、208_2電性連接於接腳202_1~202_N並設置於晶片200與接腳202_1~202_N之間,用來提供晶片200與接腳202_1~202_N之間之走線。模封蓋206可為環氧樹脂(Molding Compound)或氣腔(Air-Cavity)封裝等模封材料所製成,而不在此限。模封蓋206用來包覆走線層208_1、208_2及晶片200,使得封裝結構20之外觀為四方扁平無引腳封裝。
詳細來說,晶片200可透過一熱導孔(Hot Via)製程形成有複數個通孔200_via,而走線層208_1、208_2亦可透過鑽孔的方式形成有複數個通孔208_via,晶片200的訊號,由晶片200之一正面(晶片200之正面與模封蓋206接觸),透過通孔200_via連接到晶片200之一背面(晶片200之背面與走線層208_1接觸),且電性連接於位於走線層之通孔208_via。換句話說,走線層208_1、208_2透過通孔208_via,利用如微帶線(Microstrip Line)等導電材質,以提供晶片200與接腳202_a、202_b之間之走線,如此一來,承上述實施例,訊號RF_a、RF_b即可透過通孔200_via及通孔208_via直接由接腳202_a、202_b傳遞至晶片200(或由晶片200傳遞至接腳202_a、202_b)。另外,走線層208_1、208_2可以一薄型印刷電路板(Laminate PCB)或一陶瓷材質所製成,或是可電性導通封裝結構20之一導電支架(Lead Frame,未繪示於第2圖)之介質,而未有所限。除此之外,藉由熱導孔製程,晶片200之一晶片接地部200_gnd可透過通孔鍊性連接於封裝結構20之一接地接腳202_gnd,使得封裝結構20及晶片200具有較佳的散熱特性。
需注意的是,高頻訊號RF_a、RF_b可透過通孔200_via、208_via或導電支架而電性連接於接腳202_a、202_b,藉此,本發明之通孔200_via、208_via可取代傳統利用打線接合(Wire Bonding)方式晶片之訊號傳遞至封裝結構之接腳,以避免不必要的電感效應。因此,封裝結構20於高頻(操作頻率高於6GHz)時,封裝結構20不會產生(或僅產生輕微的)寄生電感效應,因此可降低封裝結構20於高頻時所產生之損耗。請參考第3圖,第3圖為第1圖封裝結構10與第2圖之封裝結構20之穿透係數之頻率響應之示意圖,其中,虛線為封裝結構10之穿透係數之頻率響應,實線為封裝結構20之穿透係數之頻率響應。由第3圖可知,因習知封裝結構10之金屬線104與模封蓋106接觸而於高頻產生寄生電感效應,使得封裝結構10之穿透係數於操作頻率高於20GHz時急遽地衰減,及封裝結構10之損耗於操作頻率高於20GHz時急遽地惡化。相較之下,本發明即使在操作頻率高於20GHz的情況下,封裝結構20之損耗極小,衰減幅度僅小於1dB。
因此,本發明之封裝結構可大幅降低於高頻時所產生之損耗,除此之外,本發明之封裝結構可適用於表面黏著技術(Surface Mount Technology,SMT)之封裝,可經大量的組裝製造成各類行動裝置。另外,本發明使用熱導孔製程於晶片200中形成有通孔200_via,因此,相較於現行倒晶封裝技術(Flip Chip),晶片200之電路佈局不須配合倒晶封裝之接線而另外重新設計,而且本發明使用熱導孔製程,晶片200具有較佳的散熱特性。
前述實施例係用以說明本發明之概念,本領域具通常知識者當可據以做不同之修飾,而不限於此。舉例來說,於封裝結構20中,因晶片200之面積通常小於封裝結構20之面積,而在薄型印刷電路板上進行垂直鑽孔已為一成熟技術,故可利用經垂直鑽孔之二走線層208_1、208_2與經適當佈線之走線層208_2,將訊號RF_a、RF_b由接腳202_a、202_b傳遞至晶片200(或由晶片200傳遞至接腳202_a、202_b),然而,本發明之封裝結構不限於二走線層,亦可僅包含單一走線層。舉例來說,請參考第5圖,第5圖為本發明實施例一封裝結構50之剖面示意圖。封裝結構50與封裝結構20類似,與封裝結構20不同的是,封裝結構50僅包含一走線層508,且因封裝結構50所包含之一晶片500具有較晶片200寬大的面積,使得晶片500之一垂直投影結果與接腳502_a、502_b重疊,如此一來,走線層508可利用垂直鑽孔的方式形成通孔508_via,以建立晶片500與接腳502_a、502_b之間之走線。需注意的是,走線層中通孔的形式可視實際需求而變化,其可透過斜角鑽孔或曲線鑽孔的方式而形成,並不限於利用垂直鑽孔的方式形成通孔,換句話說,只要走線層形成有通孔以建立晶片與接腳之間之走線,即滿足本發明需求且屬於本發明之範疇。
另一方面,於前述實施例中,封裝結構20將高頻訊號RF_a、RF_b利用通孔傳遞於晶片200與接腳202_a、202_b之間,而不限於此。在此情形下,晶片所產生或接收之訊號皆可利用形成於晶片與走線層之通孔而傳遞於晶片與接腳之間;或者,若晶片所產生或接收之訊號包含低頻或直流訊號及高頻訊號,則高頻訊號可利用通孔傳遞於晶片與接腳之間,而其餘之低頻或直流訊號仍可利用打線接合(Wire Bonding)的方式傳遞於晶片與接腳之間。換句話說,封裝結構中只要有訊號透過走線層之至少一第一通孔與晶片之至少一第二通孔傳遞於晶片與接腳之間,即滿足本發明需求且屬於本發明之範疇。
另外,封裝結構20可為QFN封裝所衍生之變形,如高功率QFN封裝(Power QFN,PQFN)、薄型QFN封裝(Thin QFN,TQFN)、超薄型QFN封裝(Ultra Thin QFN,UTQFN)、極薄型QFN封裝(Extreme Thin QFN,XQFN),皆屬於本發明之範疇。除此之外,封裝結構20亦可為雙側扁平無引腳封裝(Dual Flat No-lead Package,DFN)及其衍生之變形,如高功率DFN封裝(Power DFN,PDFN)、薄型DFN封裝(Thin DFN,TDFN)、超薄型DFN封裝(Ultra Thin DFN,UTDFN)、極薄型DFN封裝(Extreme Thin DFN,XDFN),皆屬於本發明之範疇。
封裝結構20係說明封裝單一晶片之實施例,其係用以降低於封裝結構於高頻時所產生之損耗。除此之外,本發明亦可應用於多晶片之封裝,例如,若將多個晶片於垂直方向上適當地堆疊,則可進一步形成一三維封裝結構。舉例來說,請繼續參考第4圖,第4圖為本發明實施例一三維封裝結構40之示意圖。封裝結構40係為包含接腳402_1~402_N之QFN封裝,接腳402_1~402_N設置於封裝結構40之下方,如第4圖所示,三維封裝結構40包含有晶片400_1~400_3、走線層408_1、408_2、及一模封蓋406,為求簡潔,第4圖僅繪示接腳402_1~402_N中之二接腳402a、402b,而接腳402_a、402_b分別用來傳遞高頻訊號RF_a、RF_b至外部電路板。走線層408_1、408_2電性連接於接腳402_a、402_b並設置於晶片400_3與接腳402_a、402_b之間,走線層408_1、408_2中形成有通孔408_via,走線層408_1、408_2亦可為可電性導通封裝結構40之一導電支架(未繪示於第4圖)之介質。晶片400_1~400_3皆可為未經封裝之晶粒,其相互堆疊(即晶片400_1設置於晶片400_2之上且晶片400_2設置於晶片400_3之上)而設置於走線層408_1之上,晶片400_1~400_3中可透過熱導孔製程而各自形成有通孔400_via,晶片400_1~400_3用來產生或接收高頻訊號RF_a、RF_b。模封蓋406可為環氧樹脂或氣腔封裝等模封材料所製成,而不在此限。模封蓋406用來包覆走線層408_1、408_2及晶片400_1~400_3,使得封裝結構20之外觀與一般四方扁平無引腳封裝相同。如此一來,訊號RF_a、RF_b即可透過通孔400_via及通孔408_via或導電支架直接由接腳402_a、402_b傳遞至晶片400_1~400_3(或由晶片400傳遞至接腳402_a、402_b),即通孔400_via及通孔408_via用來提供晶片400_1~400_3與走線層408_1、408_2之間之走線。需注意的是,三維封裝結構40係用以說明本發明之概念,本領域具通常知識者當可據以做不同之修飾,而不限於此。舉例來說,三維封裝結構所包含之晶片個數並未有所限,可包含複數個晶片,該複數個晶片只要有一晶片利用熱導孔製程以形成通孔400_via,即滿足本發明需求且屬於本發明之範疇。另外,三維封裝結構之走線層之層數不限於二層,亦可僅包含一層走線層,而走線層中之通孔亦可利用垂直鑽孔、斜角鑽孔或曲線鑽孔的方式來形成,而不在此限。其餘變化方式可參考前述相關段落,於此不贅述。
由上述可知,本發明之封裝結構利用形成於晶片與走線層之通孔來傳遞高頻訊號,避免高頻訊號的傳遞路徑與模封蓋接觸,於高頻時不會產生寄生電感。相較於習知技術,本發明之封裝結構於高頻時的損耗較小,且適用於表面黏著技術之封裝,可經大量的組裝製造成各類行動裝置。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
10、20、40、50‧‧‧封裝結構
100、200、400_1、400_2、400_3、500‧‧‧晶片
200_gnd‧‧‧晶片接地部
104‧‧‧金屬線
202_a、202_b、402_a、402_b、502_a、502_b‧‧‧接腳
202_ gnd‧‧‧接地接腳
106、206、406、506‧‧‧模封蓋
200_via、208_via、400_via、408_via、500_via、508_via‧‧‧通孔
208_1、208_2、408_1、408_2、508‧‧‧走線層
100、200、400_1、400_2、400_3、500‧‧‧晶片
200_gnd‧‧‧晶片接地部
104‧‧‧金屬線
202_a、202_b、402_a、402_b、502_a、502_b‧‧‧接腳
202_ gnd‧‧‧接地接腳
106、206、406、506‧‧‧模封蓋
200_via、208_via、400_via、408_via、500_via、508_via‧‧‧通孔
208_1、208_2、408_1、408_2、508‧‧‧走線層
第1圖為習知一封裝結構之剖面示意圖。 第2圖為本發明實施例一封裝結構之剖面示意圖。 第3圖為第1圖之封裝結構與第2圖之封裝結構之穿透係數之頻率響應之示意圖。 第4圖為本發明實施例一三維封裝結構之示意圖。 第5圖為本發明實施例一封裝結構之剖面示意圖。
20‧‧‧封裝結構
200‧‧‧晶片
200_gnd‧‧‧晶片接地部
202_a、202_b‧‧‧接腳
202_gnd‧‧‧接地接腳
206‧‧‧模封蓋
200_via、208_via‧‧‧通孔
208_1、208_2‧‧‧走線層
Claims (12)
- 一種封裝結構,包含有:至少一接腳,用來傳遞至少一訊號;至少一走線層,連接於該至少一接腳,該至少一走線層中形成有至少一第一通孔或為可電性導通該封裝結構之一導電支架(Lead Frame)之介質;一晶片,設置於該至少一走線層之上,該晶片形成有至少一第二通孔,該晶片產生或接收該至少一訊號,該至少一訊號透過該至少一第二通孔傳遞於該晶片之一第一面與該晶片之一第二面之間;以及一模封蓋,用來包覆該至少一走線層及該晶片;其中,該至少一訊號透過該至少一第一通孔及該至少一第二通孔或該至少一訊號透過該導電支架傳遞於該晶片與該至少一接腳之間;其中,該至少一走線層設置於該至少一接腳與該模封蓋之間,使得該模封蓋不與該至少一接腳直接接觸。
- 如請求項1所述之封裝結構,其中該封裝結構為一四方扁平無引腳封裝(Quad Flat No-lead Package,QFN)或一雙側扁平無引腳封裝(Dual Flat No-lead Package,DFN)。
- 如請求項1所述之封裝結構,其中該至少一走線層係以一薄型印刷電路板(Laminate PCB)或一陶瓷材質所製成。
- 如請求項1所述之封裝結構,其中該至少一第二通孔係以一熱導孔(Hot Via)所製成。
- 如請求項1所述之封裝結構,其中該模封蓋為環氧樹脂(Molding Compound)或氣腔(Air-Cavity)封裝等模封材料所製成。
- 如請求項1所述之封裝結構,其中該至少一接腳形成於該至少一走線層之一第一走線層之下方,該模封蓋包覆該晶片於該至少一走線層之一第二走線層之上方。
- 一種三維(3D)封裝結構,包含有:至少一接腳,用來傳遞至少一訊號;至少一走線層,連接於該至少一接腳,該至少一走線層中形成有至少一第一通孔或為可電性導通該三維封裝結構之一導電支架(Lead Frame)之介質;複數個晶片,相互堆疊而設置於該至少一走線層之上,該複數個晶片中至少一第一晶片形成有至少一第二通孔,該至少一第一晶片產生或接收該至少一訊號;以及一模封蓋,用來包覆該至少一走線層及該複數個晶片;其中,該至少一訊號透過該至少一第一通孔及該至少一第二通孔或該至少一訊號透過該導電支架傳遞於該至少一第一晶片與該至少一接腳之間;其中,該至少一走線層設置於該至少一接腳與該模封蓋之間,使得該模封蓋不與該至少一接腳直接接觸。
- 如請求項7所述之三維封裝結構,其中該封裝結構為一四方扁平無引腳封裝(Quad Flat No-lead Package,QFN)或一雙側扁平無引腳封裝(Dual Flat No-lead Package,DFN)。
- 如請求項7所述之三維封裝結構,其中該至少一走線層係以一薄型印刷電路板(Laminate PCB)或一陶瓷材質所製成。
- 如請求項7所述之三維封裝結構,其中該至少一第二通孔係以一熱導孔(Hot Via)所製成。
- 如請求項7所述之三維封裝結構,其中該模封蓋為環氧樹脂(Molding Compound)或氣腔(Air-Cavity)封裝等模封材料所製成。
- 如請求項7所述之三維封裝結構,其中該至少一接腳形成於該至少一走線層之一第一走線層之下方,該模封蓋包覆該複數個晶片於於該至少一走線層之一第二走線層之上方。
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CN106298708B (zh) | 2019-05-07 |
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