JP2013077765A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2013077765A JP2013077765A JP2011217877A JP2011217877A JP2013077765A JP 2013077765 A JP2013077765 A JP 2013077765A JP 2011217877 A JP2011217877 A JP 2011217877A JP 2011217877 A JP2011217877 A JP 2011217877A JP 2013077765 A JP2013077765 A JP 2013077765A
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- semiconductor chip
- semiconductor device
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- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】表面側に電極面を有する半導体チップ10と、半導体チップ10の表面側と接合され、半導体チップ10の電極と電気的に接続されて、半導体チップ10の外周よりも外側へその電位を引き出すための配線が設けられた第1配線基板20と、接合材14を介して半導体チップの裏面側と接合された第1支持体30と、を有することを特徴とする半導体装置。
【選択図】図2
Description
12 半田ボール
14 半田層
16 アンダーフィル材
18 グランド層
20 プリントボード
21 グランドパターン
22 リフロー半田
23 ビアホール
24 レジストパターン
25 ビアホール
26 分離部
28 レジスト開口部
30 筐体
32 凹部
40 PCB
42 開口部
50 支持基板
52 ネジ止め
60 第1内部金属層
62 第2内部金属層
RF 信号ライン
VGG ゲートバイアスライン
VDD ドレインバイアスライン
GND グランドライン
Claims (9)
- 表面側に電極面を有する半導体チップと、
前記半導体チップの表面側と接合され、前記半導体チップの電極と電気的に接続されて、前記半導体チップの外周よりも外側へその電位を引き出すための配線が設けられた第1配線基板と、
接合材を介して前記半導体チップの裏面側と接合された第1支持体と、
を有することを特徴とする半導体装置。 - 前記半導体チップの表面側には、グランド電位と共通に接続され、複数の電極が配置された金属層が設けられてなることを特徴とする請求項1記載の半導体装置。
- 前記第1支持体と前記接合材との間には、第2支持体が介在してなることを特徴とする請求項1または2に記載の半導体装置。
- 前記第2支持体には、第2支持体を前記第1支持体にネジ止めをするための貫通孔が形成されていることを特徴とする請求項3に記載の半導体装置。
- 前記半導体チップと前記第1配線基板とは、半田ボールあるいはバンプにより電気的に接続されていることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。
- 前記半導体チップの外周は前記第1配線基板の外周の内側に位置することを特徴とする請求項1〜7のいずれか1項に記載の半導体装置。
- 前記第1配線基板には、前記半導体チップと前記第1配線基板とが対向する対向領域の内側から、外側に延在する配線が設けられてなることを特徴とする請求項6に記載の半導体装置。
- 前記第1基板に設けられた配線は、前記第1支持体側に配置された第2配線基板と接続するための電極が設けられてなることを特徴とする請求項1に記載の半導体装置。
- 表面側に電極面を有する半導体チップと、
前記半導体チップの表面側と接合され、前記半導体チップの電極と電気的に接続される第1配線基板と、
接合材を介して前記半導体チップの裏面側と接合される第1支持体と、
前記第1支持体側に設けられ、前記第1配線基板と電気的に接続される第2配線基板と、
を有することを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2011217877A JP5987222B2 (ja) | 2011-09-30 | 2011-09-30 | 半導体装置 |
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JP2011217877A JP5987222B2 (ja) | 2011-09-30 | 2011-09-30 | 半導体装置 |
Publications (2)
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JP2013077765A true JP2013077765A (ja) | 2013-04-25 |
JP5987222B2 JP5987222B2 (ja) | 2016-09-07 |
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JP2011217877A Active JP5987222B2 (ja) | 2011-09-30 | 2011-09-30 | 半導体装置 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111312671A (zh) * | 2018-12-05 | 2020-06-19 | 三菱电机株式会社 | 半导体装置 |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07240496A (ja) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | 半導体装置、その製造方法、半導体素子のテスト方法、そのテスト基板およびそのテスト基板の製造方法 |
JPH098432A (ja) * | 1995-06-22 | 1997-01-10 | Mitsubishi Electric Corp | 高周波回路装置 |
JPH09260583A (ja) * | 1996-03-18 | 1997-10-03 | Nippon Telegr & Teleph Corp <Ntt> | 高周波半導体装置 |
JPH11503565A (ja) * | 1995-03-29 | 1999-03-26 | オリン コーポレイション | 集積回路装置を収容するための部品 |
JPH11195730A (ja) * | 1997-10-30 | 1999-07-21 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2002305263A (ja) * | 2001-04-09 | 2002-10-18 | Nippon Telegr & Teleph Corp <Ntt> | 半導体素子実装用パッケージおよび半導体素子実装方法 |
WO2003012863A1 (en) * | 2001-07-31 | 2003-02-13 | Renesas Technology Corp. | Semiconductor device and its manufacturing method |
US20030143831A1 (en) * | 2001-11-30 | 2003-07-31 | Mcdonough Robert J. | Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier |
JP2003258142A (ja) * | 2002-02-28 | 2003-09-12 | Hitachi Ltd | 半導体装置 |
US20060043581A1 (en) * | 2004-09-01 | 2006-03-02 | Victor Prokofiev | IC package with power and singal lines on opposing sides |
JP2006066719A (ja) * | 2004-08-27 | 2006-03-09 | Mitsubishi Electric Corp | マイクロ波モジュール |
-
2011
- 2011-09-30 JP JP2011217877A patent/JP5987222B2/ja active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07240496A (ja) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | 半導体装置、その製造方法、半導体素子のテスト方法、そのテスト基板およびそのテスト基板の製造方法 |
JPH11503565A (ja) * | 1995-03-29 | 1999-03-26 | オリン コーポレイション | 集積回路装置を収容するための部品 |
JPH098432A (ja) * | 1995-06-22 | 1997-01-10 | Mitsubishi Electric Corp | 高周波回路装置 |
JPH09260583A (ja) * | 1996-03-18 | 1997-10-03 | Nippon Telegr & Teleph Corp <Ntt> | 高周波半導体装置 |
JPH11195730A (ja) * | 1997-10-30 | 1999-07-21 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2002305263A (ja) * | 2001-04-09 | 2002-10-18 | Nippon Telegr & Teleph Corp <Ntt> | 半導体素子実装用パッケージおよび半導体素子実装方法 |
WO2003012863A1 (en) * | 2001-07-31 | 2003-02-13 | Renesas Technology Corp. | Semiconductor device and its manufacturing method |
US20030143831A1 (en) * | 2001-11-30 | 2003-07-31 | Mcdonough Robert J. | Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier |
JP2003258142A (ja) * | 2002-02-28 | 2003-09-12 | Hitachi Ltd | 半導体装置 |
JP2006066719A (ja) * | 2004-08-27 | 2006-03-09 | Mitsubishi Electric Corp | マイクロ波モジュール |
US20060043581A1 (en) * | 2004-09-01 | 2006-03-02 | Victor Prokofiev | IC package with power and singal lines on opposing sides |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111312671A (zh) * | 2018-12-05 | 2020-06-19 | 三菱电机株式会社 | 半导体装置 |
CN111312671B (zh) * | 2018-12-05 | 2024-01-05 | 三菱电机株式会社 | 半导体装置 |
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JP5987222B2 (ja) | 2016-09-07 |
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