TW201503268A - 半導體三維封裝體、半導體結構及其製作方法 - Google Patents

半導體三維封裝體、半導體結構及其製作方法 Download PDF

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TW201503268A
TW201503268A TW103104684A TW103104684A TW201503268A TW 201503268 A TW201503268 A TW 201503268A TW 103104684 A TW103104684 A TW 103104684A TW 103104684 A TW103104684 A TW 103104684A TW 201503268 A TW201503268 A TW 201503268A
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semiconductor
dielectric layer
conductive plug
semiconductor structure
layer
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TW103104684A
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TWI538065B (zh
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Po-Hao Tsai
Jui-Pin Hung
Jing-Cheng Lin
Long-Hua Lee
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

一種半導體結構包括：一封膠材料；一導電插塞，位於封膠材料中；一覆蓋元件，位於導電插塞和封膠材料間之一頂部接點上方；及一介電層，位於覆蓋元件上且位於封膠材料上方。

Description

半導體三維封裝體、半導體結構及其製作方法
本揭示係有關於一種半導體元件，特別是有關於一種三維積體擴散型封裝體(three dimensional integrated fan out package)。
半導體元件廣泛的應用於各種應用。隨著使用者在效能和功能的需求增加，半導體元件的幾何尺寸快速的下降。例如，現在市場上的3G行動電話需能進行通訊、影像擷取和處理高流量的資料。為了滿足上述需求，3G行動電話需在有限的空間配備不同的元件，例如處理器、記憶體和影像感測器。
於一封裝體中結合數個感測器可達成增進積體電路元件的效能，使其具有各種不同的功能。現在這領域的主要發展具有多層的結構之三維封裝體，以儲存較多的小型半導體構件。
一個三維的半導體積體電路封裝體包含數個不同的次結構。此次結構是以彼此堆疊的方式彼此接觸或藉由內連線彼此連結。然而，次結構不同的特性亦會對設計者造成挑戰。與二維的半導體封裝體相比較，三維的半導體封裝體由於較複雜，因此失效的種類增加。根據上述，三維的半導體封裝 體結構和方法的改進係持續的進行。
根據上述，本揭示於一實施例提供一種半導體結構包括：一封膠材料；一導電插塞，位於封膠材料中；一覆蓋元件，位於導電插塞和封膠材料間之一頂部接點上方；及一介電層，位於覆蓋元件上且位於封膠材料上方。
本揭示於一實施例提供一種半導體三維封裝體，包括：一封膠材料；一填充導孔，位於封膠材料中；一介電層，位於封膠材料上；一分隔元件，位於封膠材料上，其中分隔元件、填充導孔和封膠材料形成三方界面，且分隔元件將介電層與三方界面分開。
本揭示於一實施例提供一種半導體結構之製作方法，包括：於一基底上形成一導電插塞；以一封膠材料包圍導電插塞之側壁；及於一頂部接點上方設置一分隔元件，其中頂部接點位於封膠材料和導電插塞間。
10‧‧‧3D半導體結構
15‧‧‧半導體晶片
20‧‧‧封膠材料
21‧‧‧底部表面
23‧‧‧頂部表面
25‧‧‧頂部接點
30‧‧‧導電插塞
32‧‧‧凸起部分
35‧‧‧界面
40‧‧‧覆蓋元件或分隔元件
42‧‧‧延伸部
43‧‧‧空穴
44‧‧‧外部邊緣
45‧‧‧內部邊緣
46‧‧‧虛線
47‧‧‧第一部分
48‧‧‧凸塊下金屬層
49‧‧‧第二部分
50‧‧‧介電堆疊
60‧‧‧銲料球
152‧‧‧鈍化層
154‧‧‧接合墊
421‧‧‧端
471‧‧‧重分佈層
472‧‧‧重分佈層
480‧‧‧晶種層
501‧‧‧第一介電層
502‧‧‧第二介電層
503‧‧‧第三介電層
504‧‧‧第四介電層
512‧‧‧貫穿結構
513‧‧‧貫穿結構
471‧‧‧重分佈層
472‧‧‧重分佈層
572‧‧‧重分佈層
700‧‧‧載板
702‧‧‧緩衝層
703‧‧‧晶粒貼合薄膜
705‧‧‧晶種層
708‧‧‧圖案化層
710‧‧‧導電柱
715‧‧‧薄膜
725‧‧‧導電薄膜
2540‧‧‧頂部接點
第1圖顯示三維半導體結構之概式圖。
第2A-2B圖顯示不同視點包括封膠材料和導電插塞之半導體結構。
第3A-3B圖顯示不同視點包括封膠材料和導電插塞之半導體結構。
第4圖顯示構成為積體封裝之三維半導體結構。
第5圖顯示具有填充導孔之三維半導體結構。
第6A-6B圖顯示不同視點包括封膠材料和導電插塞之半導體結構。
第7A-7H圖顯示三維半導體結構之製作方法。
第8A-8D圖顯示三維半導體結構之製作方法。
第9A-9F圖顯示三維半導體結構之製作方法。
第10A-10B圖顯示三維半導體結構之製作方法。
第11圖顯示本揭示一些實施例之三維積體電路封裝體。
本揭示設計一三維(3D)半導體結構或封裝體，以防止於封裝體的結構中產生薄膜內的破裂傳遞(in-film crack propagating)。一導體和其周圍介電層(通常為molding compound(封膠材料))熱膨脹係數的不同會導致後續製程破裂的發展。此破裂通常被發現經由其上的層傳遞，且通常會造成其上的導體破裂或變弱，在製造和產品操作過程中造成斷路。不希望的斷路會造成產品的失效。因此，需要對結構進行改善，以防止薄膜內的破裂傳遞至其上的層。
根據各種實施例，3D半導體結構包括薄膜層，用以防止導電插塞和周圍封膠材料之界面的破裂，導致其上的導體產生破裂。此薄膜層保護鑲嵌半導體晶片和一些內連線。此薄膜層亦可稱為分隔元件和覆蓋元件，且設置於容易發生破裂的特定界面上，以防止破裂的傳遞由此產生。
第1圖顯示一3D半導體結構10。3D半導體結構10具有一半導體晶片15，位於3D半導體結構10之底部。位於半導體晶片15之側壁，一封膠材料20包圍半導體晶片15。3D半導體 結構10於封膠材料20中具有一導電插塞30，且導電插塞30穿過封膠材料20。
半導體晶片15具有一鈍化層152，鈍化層152包括介電材料，例如旋轉塗佈玻璃(SOG)、氧化矽、氮氧化矽、氮化矽或類似的材料。半導體晶片15具有一接合墊154，位於其頂部表面。鈍化層中提供一開口，以暴露部分的接合墊154。
封膠材料20可以為一單一層薄膜或複合堆疊層。其包括各種的材料，例如一或多個環氧樹脂、酚系硬化劑、矽石、活性觸媒、色料、脫模劑或類似的材料。形成之封膠材料具有高熱導率、低水氣吸收率，在板安裝溫度下具有高撓性強度(flexural strength)，或其組合。
在一些實施例中，3D半導體結構10具有聚合物緩衝層(第1圖未繪示)，且聚合物緩衝層位於封膠材料20的底部。
導電插塞30在封膠材料的頂部表面23具有一端，且在封膠材料20的底部表面21具有另一端。在一些實施例中，導電插塞30是一填入導電材料的導孔(via)。填入導孔或導電插塞之導電材料包括金、銀、銅、鎳、鎢、鋁、錫及/或上述合金。
一頂部接點25定義為導電插塞30和封膠材料20間之界面的頂部。從上視圖來看，頂部接點25是將導電插塞30和封膠材料20分隔之一條線或邊緣。頂部接點25包圍導電插塞30。藉由增加一薄膜或層於頂部接點25上，增加的薄膜或層、導電插塞30和封膠材料20形成三方界面。當增加的薄膜或層與導電插塞30有相同的材料，與封膠材料形成的界面是一在頂部 接點25具有兩個材料的直角界面。
一導電柱45位於接合墊154之頂部表面。在導電柱45之一端，導電柱45電性連接半導體晶片15之接合墊154。在導電柱45之另一端，導電柱45電性連接一內連線。導電柱45包括金、銀、銅、鎳、鎢、鋁、鈀及/或上述合金。導電柱45可以下列製程形成：例如蒸鍍、電鍍、氣相沈積、濺鍍或網印。
半導體結構包括例如重分佈層(redistribution layer，以下簡稱RDL)471及472之內連線。在如第1圖之一些實施例中，重分佈層471、472各包括一晶種層480。重分佈層是半導體晶片15和外部電路間之電性連接。在第1圖中，RDL 471在一端電性連接導電柱45。在RDL 471之另一端，RDL 471電性連接RDL 472。例如RDL471和472之內連線包括金、銀、銅、鎳、鎢、鋁、鈀及/或上述合金。
一凸塊下金屬層(under bump metallurgy，以下簡稱UBM)設置於半導體結構10之頂部表面上。UBM 48具有一底部部分，且底部部分電性連接至RDL 472之一端。UBM 48具有一頂部表面482，以容納焊球及焊料。在一些實施例中，UBM 48包括金、銀、銅、鎳、鎢、鋁、鈀及/或上述合金。
請參照第1圖，一覆蓋元件40位於頂部接點25之上方，且位於導電插塞30上和封膠材料20上。覆蓋元件40、導電插塞30和封膠材料20形成三方界面。覆蓋元件40包括延伸部42，其為部分的覆蓋元件40，設置於封膠材料20之頂部表面23上。延伸部42之長度d是從頂部接點25量測至延伸部42之一端421。在一些實施例中，延伸部42之長度d大於2.5μm。在一些 實施例中，延伸部42之長度d大於7.5μm。
在一些實施例中，如第1圖所示，覆蓋元件40在一剖面中包括兩個延伸部42。延伸部42對於導電插塞30對稱的設置，亦即，各延伸部42沿著封膠材料20之頂部表面23延伸相同的距離。在具有兩個延伸部之一些實施例中，一位於導電插塞一側的延伸部較另一延伸部長。在一些實施例中，覆蓋元件具有導電性。覆蓋元件可包括金、銀、銅、鎳、鎢、鋁、鈀及/或上述合金。在一些實施例中，覆蓋元件不具有導電性。覆蓋元件可包括氧化矽、氮化矽、氮氧化矽。在一些實施例中，覆蓋元件包括橡膠或聚合物材料，例如環氧化合物、聚亞醯胺(polyimide)、聚苯噁唑(Polybenzoxazole，PBO)或類似的材料。
一介電堆疊形成於3D半導體結構中，以於導電單元和內連線間提供電性隔離。介電堆疊亦保護內部結構，防止其暴露於外部環境中。在一些實施例中，如第1圖所示，介電堆疊50包括三個不同的層：第一介電層501；第二介電層502和第三介電層503。形成於半導體晶片15上的第一介電層501具有聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜(Ajinomoto Build-up Film)或類似的材料。在一些實施例中，第一介電層501將半導體晶片15與RDL 417隔離。在一些實施例中，第一介電層501是鈍化層152和第二介電層502間的應力緩衝。
第二介電層502位於第一介電層501和封膠材料20上。第二介電層502將RDL 471與RDL 472隔離。第二介電層502具有一貫穿結構512。RDL 472經由貫穿結構512中電性連接 RDL 471。第二介電層502包括聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。第二介電層502亦可包括介電材料，例如旋轉塗佈玻璃(SOG)、氧化矽、氮氧化矽或類似的材料，且其可以任何適合的方法形成，例如旋轉塗佈或氣相沈積。在如第1圖所示之一些實施例中，第二介電層502亦位於覆蓋元件40和RDL 471上。
第三介電層503形成於第二介電層502和RDL 472上，且其包括聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。第三介電層503用以保護RDL 472，防止其暴露於外部環境中。第三介電層503具有一貫穿結構513。一凸塊下金屬層(UBM)48形成於貫穿結構513中，且電性連接RDL 472。第三介電層503亦可包括介電材料，例如旋轉塗佈玻璃(SOG)、氧化矽、氮氧化矽、或類似的材料，且其可以任何適合的方法形成，例如旋轉塗佈或氣相沈積。在第1圖中，覆蓋元件40將第二介電層502與三方界面分開。三方界面係位於覆蓋元件40、導電插塞30和封膠材料20間。一旦頂部接點25處產生任何破裂，覆蓋元件40可防止破裂傳遞至第二介電層。
在一些實施例中，導電插塞30之熱膨脹係數為介於5×10-6m/mK和20×10-6m/mK間，且封膠材料20之熱膨脹係數為介於5×10-6m/mK和75×10-6m/mK間。若施加熱循環於3D半導體結構10上，由於導電插塞30和封膠材料20熱膨脹係數不匹配，在頂部接點25可能會產生破裂。位於頂部接點25上的覆蓋元件40提供半導體結構一阻障，使得破裂無法由頂部接點25傳 遞至第二介電層502。
根據各實施例，3D半導體結構中的一覆蓋元件或一分隔元件係設計用來防止破裂傳遞。在一些實施例中，覆蓋元件是覆蓋封膠材料和導電插塞間頂部接點之板材。在一些實施例中，覆蓋元件是圈形或環形。請參照第2A圖，一半導體結構10包括一封膠材料20和一導電插塞30。導電插塞30位於封膠材料20中。封膠材料20包圍導電插塞30之側壁。一界面係位於封膠材料20和導電插塞30間。一頂部接點25位於界面之頂部。從一上視觀點，頂部接點25是將導電插塞30和封膠材料20分隔之一條線或邊緣。覆蓋元件40位於頂部接點25上方且位於部分的導電插塞30上。覆蓋元件40亦位於部分的封膠材料20上。第2B圖是覆蓋元件40之上視圖。覆蓋元件40是一圈形且具有一內部邊緣45和一外部邊緣44。一虛線46位於內部邊緣45和外部邊緣44間。虛線46代表頂部接點25。一空穴43位於內部邊緣45內。於空穴43中填入第二介電層502。覆蓋元件40之外部寬度是d1，且空穴43或內部邊緣45之寬度是d2。在一些實施例中，覆蓋元件外部寬度和空穴或內部邊緣寬度間的差距的一半大於2.5μm，亦即(d1-d2)/2>2.5μm。換句話說，圈的厚度(外部邊緣至內部邊緣的距離)大於約3μm。在一些實施例中，外部邊緣寬度與空穴寬度間的差距大於15μm，亦即d1-d2>15μm。
在一些實施例中，如第3A圖所示，覆蓋元件40為一環形。覆蓋元件40位於頂部接點25上、部分的導電插塞30和部分的封膠材料20上。第3B圖顯示覆蓋元件40的上視圖。覆蓋元件40具有一內部邊緣45和一外部邊緣44。一虛線46位於內部 邊緣45和外部邊緣44間。虛線46代表導電插塞30和封膠材料20間的界面。一空穴43位於內部邊緣45內。於空穴43中填入第二介電層502。對於覆蓋元件40，覆蓋元件40之外部寬度是d1，且空穴43或內部邊緣45之寬度是d2。在一些實施例中，覆蓋元件外部寬度和空穴或內部邊緣寬度間的差距的一半大於2.5μm，亦即(d1-d2)/2>2.5μm。在一些實施例中，外部邊緣寬度d1與空穴寬度d2間的差距大於15μm，亦即d1-d2>15μm。
在一些實施例中，覆蓋元件40是一多邊環形。在一些實施例中，覆蓋元件40是一三角環形。在一些實施例中，覆蓋元件40是一四邊環形。在一些實施例中，接點是位於多邊環形之外部邊緣和內部邊緣間。多邊環形之內部亦具有一空穴，且空穴位於接點內。
在一些實施例中，覆蓋元件不直接接觸封膠材料和導電插塞。覆蓋元件位於封膠材料和導電插塞間之接點上方。在接點產生之破裂僅可在覆蓋元件下延伸，破裂無法傳遞至覆蓋元件上的任何其他區域。
在第4圖中，根據本揭示的一些實施例，半導體結構10是一3D半導體封裝體。3D半導體封裝體10具有一封膠材料20，包圍一導電插塞30。一頂部接點25位於導電插塞30和封膠材料20間之界面的頂部上。從上視圖觀點，頂部接點25是將導電插塞30和封膠材料20分隔之一條線或邊緣。導電插塞30的寬度是w1。在一些實施例中，寬度w1是導電插塞30的直徑。一第二介電層502位於導電插塞30上。一覆蓋元件40位於第二介電層502上，且位於頂部接點25上方。覆蓋元件40具有一寬 度w2。覆蓋元件40之寬度w2大於導電插塞之寬度w1，亦即w2>w1。在一些實施例中，w2-w1大體上等於5μm。在一些實施例中，w2-w1大於5μm。在一些實施例中，w2-w1大於15μm。一凸起部分32位於導電插塞30上且支撐覆蓋元件40。凸起部分32在一端連接導電插塞30，且在另一端連接覆蓋元件40。在一些實施例中，覆蓋元件40是以形成RDL472相同的步驟形成。在一些實施例中，凸起部分32是以形成RDL471相同的步驟形成。在一些實施例中，凸起部分32具有導電性。
在一些實施例中，覆蓋元件或分隔元件是RDL的一部分。覆蓋元件或分隔元件電性連接至導電插塞(藉由填入一導孔形成)和外部電路，其中導電插塞是於導孔中填入導電材料形成。請參照第5圖，3D半導體結構10具有一填充導孔30。填充導孔30包括金、銀、銅、鎳、鎢、鋁及/或上述合金。填充導孔30位於封膠材料20中且具有兩端。一端連接至覆蓋元件40，且另一端連接至外部電路，其中外部電路位於半導體結構10之底部表面。在特定的實施例中，填充導孔30之一端連接至覆蓋元件40，且另一端連接至位於一緩衝層上的外部電路。緩衝層位於半導體結構10之底部表面上。覆蓋元件40位於頂部接點25上且具有兩個部分。第一部分47大體上沿著封膠材料20之頂部表面23延伸。第一部分47位於頂部接點25上方且具有一延伸部，位於頂部接點25上。延伸部位各邊於封膠材料20上的最小覆蓋範圍至少為2.5μm。覆蓋元件40具有一第二部分49。第二部分49大體上沿著第二介電層502的側壁。覆蓋元件40是於形成RDL471之相同步驟形成。在一些實施例中，覆蓋元件40 是部份的RDL。
上述3D半導體結構10具有四個介電層。第一介電層501位於半導體晶片15上。第一介電層501具有聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜(Ajinomoto Build-up Film)或類似的材料。第一介電層501將半導體晶片15與RDL471隔離。第二介電層502形成於第一介電層501、封膠材料20和導電柱45上，第二介電層502具有聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。第二介電層亦可包括介電材料，例如旋轉塗佈玻璃(SOG)、氧化矽、氮氧化矽或類似的材料，且其可以任何適合的方法形成，例如旋轉塗佈或氣相沈積。一RDL471形成於第二介電層502上。第二介電層502具有一貫穿結構512。RDL471之一部分形成於貫穿結構512之側壁上。RDL471在一端連接至導電柱45。
第三介電層503可以是聚合物材料或沉積的介電材料。第三介電層503可以形成於第二介電層502和RDL471上。第三介電層503可具有聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。第三介電層亦可包括介電材料，例如旋轉塗佈玻璃(SOG)、氧化矽、氮氧化矽或類似的材料，且其可以任何適合的方法形成，例如旋轉塗佈、層壓法或氣相沈積。第三介電層503將RDL 471與RDL 472隔離。RDL 471使用一貫穿結構513連接RDL 472。一貫穿結構513連接RDL 471和RDL 472。RDL 472形成於第三介電層503上。第三介電層503之貫穿結構513提供形成RDL472之 側壁，以連接RDL 471。
第四介電層504形成於第三介電層503和RDL472上。第四介電層504可具有聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。第四介電層504亦可包括介電材料，例如旋轉塗佈玻璃(SOG)、氧化矽、氮氧化矽或類似的材料，且其可以任何適合的方法形成，例如旋轉塗佈、層壓法、壓鑄模法或氣相沈積。第四介電層504保護RDL 472，防止其暴露於外部環境中。第四介電層504具有一貫穿結構514。凸塊下金屬層(UBM)48形成於貫穿結構514中，且電性連接RDL 472。第四介電層504保護RDL472，使其避免暴露於外部環境。
一銲料球60位於凸塊下金屬層48上。銲料球60接合凸塊下金屬層48之頂部表面，且電性連接一外部電路。在一些實施例中，銲料球60是一焊錫膏。
請參照第6A圖，在本揭示一些實施例中，一3D半導體封裝體10具有一封膠材料20。封膠材料20鄰接半導體晶片15。一填充導孔30位於封膠材料20中。填充導孔30是一位於封膠材料20中的穿導孔。一界面35位於封膠材料20和填充導孔30間。一第二介電層502位於封膠材料20和填充導孔30上。一分隔元件40位於界面35上方。分隔元件40、封膠材料20和填充導孔30一起形成三方界面37。在一些實施例中，填充導孔30之線性溫度膨脹係數為介於4×10-6m/mK和20×10-6m/mK之間，且封膠材料20之線性溫度膨脹係數為介於30×10-6m/mK和100×10-6m/mK之間。封膠材料20和填充導孔30之溫度膨脹係數具有顯 著的差異。為了防止任何破裂傳遞至第二介電502，分隔元件40將三方界面37與第二介電層502分隔。
在如第6A圖所示之一些實施例中，分隔元件40具有一高度H1，大體上沿著填充導孔30的軸向延伸。第6B圖為分隔元件40之上視圖。從上視圖觀點，分隔元件40是圈形。在一些實施例中，分隔元件40是一四邊圈形。在一些實施例中，分隔元件40是一三角圈形。在一些實施例中，分隔元件40是一環形。覆蓋元件40具有一內部邊緣45和一外部邊緣44。虛線46代表導電插塞30和封膠材料20間的界面。一空穴43位於內部邊緣45內。於空穴43中填入第二介電層502。外部邊緣之寬度是d1，且內部邊緣之寬度是d2。在一些實施例中，外部邊緣之寬度和內部邊緣之寬度間的差距的一半大於2.5μm，亦即(d1-d2)/2>2.5μm。在一些實施例中，外部邊緣之寬度和內部邊緣之寬度間的差距大於15μm，亦即d1-d2>15μm。
由於熱膨脹係數的差異，填充導孔和封膠材料之界面具有高應力。藉由設置覆蓋元件和分隔元件於界面上，可減少填充導孔上方介電層受到的應力。根據模擬的結果，界面上方量測到的應力大體上等於插塞中央量測到的應力。在一些實施例中，當使用覆蓋元件或分隔元件，界面量測到的應力約大於插塞中央量測到應力之5%至10%。若沒有覆蓋元件或分隔元件，界面量測到的應力約等於或大於插塞中央量測到應力之50%。
3D半導體結構之製作方法和其半導體結構具有一覆蓋元件或一分隔元件，以防止破裂傳遞至介電層。此方法包 括數個操作且其描述和揭示不視為操作順序的揭示。
以下的描述使用「圖形化」或「圖案化」以描述於一表面上形成預定圖案之操作。圖案化之操作包括各步驟和製程，且對應於實施例的圖樣變化。在一些實施例中，圖案化之操作是用來圖案化存在的薄膜或層。圖案化的操作包括形成一罩幕層於存在的薄膜或層上，且以一蝕刻或其他移除製程，移除未被罩幕覆蓋的薄膜或層。罩幕是光阻或硬式罩幕。在一些實施例中，圖案化之操作是用來直接於一表面上形成一圖案化層。圖案化操作包括於表面上形成一光阻薄膜，進行一微影製程和顯影製程。剩餘的光阻係保留，且整合至3D半導體結構。
本揭示中使用的用語「鍍層」以描述於一表面上形成薄膜或層之操作。鍍層之操作包括各步驟和製程，且對應於實施例的圖樣變化。於表面上鍍之層是一單一薄膜或一複合堆疊。在一些實施例中，鍍層之操作是用來形成金屬薄膜。在一些實施例中，鍍層之操作包括形成一晶種層和於晶種層上電鍍一金屬薄膜。在一些實施例中，鍍層之操作是一氣相沉積製程。在一些實施例中，鍍層之操作是一濺鍍製程。
本揭示的描述中使用「填入」或「填充」以描述於一孔洞中形成材料之操作。填入之操作包括各步驟和製程，且對應於實施例的圖樣變化。在一些實施例中，填入之操作包括形成一襯層於孔洞之側壁上和形成一導電材料於襯層上。在一些實施例中，填入之操作包括電鍍製程。填入之操作包括氣相沉積製程。在一些實施例中，填入之操作包括一濺鍍製程。
在第7A圖中，提供一用來形成3D半導體結構之載 板700。形成一聚合物緩衝層702於載板700之頂部表面。聚合物緩衝層702包括聚亞醯胺、聚苯噁唑、阻焊劑、光熱轉換薄膜(light to heat conversion film，簡稱LTHC)和ABF薄膜。在一些實施例中，聚合物緩衝層702包括不同材料之至少兩層。形成一晶種層705於聚合物緩衝層702之頂部。晶種層705是一單一層或複合堆疊，且形成之材料包括銅、鈦、鎢、鉭、鈦/銅或上述之組合。在第7B圖中，形成一圖案化層708於晶種層705上。圖案化層708具有數個孔洞718。
在第7C圖中，於孔洞718中填入導電材料710。在一些實施例中，使用電鍍製程填充導電材料710。在第7D圖中，移除圖案化層，保留數個導電柱710於晶種層705上。在第7E圖中，移除部份的晶種層。形成數個導電插塞30於載板700之頂部表面。各導電插塞30包括一晶種層和一導電柱710。
在第7F圖中，將一半導體晶片15置於載板700上，且位於導電插塞30間。在如第7F圖之一些實施例中，在將半導體晶片15置於載板700上之前，形成一晶粒貼合薄膜703(die attachment film，DAF)於聚合物緩衝層703上。將半導體晶片15以一第一介電層501覆蓋。設置一第一導電柱45於半導體晶片15上，以電性連接一內連線。在一些實施例中，第一介電層501是在半導體晶片15置於載板700之後形成於半導體晶片15上。在一些實施例中，在晶片15置於載板700之前，預形成第一介電層501及/或導電柱45於半導體晶片15上。
在第7G圖中，設置封膠材料20於載板700上。封膠材料20覆蓋半導體晶片15、第一介電層501、導電柱45和導電 插塞30。在如第7G圖之一些實施例中，封膠材料20覆蓋導電插塞30之頂部表面。
以下描述的方法包括進行一研磨製程，移除部份的封膠材料20。在第7H圖中，將封膠材料20減少至預定的高度H，以暴露導電柱45。在特定的實施例中，預定高度H為介於50μm至250μm之間。研磨製程亦可減少導電插塞30之高度，使導電插塞30之頂部表面暴露。
第8A-第8D圖顯示本揭示一些實施例於頂部接點上方形成分隔元件之方法，其中頂部接點位於一封膠材料和一導電體間。在第8A圖中，於封膠材料20之頂部表面設置一薄膜715。在一些實施例中，薄膜715之厚度介於1μm和20μm之間。薄膜715包括導電材料，例如包括金、銀、銅、鎳、鎢、鋁、鈀及/或上述合金。在一些實施例中，薄膜715不具有導電性，且可具有橡膠或聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。
在第8B圖中，將薄膜715圖案化以形成分隔元件40。分隔元件40位於頂部接點25上，且具有一從頂部接點25延伸之延伸部42，且覆蓋部分的封膠材料20頂部表面。在一些實施例中，位於封膠材料20頂部表面上之延伸部42為約2.5μm。
在第8C圖之實施例中，分隔元件40之形成材料與重非配層471(RDL)相同。本揭示一些實施例在相同的步驟中將薄膜715圖案化，形成重分佈層471和分隔元件40。在一些實施例中，分隔元件40具有如第8D圖所示之空穴43。
在一些實施例中，在於頂部接點上方形成分隔元 件前形成第二介電層(頂部接點位於封膠材料和導電插塞間)。在第9A圖中，形成一第二介電層502於封膠材料20和第一介電層501上。在一些實施例中，第二介電層502與第一介電層501包括相同的材料。在一些實施例中，第二介電層502與第一介電層501包括聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。在一些實施例中，第二介電層501與第一介電層501包括不同的材料。
在第9B圖中，將第二介電層502圖案化，以形成數個貫穿結構512。將導電插塞30和重分佈層571於之頂部表面於貫穿結構512之底部表面暴露。設置於導電插塞上30的貫穿結構512之底部開口的直徑大於導電插塞30的直徑。在第9C圖中，形成一導電薄膜725於第二介電層502、導電插塞30和重分佈層571上。將導電薄膜725圖案化，以具有如第9D圖所示之數個部分。上述部分包括數個分隔元件40和一重分佈層572。將分隔元件40形成於導電插塞30和貫穿結構512之側壁上。各分隔元件40係位於頂部接點25上方，其中頂部接點25位於封膠材料20和導電插塞30間。在一些實施例中，分隔元件40電性連接導電插塞30。形成重分佈層572於重分佈層571，貫穿結構512之側壁和第二介電層502上。重分佈層572電性連接重分佈層571。在一些實施例中，分隔元件亦是部份的重分佈層。
在一些實施例中，將第二介電層中穿孔的尺寸設計以於導電插塞上形成一柱形的分隔元件。在第9E圖中，將導電插塞上的貫穿結構512調整，以填入導電薄膜725。將貫穿結構512的尺寸設計以填入導電薄膜725。底部開口的直徑大於導 電插塞30的直徑。在第9F圖中，將第二介電層502上之部份的導電薄膜移除。形成數個柱形的分隔元件40於導電插塞30上。形成RDL572於RDL571上。RDL572在一端連接RDL571。在一些實施例中，於一導電插塞上包括至少兩個類柱形之分隔元件。
第10A圖顯示本揭示之一些實施例。在第10A圖中，形成一第三介電層503於第二介電層502上。第三介電層503亦位於RDL572和分隔元件40上。在一些實施例中，第三介電層503與第二介電層502包括不同的材料。在一些實施例中，第三介電層包括聚合物材料，例如環氧化合物、聚亞醯胺、聚苯噁唑、阻焊劑、ABF薄膜或類似的材料。在第10B圖中，形成一貫穿結構513於第三介電層503中。於貫穿結構513之底部開口將部份RDL572的頂部表面暴露。設計底部開口使UBM形成於RDL572之暴露部分上。
第11圖顯示積體3D IC封裝體600。積體3D IC封裝體600包括如第5圖所示的3D半導體結構10和一記憶晶片11。記憶晶片11電性連接3D半導體結構10。
在一些實施例中，具有超過3個介電材料層，形成於3D半導體結構中。在一些實施例中，具有超過2個RDL形成於3D半導體結構中。
在一些實施例中，一半導體結構包括一封膠材料；一導電插塞，位於封膠材料中；一覆蓋元件，位於導電插塞和封膠材料間之一頂部接點上方；及一介電層，位於覆蓋元件上且位於封膠材料上方。
在一些實施例中，一種半導體三維封裝體，包括：一封膠材料；一填充導孔，位於封膠材料中；一介電層，位於封膠材料上；一分隔元件，位於封膠材料上，其中分隔元件、填充導孔和封膠材料形成三方界面，且分隔元件將介電層與三方界面分開。
在一些實施例中，一種半導體結構之製作方法，包括：於一基底上形成一導電插塞；以一封膠材料包圍導電插塞之側壁；及於一頂部接點上方設置一分隔元件，其中頂部接點位於封膠材料和導電插塞間。
雖然本揭示之較佳實施例說明如上，然其並非用以限定本揭示，任何熟習此領域之技術者，在不脫離本揭示之精神和範圍內，當可作些許之更動與潤飾，因此本揭示之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧3D半導體結構
20‧‧‧封膠材料
25‧‧‧頂部接點
30‧‧‧導電插塞
40‧‧‧覆蓋元件
43‧‧‧空穴
44‧‧‧外部邊緣
45‧‧‧內部邊緣
46‧‧‧虛線
502‧‧‧第二介電層

Claims (12)

  1. 一種半導體結構，包括：一封膠材料；一導電插塞，位於該封膠材料中；一覆蓋元件，位於該導電插塞和該封膠材料間之一頂部接點上方；及一介電層，位於該覆蓋元件上且位於該封膠材料上方。
  2. 如申請專利範圍第1項所述之半導體結構，其中該覆蓋元件沿著該封膠材料之頂部表面包括具有一長度的延伸部。
  3. 如申請專利範圍第1項所述之半導體結構，其中該覆蓋元件是一重分佈層(redistribution layer，RDL)。
  4. 如申請專利範圍第1項所述之半導體結構，其中該覆蓋元件是一圈形結構。
  5. 如申請專利範圍第4項所述之半導體結構，其中該覆蓋元件包括一內部邊緣和一外部邊緣，且該內部邊緣和該外部邊緣間的差距大於5μm。
  6. 如申請專利範圍第1項所述之半導體結構，更包括一空穴，位於該覆蓋元件之內部。
  7. 一種半導體三維封裝體，包括：一封膠材料；一填充導孔，位於該封膠材料中；一介電層，位於該封膠材料上；及一分隔元件，位於該封膠材料上，其中該分隔元件、該填充導孔和該封膠材料形成三方界面，且該分隔元件將該介 電層與該三方界面分開。
  8. 如申請專利範圍第7項所述之半導體三維封裝體，其中該分隔元件具有一熱膨脹係數，且該分隔元件之熱膨脹係數在該填充導孔之熱膨脹係數和該封膠材料之熱膨脹係數間。
  9. 如申請專利範圍第7項所述之半導體三維封裝體，其中該分隔元件沿著該填充導孔之軸向延伸。
  10. 如申請專利範圍第7項所述之半導體三維封裝體，其中該分隔元件是一圈形結構或一環形結構。
  11. 如申請專利範圍第7項所述之半導體三維封裝體，更包括一凸起部分，其中該凸起部分位於該填充導孔上，且位於該分隔元件下。
  12. 一種半導體結構之製作方法，包括：於一基底上形成一導電插塞；以一封膠材料包圍該導電插塞之側壁；及於一頂部接點上方設置一分隔元件，其中該頂部接點位於該封膠材料和該導電插塞間。
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