TWI832448B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI832448B
TWI832448B TW111136472A TW111136472A TWI832448B TW I832448 B TWI832448 B TW I832448B TW 111136472 A TW111136472 A TW 111136472A TW 111136472 A TW111136472 A TW 111136472A TW I832448 B TWI832448 B TW I832448B
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Taiwan
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density
low
inlay
bumps
semiconductor die
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TW111136472A
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TW202303780A (zh
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貝傑翰
杜旺朱
姚民
金陽瑞
張民華
金東和
喬阿拉
安韶珍
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美商艾馬克科技公司
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Abstract

一種半導體裝置包括低密度基板、位於所述低密度基板的空腔內的高密度嵌體、第一半導體晶粒和第二半導體晶粒。所述第一半導體晶粒包括高密度凸塊和低密度凸塊。所述第二半導體晶粒包括高密度凸塊和低密度凸塊。所述第一半導體晶粒的高密度凸塊和第二半導體晶粒的高密度凸塊電連接到所述高密度嵌體。所述第一半導體晶粒的低密度凸塊和所述第二半導體晶粒的低密度凸塊電連接到所述低密度基板。

Description

半導體裝置及其製造方法
本公開的各種實施例涉及一種半導體裝置及其製造方法。 相關申請案
本申請案主張於2017年1月23日在韓國知識產權局提交的韓國專利申請第10-2017-0010704號的優先權且獲得的所有益處，並且其內容透過引用整體併入本文。
半導體封裝保護積體電路或晶片免受物理損壞和外部應力。另外，半導體封裝可以提供熱傳導路徑以有效地移除晶片中產生的熱量，並且還提供到例如印刷電路板的其它部件的電連接。
通過將常規和傳統方法與具有本申請的其餘部分中提出的本公開的各態樣之這種系統進行比較，常規和傳統方法的限制和缺點對於本領域技術人士來說應該變得顯而易見。
本發明的一態樣是一種半導體裝置，包括：低密度基板；高密度嵌體，位於所述低密度基板中的空腔內；第一半導體晶粒，包括高密度凸塊和低密度凸塊；以及第二半導體晶粒，包括高密度凸塊和低密度凸塊，其中所述第一半導體晶粒的所述高密度凸塊和所述第二半導體晶粒的所述高密度凸塊電連接到所述高密度嵌體，並且所述第一半導體晶粒的所述低密度凸塊和所述第二半導體晶粒的所述低密度凸塊電連接到所述低密度基板。在所述半導體裝置中，所述高密度嵌體包括具有一個或多個高密度電路圖案和一個或多個介電層的高密度重新分佈結構；以及所述低密度基板包括具有一個或多個低密度電路圖案和一個或多個介電層的低密度重新分佈結構。在所述半導體裝置中，所述高密度電路圖案電連接到所述高密度凸塊；以及所述低密度電路圖案電連接到所述低密度凸塊。在所述半導體裝置中，所述高密度嵌體包括底板和所述底板上的高密度重新分佈結構；以及所述高密度重新分佈結構的一個或多個高密度電路圖案電連接到所述第一半導體晶粒和所述第二半導體晶粒的所述高密度凸塊。在所述半導體裝置中，所述高密度嵌體進一步包括插入在所述一個或多個高密度電路圖案和所述高密度凸塊之間的高密度襯墊。所述半導體裝置還包括圍繞所述高密度襯墊的底部填充物。在所述半導體裝置中，所述低密度基板包括：第一介電層；通過所述第一介電層的低密度柱；以及在所述第一介電層和所述低密度柱之下的低密度重新分佈結構；其中所述低密度柱被插入在所述低密度凸塊和所述低密度重新分佈結構的一個或多個低密度電路圖案之間。在所述半導體裝置中，所述低密度基板包括：第一介電層；通過所述第一介電層的低密度柱；以及在所述第一介電層和所述低密度柱之下的低密度重新分佈結構；其中所述低密度柱被插入在所述低密度凸塊和所述低密度重新分佈結構的一個或多個低密度電路圖案之間；以及其中所述高密度襯墊的頂表面和所述低密度柱的頂表面是共平面。在所述半導體裝置中，所述高密度襯墊的所述頂表面、所述低密度柱的所述頂表面和所述第一介電層的頂表面是共平面。在所述半導體裝置中，所述低密度重新分佈結構包括第二介電層；所述第一介電層和所述第二介電層包括樹脂；以及所述第一介電層包含比所述第二介電層更大量的無機填料。在所述半導體裝置中，所述低密度重新分佈結構包括第二介電層；所述第一介電層包含環氧模塑化合物；以及所述第二介電層包括比所述環氧模塑化合物更軟的樹脂。在所述半導體裝置中，所述高密度嵌體的底表面接觸所述低密度重新分佈結構的頂表面。在所述半導體裝置中，所述高密度嵌體的側表面接觸所述空腔的側表面。在所述半導體裝置中，所述第一半導體晶粒和所述第二半導體晶粒的所述高密度凸塊的高度以及所述第一半導體晶粒和所述第二半導體晶粒的所述低密度凸塊的高度相等。
本發明的另一態樣是一種半導體裝置的製造方法，包括：在第一載體上形成高密度襯墊和低密度柱；將高密度嵌體電連接到所述高密度襯墊；在所述高密度嵌體和所述低密度柱上方形成低密度基板，使得所述低密度基板的第一介電層圍繞所述低密度柱；去除所述第一載體以暴露所述高密度嵌體和所述低密度柱；以及將所述第一半導體晶粒和所述第二半導體晶粒電連接到所述高密度嵌體和所述低密度柱。在所述製造方法中，形成所述低密度基板包括在所述第一介電層上方形成低密度重新分佈結構，使得所述低密度重新分佈結構的一個或多個低密度電路圖案電連接到所述低密度柱。在所述製造方法中，形成所述低密度重新分佈結構包括形成一個或多個第二介電層，使得所述一個或多個第二介電層中的第二介電層位於所述一個或多個低密度電路圖案之上覆的低密度電路圖案和底下的低密度電路圖案之間。所述製造方法還包括：在所述低密度基板上形成傳導凸塊；藉由施加黏合劑至所述傳導凸塊而將第二載體黏附到所述低密度基板；以及在所述黏附動作之後去除所述第一載體。在所述製造方法中，電連接所述第一半導體晶粒和所述第二半導體晶粒包括：藉由電連接所述第一半導體晶粒的高密度凸塊和所述第二半導體晶粒的高密度凸塊至所述高密度嵌體，而將所述第一半導體晶粒電連接到所述第二半導體晶粒。在所述製造方法中，電連接所述第一半導體晶粒和所述第二半導體晶粒進一步包括將所述第一半導體晶粒的低密度凸塊和所述第二半導體晶粒的低密度凸塊電連接到所述低密度基板。
在下文中，參考附圖詳細描述優選示例實施例。本發明揭露的各個態樣可以許多不同的形式來實現，並且不應該被解釋為侷限於在此闡述的示例實施例。而是，提供本發明的這些示例實施例，以便使本揭露變得徹底和完整的，且向本領域技術人士傳達本發明揭露的各個態樣。
在附圖中，為了清楚起見，層和區域的厚度可能被誇大。本文中，相同的元件符號始終表示相同的元件。如本文所使用的，用語“及/或”包括一個或多個相關所列項目的任何和所有組合。還應理解的是，當元件A被稱為“連接到”元件B時，元件A可以直接連接到元件B，或者可以存在中間元件C以讓元件A和元件B間接地相互連接。
本文使用的用語僅用於描述特定實施例的目的，而不意圖限制本發明揭示。如本文所使用的，除非上下文另有明確指示，否則單數形式也意圖包括複數形式。將進一步理解的是，當在本說明書中使用時，用語“包括”及/或“包含”指出所述特徵、數字、步驟、操作、元件及/或組件的存在，但是不排除存在或添加一個或多個其他特徵、數字、步驟、操作、元件、組件和/或其組合。
應該理解的是，雖然這裡可以使用用語第一、第二等來描述各種構件、元件、區域、層及/或部分，但是這些構件、元件、區域、層及/或部分應該不受這些用語的限制。這些用語僅用於區分一個構件、元件、區域、層及/或部分與另一個構件、元件、區域、層及/或部分。因此，例如，下面討論的第一構件、第一元件、第一區域、第一層及/或第一部分可以被稱為第二構件、第二元件、第二區域、第二層及/或第二部分而不偏離本發明揭露的教導。
為了便於描述，可以在本文使用諸如“之下”、“下方”、“下面”、“之上”、“上方”等的空間相對用語來描述一個元件或特徵與另一個元素或特徵的關係，如圖所示。應該理解的是，空間相對用語旨在包含除了附圖中描繪的方位之外的裝置在使用或操作中的不同方位。例如，如果附圖中的裝置被翻轉，則被描述為在其他元件或特徵“下方”或“之下”的元件將被定向為在所述其他元件或特徵“之上”。因此，示例性用語“之下”可以涵蓋上方和下方的方位。所述裝置可以其他方式定向（旋轉90度或在其他方位），並且可以相應地解釋本文使用的空間相對描述符。
此外，於本文使用用語“共平面”和類似的用語來表示位於同一平面內的兩個表面。共平面可以彼此相鄰或鄰接；然而不相鄰及/或不鄰接的表面也可以是共平面的。例如，可以在共平面的表面之間插入間隙、空隙及/或其它結構。此外，由於製造公差、熱膨脹等，共平面的表面中可能存在輕微的偏差。這種偏差可能導致一個表面比另一個表面略高，從而在表面之間形成突然變化（step-off）（例如，升高或降低）。如本文使用的，用語“共平面”包括具有在0和7微米之間範圍內的突然變化的表面。
在整個說明書中，通常使用措辭“高密度”和“低密度”。用語“高密度”用來表示與“低密度”相比更精細的佈線間距或在組件的預定區域中與“低密度”相比更精細的佈線間距。用語“低密度”用來表示與“高密度”相比更大的佈線間距或在預定區域中與“高密度”相比更粗的佈線間距。因此，“高密度”和“低密度”這兩個術語被用作簡略表示以反映與第二區域（即，低密度區域）相比，第一區域（即，高密度區域）具有更多數量的佈線或其他注意到的結構，並且因此具有更高密度的佈線或其他結構。高密度區域中的結構相對於低密度區域的類似結構可以是更精細（即，更小或更窄）及/或可以更緊密地定位（即，結構之間更小的間隔）。因此，用語“高密度”和“低密度”表示關於特定半導體裝置的區域或結構的內部明確和一致的關係，但並不意圖暗示這樣的區域或結構相對於其他半導體裝置的類似區域或結構的密度程度。
根據本發明揭露的各種實施例，半導體裝置可以包括低密度基板、附接到所述低密度基板的高密度嵌體、包括高密度凸塊和低密度凸塊的第一半導體晶粒以及包括高密度凸塊和低密度凸塊的第二半導體晶粒。所述第一半導體晶粒的高密度凸塊和所述第二半導體晶粒的高密度凸塊可以電連接到所述高密度嵌體。所述第一半導體晶粒的低密度凸塊和所述第二半導體晶粒的低密度凸塊可以電連接到所述低密度基板。
所述高密度嵌體可以包括具有高密度電路圖案的高密度重新分佈結構。所述低密度基板可以包括具有低密度電路圖案的低密度重新分佈結構。所述高密度電路圖案可以電連接到所述高密度凸塊。所述低密度電路圖案可以電連接到所述低密度凸塊。
所述高密度嵌體還可以包括插入在所述高密度電路圖案和所述高密度凸塊之間的高密度襯墊。所述高密度襯墊可以被底部填充物包圍。
所述低密度基板可以包括第一介電層、穿過所述第一介電層的低密度柱以及在所述第一介電層和所述低密度柱之下的低密度重新分佈結構。所述低密度柱可以插入在所述第一和第二晶粒的低密度凸塊和所述低密度重新分佈結構的低密度電路圖案之間。所述高密度襯墊的頂表面和所述低密度柱的頂表面可以是共平面。而且，所述高密度襯墊的頂表面、所述低密度柱的頂表面和所述第一介電層的頂表面可以是共平面。
所述第一和第二介電層可以包括樹脂。所述第一介電層可以包括比所述低密度重新分佈結構的第二介電層更大量的無機填料。所述第一介電層可以包括環氧模塑化合物。
所述高密度嵌體的底表面可以接觸所述低密度重新分佈結構的頂表面。所述高密度嵌體可以被定位在所述第一介電層中的空腔內。所述高密度嵌體的側表面可以接觸在所述第一介電層中的空腔的側表面。
根據本發明揭露的各種實施例，半導體裝置的製造方法可以包括在第一載體上形成高密度襯墊和低密度柱，將高密度嵌體電連接到所述高密度襯墊，以及形成具有所述低密度柱嵌入於其中的低密度基板。所述方法可以進一步包括去除所述第一載體以暴露所述高密度嵌體和所述低密度柱。所述方法還可以包括將所述第一半導體晶粒和所述第二半導體晶粒電連接到經暴露的所述高密度嵌體和低密度柱，以透過所述高密度嵌體將所述第一和第二半導體晶粒彼此電連接。
所述低密度基板可以透過用第一介電層覆蓋所述低密度柱並在所述第一介電層上形成低密度重新分佈結構以將所述重新分佈結構的低密度電路圖案電連接到所述第一介電層中的所述低密度柱來形成。
所述低密度重新分佈結構可以覆蓋所述高密度嵌體。可以在所述低密度基板上形成傳導凸塊，並且透過向所述傳導凸塊施加黏合劑以將第二載體黏附到所述低密度基板之後，所述第一載體可被去除。
所述第一半導體晶粒可以包括高密度凸塊和低密度凸塊，所述第二半導體晶粒可以包括高密度凸塊和低密度凸塊，並且所述第一半導體晶粒的高密度凸塊和所述第二半導體晶粒的高密度凸塊可以電連接到所述高密度嵌體。所述第一半導體晶粒的低密度凸塊和所述第二半導體晶粒的低密度凸塊可以電連接到所述低密度基板。
如上所述，根據本發明揭露的各種實施例，所述第一半導體晶粒的高密度凸塊和所述第二半導體晶粒的高密度凸塊可以經由所述高密度嵌體彼此電連接。而且，所述第一半導體晶粒的低密度凸塊和所述第二半導體晶粒的低密度凸塊可以電連接到所述低密度基板，由此允許第一和第二半導體晶粒的高密度凸塊透過具有高佈線密度的所述高密度嵌體而容易地彼此電連接，但不增加所述低密度基板的佈線密度。
此外，在本發明揭露的各種實施例中，經歷佈線測試之後的所述高密度嵌體可以電連接到對應於所述第一和第二半導體晶粒的高密度凸塊的區域。這種先測試和隨後的互連可以提高所述第一和第二半導體晶粒的電連接的可靠性，並降低半導體封裝成本。
參考圖1A和圖1B，圖示了根據本發明揭露的各種實施例的半導體裝置100的橫截面圖和局部放大的橫截面圖。如圖所示，參考圖1A和1B，半導體裝置100可以包括低密度基板110和高密度嵌體120。另外，半導體裝置100可以進一步包括附著到低密度基板110的傳導凸塊130。半導體裝置100可以進一步包括第一半導體晶粒141及/或第二半導體晶粒144。半導體裝置100還可以包括囊封第一半導體晶粒141及/或第二半導體晶粒144的囊封物160。
低密度基板110可以包括多個低密度柱111和第一介電層112。多個低密度柱111可以水平地佈置，使得多個低密度柱彼此分隔預定距離。所述多個低密度柱可以被第一介電層112圍繞。特別地，多個低密度柱111可以被配置為基本上垂直穿透第一介電層112，並且第一介電層112可以被配置成具有平坦的頂表面和平坦的底表面。換句話說，低密度柱111的頂表面可與第一介電層112的頂表面共平面，而低密度柱111的底表面可與第一介電層112的底表面共平面。此外，第一介電層112還可以包括具有足以接收高密度嵌體120的預定深度和寬度之空腔112c。在一些實施例中，空腔112c可以大致定位在第一介電層112的中心。
低密度柱111可以包括透過一般鍍銅製程形成的銅柱或銅桿。第一介電層112可以包括在一般的模製或囊封製程中使用的環氧模塑化合物或環氧模塑樹脂。在一些實施例中，第一介電層112可以包括相對大量的無機填料以獲得相對高的硬度。因此，第一介電層112可以用作低密度基板110的核心。除了銅之外，低密度柱111可以包括金、銀、鎳、鈀及這些元素的任何其他合適的合金。
另外，低密度基板110可以包括低密度重新分佈結構116。所述低密度重新分佈結構可以包括一個或多個低密度電路圖案113和一個或多個第二介電層114。低密度電路圖案113可以水平地佈置，使得多個低密度電路圖案113彼此間隔開預定距離。
具體而言，一個或多個低密度電路圖案113可以被配置為基本上垂直地穿透一個或多個第二介電層114。一個或多個第二介電層114可以被配置成提供低密度重新分佈結構116的平坦頂表面和平坦底表面。特別地，一個或多個低密度電路圖案113之最上層的低密度電路圖案113的頂表面可以與所述一個或多個第二介電層之最上層的第二介電層114的頂表面共平面。同樣地，一個或多個低密度電路圖案113之最下層的低密度電路圖案113的底表面可以與一個或多個第二介電層114之最下層的第二介電層114的底表面共平面。
一個或多個低密度電路圖案113和一個或多個第二介電層114可以被配置成阻擋空腔112c的底部。為此，低密度重新分佈結構116的一個或多個低密度電路圖案113和一個或多個第二介電層114可以透過一般的無芯積層(coreless build-up)製程形成。特別地，一個或多個低密度電路圖案113和一個或多個第二介電層114可以提供低密度重新分佈結構116的多層結構或層壓結構。第二介電層114可以位於上覆的低密度電路圖案113和底下的低密度電路圖案113之間。穿過居間的第二介電層114的傳導通孔可以將上覆的低密度電路圖案113電連接到底下的低密度電路圖案113。
在一些實施例中，低密度電路圖案113可以包括透過一般鍍銅製程形成的銅電路圖案或跡線。在其他實施例中，除了銅之外，低密度電路圖案113可以包括金、銀、鎳、鈀以及這些元素的任何其它合適的合金。
低密度柱111可以電連接到低密度電路圖案113。此外，第一介電層112和低密度重新分佈結構116可以彼此黏著。
第二介電層114可以包括聚醯亞胺（PI）、苯環丁烯（benzocyclobutane，BCB）、聚苯並噁唑（polybezo oxazole，PBO）、雙馬來醯亞胺-三氮雜苯（bismaleimide triazine，BT）、酚醛樹脂或環氧樹脂。在一些實施例中，第二介電層114可以不包括無機填料或比第一介電層112更少量的無機填料。無機填料含量的這種差異可以賦予第二介電層114比第一介電層112較低的硬度。第二介電層114的較低的硬度或軟度可有助於防止下文所述的傳導凸塊130發生裂紋。
同時，低密度柱111和低密度電路圖案113（包括傳導通孔）的線/間距/寬度可以在從約40μm到約100μm的範圍內。
高密度嵌體120可以被附接到低密度基板110。在示例實施例中，高密度嵌體120可以被定位在低密度基板110中提供的空腔112c中。高密度嵌體120的厚度可以基本上等於或類似於空腔112c的深度。因此，高密度嵌體120可以被牢固地安裝在低密度基板110上，使得低密度基板110的厚度和及/或半導體裝置100的厚度不增加以容納高密度嵌體120。
另外，高密度嵌體120可以在耦合到第一介電層112的空腔112c的同時附著到低密度重新分佈結構116。換句話說，高密度嵌體120的底表面可以接觸低密度重新分佈結構116的頂表面。高密度嵌體120的側表面可以接觸設置在第一介電層112中的空腔112c的側表面。
高密度嵌體120可以包括底板121和在底板121上的高密度重新分佈結構126。在示例實施例中，底板121可以包括矽玻璃或陶瓷。底板121的底表面可以基本上附著於低密度重新分佈結構116的頂表面。
在一些實施例中，高密度重新分佈結構126可以提供一個或多個高密度電路圖案122以及一個或多個介電層123的多層結構。一個或多個高密度電路圖案122可以包括透過一般鍍銅製程形成的一個或多個銅電路圖案或跡線。在其它實施例中，除了銅之外，一個或多個高密度電路圖案122可以包括金、銀、鎳、鈀以及這些元素的任何其他合適的合金。
在一些實施例中，一個或多個介電層123可以包括聚醯亞胺（PI）、苯環丁烯（BCB）、聚苯並噁唑（PBO）、雙馬來醯亞胺-三氮雜苯（BT）、酚醛樹脂或環氧樹脂。在其他實施例中，一個或多個介電層123可以包括具有高介電常數的SiO 2、Si 3N 4、Al 2O 3、Ta 2O 5、TiO 2、ZrO 2或HFO 2。
高密度重新分佈結構126的一個或多個高密度電路圖案122和一個或多個介電層123可以透過一般的無芯積層製程形成。特別地，一個或多個高密度電路圖案122和一個或多個介電層123可以提供高密度重新分佈結構126的多層結構或層壓結構。介電層123可以位於上覆的高密度電路圖案122和底下的高密度電路圖案122之間。穿過居間的介電層123的傳導通孔可以將上覆的高密度電路圖案122電連接到底下的高密度電路圖案122。
高密度嵌體120還可以包括電連接到高密度電路圖案122的高密度襯墊124。高密度襯墊124可以透過銅、金、銀、鎳、鈀或這些元素的任何其他合適的合金之一般的鍍覆製程來形成。另外，高密度襯墊124可被底部填充物125覆蓋。同時，高密度電路圖案122和高密度襯墊124的線/間距/寬度可在約0.1μm至約40μm的範圍內。因此，高密度嵌體120可以具有比低密度基板110更高的佈線密度。
另外，低密度柱111的頂表面和高密度襯墊124的頂表面可以是共平面。特別地，低密度柱111的頂表面、第一介電層112的頂表面以及高密度襯墊124的頂表面可以是共平面。更詳細地，低密度柱111的頂表面、第一介電層112的頂表面、高密度襯墊124的頂表面以及底部填充物125的頂表面可以是共平面。
傳導凸塊130可以電連接到低密度電路圖案113，所述低密度電路圖案113通過低密度基板110的底表面而暴露。例如，傳導凸塊130可以由共晶焊料（Sn37Pb）、高鉛焊料（Sn95Pb）和無鉛焊料（SnAg、SnAu、SnCu、SnZn、SnZnBi、SnAgCu、SnAgBi等）及其等效物。傳導凸塊130，如圖1A和1B所示，可以成形為球形。或者，儘管未圖示，但傳導凸塊130可以被形成為扁平的連接盤（land）。
在一些實施例中，第一半導體晶粒141和第二半導體晶粒144具有基本上相同或相似的結構。因此，第一半導體晶粒141和第二半導體晶粒144是被一起描述。
第一和第二半導體晶粒141和144可以水平地佈置並且可以電連接到低密度基板110和高密度嵌體120。雖然圖1A圖示了在高密度嵌體120周圍水平地佈置的兩個半導體晶粒141和144，但是當從上方觀看時，三個、四個或者可能更多的半導體晶粒可以水平地佈置在高密度嵌體120周圍。在這樣的實施例中，可以在靠近高密度嵌體120的每個半導體晶粒的拐角處及/或邊緣處形成晶粒的高密度凸塊。這樣的高密度凸塊可以將個別的半導體晶粒連接到高密度嵌體120，如下所述。
第一和第二半導體晶粒141和144可以分別包括多個低密度凸塊142和145以及多個高密度凸塊143和146。如圖所示，第一半導體晶粒141和第二半導體晶粒144的低密度凸塊142和145可形成在遠離高密度嵌體120的一個或多個區域處，並且第一半導體晶粒141和第二半導體晶粒144的高密度凸塊143和146可形成在接近高密度嵌體120的區域處。如進一步所示，當第一半導體晶粒141和第二半導體晶粒144被定位成使得它們各自的高密度凸塊143和146彼此接近，則第一半導體晶粒141和第二半導體晶粒144的低密度凸塊142和145可以彼此遠離地定位。
在一個示例性實施例中，低密度凸塊142和145以及高密度凸塊143和146可以包括具有焊帽的銅柱或銅桿。在另一個示例實施例中，低密度凸塊142和145可以包括焊料凸塊，並且高密度凸塊143和146可以包括銅柱，其提供比所述焊料凸塊更精細的間距。在又一示例實施例中，低密度凸塊142和145以及高密度凸塊143和146可以包括焊料凸塊。
同時，第一半導體晶粒141和第二半導體晶粒144的低密度凸塊142和145可以電連接到低密度基板110的低密度電路圖案113。特別地，低密度凸塊142和145可以經由低密度柱111電連接到低密度電路圖案113。類似地，第一和第二半導體晶粒141和144的高密度凸塊143和146可以電連接到高密度嵌體120的高密度電路圖案122。更具體地，高密度凸塊143和146可以經由高密度襯墊124電連接到高密度電路圖案122。
因此，第一和第二半導體晶粒141和144的低密度凸塊142和145可以分別電連接到低密度基板110。這樣，低密度凸塊142和145可以電連接到設置在低密度基板110的底表面上的傳導凸塊130。此外，第一和第二半導體晶粒141和144的高密度凸塊143和146可以經由高密度嵌體120彼此電連接，而不經由低密度基板110電佈線。
本文中，第一半導體晶粒141和第二半導體晶粒144可以分別包括與半導體晶圓分離的積體電路晶粒，並且可以包括例如電子電路，諸如數位信號處理器（DSP）、網絡處理器、電力管理單元、音頻處理器、RF電路、無線基頻系統單晶片（SOC）處理器、感測器或特定應用積體電路。
在一些實施例中，囊封物160可以將第一和第二半導體晶粒141和144完全囊封在低密度基板110上，以保護第一和第二半導體晶粒141和144免受外部環境的影響。在其他實施例中，第一和第二半導體晶粒141和144的頂表面可以通過囊封物160而保持暴露於外部，以改善第一和第二半導體晶粒141和144的散熱效率。在一些實施例中，底部填充物150可以進一步填充第一和第二半導體晶粒141和144與低密度基板110之間的間隙或空間。因此，囊封物160不僅可以覆蓋第一半導體晶粒141和第二半導體晶粒144而且也覆蓋底部填充物150。囊封物160可包含環氧模塑化合物、環氧模塑樹脂及其等效物。在一些實施例中，囊封物160可以包括與用於形成第一介電層112的材料相同的材料。
因此，根據本發明揭露的各種實施例，半導體裝置100可以包括低密度基板110和高密度嵌體120。具體地，在本發明揭露的各種實施例中，第一半導體晶粒141的高密度凸塊143和第二半導體晶粒144的高密度凸塊146可以透過高密度嵌體120彼此電連接。然而，第一半導體晶粒141的低密度凸塊142和第二半導體晶粒144的低密度凸塊145可以電連接到低密度基板110。因此，第一和第二半導體晶粒141和144的高密度凸塊143可以透過具有高佈線密度的高密度嵌體120彼此電連接，而不增加低密度基板110的佈線密度。
而且，在本發明揭露的各種實施例中，只有在成功完成佈線測試之後，高密度嵌體120才可以電連接到與第一半導體晶粒141和第二半導體晶粒144的高密度凸塊143和146對應的區域。以這種方式，可以改善第一半導體晶粒141和第二半導體晶粒144的電連接的可靠性，並且可以降低半導體封裝成本。
參考圖2A至2J，提供了示出根據本發明揭露的各種實施例的半導體裝置的製造方法的橫截面圖。如圖2A所示，低密度柱111和高密度襯墊124可形成在具有平坦頂表面和平坦底表面的第一載體171上。第一載體171可以包括矽、玻璃或金屬。
在一個示例性實施例中，低密度柱111可以形成為圍繞第一載體171的外圍區域的群組。相反地，高密度襯墊124可以形成為第一載體171的中心區域內的群組。此外，低密度柱111和高密度襯墊可以形成為使得低密度柱111具有比高密度襯墊124更大的線/間隔/寬度。因此，低密度柱111可以比高密度襯墊124更大（例如，更大的寬度）及/或具有更大的間距（例如，柱之間的更大的分離），因此導致柱111的密度（即，每單位面積之柱111的數量）低於其相應區域中的襯墊124的密度（即，每單位面積之襯墊124的數量）。
可以透過電鍍、無電電鍍、濺射、物理氣相沉積（PVD）或化學氣相沉積（CVD）來形成低密度柱111及/或高密度襯墊124。在一些實施例中，低密度柱111和高密度襯墊124可以透過低成本電鍍來形成。
如圖2B所示，高密度嵌體120可以電連接到高密度襯墊124。高密度嵌體120可以包括底板121、介電層123和高密度電路圖案122。特別地，高密度電路圖案122可以電連接到高密度襯墊124。在示例實施例中，高密度電路圖案122可以透過熱壓接合方法而電連接到高密度襯墊124。在另一示例性實施例中，高密度電路圖案122可以透過諸如焊料的傳導膏、各向異性傳導膜或各向異性傳導漿糊而電連接到高密度襯墊124。另外，可以施加底部填充物125以填充高密度嵌體120和第一載體171之間的間隙、圍繞高密度襯墊124且將高密度嵌體120固定到第一載體171。
如圖2C所示，低密度柱111可以被第一介電層112覆蓋。在一個示例實施例中，第一介電層112可以包括環氧模塑化合物或環氧模塑樹脂。因此，設置在第一載體171上的低密度柱111可以透過一般的分配、模製、壓縮模製或轉移模塑而被第一介電層112包圍。特別地，第一介電層112可以形成為具有足以覆蓋低密度柱111的側表面和頂表面以及高密度嵌體120的側表面和頂表面之厚度。在這樣的實施例中，第一介電層112的頂表面可透過機械研磨或化學蝕刻來移除。在一些實施例中，不僅第一介電層112的頂表面，而且高密度嵌體120的頂表面和低密度柱111的頂表面都可以經歷研磨及/或蝕刻。在這樣的研磨或蝕刻之後，低密度柱111的頂表面、高密度嵌體120的頂表面（例如，底板121的頂表面）可以與第二介電層114的頂表面共平面。
如圖2D所示，低密度基板110可以透過在低密度柱111、第一介電層112和高密度嵌體120上方形成低密度重新分佈結構116來完成。如圖所示，低密度重新分佈結構116可以包括一個或多個低密度電路圖案113和一個或多個第二介電層114。一個或多個低密度電路圖案113和一個或多個第二介電層114可以透過一般的無芯積層製程而形成在低密度柱111、第一介電層112和高密度嵌體120上。特別地，一個或多個低密度電路圖案113和一個或多個第二介電層114可以提供低密度重新分佈結構116的多層結構或層壓結構。第二介電層114可以位於上覆的低密度電路圖案113和底下的低密度電路圖案113之間。穿過居間的第二介電層114的傳導通孔可以將上覆的低密度電路圖案113電連接到底下的低密度電路圖案113。
作為上述製程的結果，低密度重新分佈結構116可以被黏著到第一介電層112，並且低密度重新分佈結構116的低密度電路圖案113可以被電連接到低密度柱111。第二介電層114可以透過一般的旋塗、印刷、噴塗、燒結、熱氧化、物理氣相沉積（PVD）、化學氣相沉積（CVD）或原子層沉積（ALD）來形成。低密度電路圖案113可以透過一般的電鍍、無電電鍍、濺射、物理氣相沉積（PVD）或化學氣相沉積（CVD）來形成。
如上所述，低密度柱111的頂表面，第一介電層112的頂表面和高密度嵌體120的頂表面可以是共平面。由於是在這樣的頂表面上形成，所以第二介電層114的頂表面和低密度電路圖案113的頂表面也可以是共平面。此外，低密度電路圖案113的頂表面可以經由第二介電層114的頂表面暴露到外部。
值得注意的是，高密度嵌體120的頂表面可以被低密度重新分佈結構116的低密度電路圖案113和第二介電層114覆蓋。特別地，高密度嵌體120可以被配置為嵌入在低密度基板110中，使得低密度基板110的厚度基本上不會因高密度嵌體120而增加。
如圖2E所示，傳導凸塊130可以形成在低密度基板110的低密度重新分佈結構116的頂表面上。在示例實施例中，傳導凸塊130可以透過一般的大規模回焊製程或雷射輔助接合製程而電連接到低密度基板110的低密度電路圖案113。另外，傳導凸塊130可以被成形為圓球，如圖2E所示，或扁平的連接盤。
參考圖2F，可以使用臨時黏合劑172將第二載體173黏附到低密度基板110。具體地，可以在臨時黏合劑172覆蓋傳導凸塊130的同時將臨時黏合劑172施加到低密度基板110上。第二載體173可以定位在臨時黏合劑172上以黏附到低密度基板110。臨時黏合劑172可以包括黏合劑，其在熱、光或化學溶液的存在下失去它的黏合性。另外，第二載體173可以包括矽、玻璃、陶瓷或金屬。
如圖2G所示，可移除第一載體171以暴露低密度基板110的底表面及高密度嵌體120的底表面。特別地，第一載體171可以透過一般機械研磨、化學蝕刻或物理剝離來移除。因此，在低密度基板110中，低密度柱111的底表面和第一介電層112的底表面可以暴露於外部。另外，在高密度嵌體120中，高密度襯墊124的底表面和底部填充物125的底表面可以暴露於外部。低密度柱111的底表面、第一介電層112的底表面、高密度襯墊124的底表面及/或底部填充物125的底表面可以是共平面。
如圖2H所示，第一和第二半導體晶粒141和144可以電連接到低密度基板110和高密度嵌體120。特別地，第一和第二半導體晶粒141和144可以分別包括低密度凸塊142以及高密度凸塊143和146。低密度凸塊142和145可以電連接到低密度基板110的低密度電路圖案113，並且高密度凸塊143和146可以電連接到高密度嵌體120的高密度電路圖案122。特別地，低密度凸塊142和145可以經由低密度柱111電連接到低密度電路圖案113。高密度凸塊143和146可以經由高密度襯墊124電連接到高密度電路圖案122。
由於低密度柱111的頂表面、第一介電層112的頂表面、高密度襯墊124的頂表面及/或底部填充物125的頂表面全部是共平面，低密度凸塊142和145以及高密度凸塊143和146的高度或厚度可以全部相等。此外，低密度凸塊142和145的底表面和高密度凸塊143和146的底表面可以共平面。因此，除了低密度凸塊142和145與高密度凸塊143和146之間的線/間隔/寬度的差異之外，就高度或厚度而言，低密度凸塊142和145以及高密度凸塊143和146可以彼此基本上彼此相同。
這種配置可以增加第一半導體晶粒141和第二半導體晶粒144的可管理性。特別地，在第一半導體晶粒141和第二半導體晶粒144的熱壓縮製程或大規模回焊製程期間，第一半導體晶粒141和第二半導體晶粒144可以在預定時間內被暫時性安全地定位在低密度基板110和高密度嵌體124上。在這樣的定位之後，第一半導體晶粒141和第二半導體晶粒144可以透過一般的熱壓接合製程或大規模回焊製程而電連接且固定到低密度基板110和高密度嵌體120。
如圖2I所示，可以施加底部填充物150來填充第一半導體晶粒141和第二半導體晶粒144中的每一個、低密度基板110和高密度嵌體120之間的間隙。特別地，底部填充物150可以填充在第一和第二半導體晶粒141和144與低密度基板110之間的間隙或空間、在第一和第二半導體晶粒141和144與高密度嵌體120之間的間隙或空間以及在第一和第二半導體晶粒141和144之間的間隙或空間。這樣的填充可以將第一和第二半導體晶粒141和144、低密度基板110和高密度嵌體120彼此機械地耦合。在一些實施例中，可以跳過施加底部填充物150的製程。
在圖2J中所示，第一半導體晶粒141和第二半導體晶粒144可以被囊封物160囊封。囊封物160可以覆蓋設置在低密度基板110上的第一半導體晶粒141和第二半導體晶粒144的側表面和頂表面。在一些實施例中，囊封物160可以僅覆蓋第一半導體晶粒141和第二半導體晶粒144的側表面，從而允許第一半導體晶粒141和第二半導體晶粒144的頂表面暴露於外部。當囊封物160的無機填料小於在第一和第二半導體晶粒141和144與低密度基板110之間的間隙尺寸時，囊封物160可以直接填充在第一和第二半導體晶粒141和144與低密度基板110之間的間隙，而不使用底部填充物150。
在完成製造製程之後，可移除第二載體173和臨時黏合劑172以將附接到低密度基板110的傳導凸塊130暴露於外部。另外，由於此製造製程可以形成水平及/或垂直排列的數個半導體裝置100，所以在製造製程結束時可以緊接著鋸切或單一化切割成各個半導體裝置100。為此，可以使用鑽石刀或雷射束將低密度基板110和囊封物160鋸切或單一化切割，從而導致低密度基板110的側表面與囊封物160的側表面共平面。
本發明的揭示包括對某些示例實施例的引用，然而，本領域技術人士將理解的是，在不脫離本發明揭露的範圍的情況下可以進行各種改變並且可以替換等效物。另外，在不脫離本發明揭露的範圍的情況下，可以對所揭露的示例實施例進行修改。因此，這意謂著本發明的揭示不限於所揭露的示例實施例。
100:半導體裝置 110:低密度基板 111:低密度柱 112:第一介電層 112c:空腔 113:低密度電路圖案 114:第二介電層 116:低密度重新分佈結構 120:高密度嵌體 121:底板 122:高密度電路圖案 123:介電層 124:高密度襯墊/襯墊 125:底部填充物 126:高密度重新分佈結構 130:傳導凸塊 141:第一半導體晶粒/半導體晶粒 142:低密度凸塊 143:高密度凸塊 144:第二半導體晶粒/半導體晶粒 145:低密度凸塊 146:高密度凸塊 150:底部填充物 160:囊封物 171:第一載體 172:臨時黏合劑 173:第二載體
[圖1A和1B]示出了根據本發明揭露的各種實施例的半導體裝置的截面圖和局部放大的截面圖。
[圖2A]至[圖2J]示出了圖示根據本發明揭露的各種實施例的半導體裝置的製造方法的截面圖。
100:半導體裝置
110:低密度基板
111:低密度柱
112:第一介電層
112c:空腔
113:低密度電路圖案
114:第二介電層
116:低密度重新分佈結構
120:高密度嵌體
121:底板
122:高密度電路圖案
130:傳導凸塊
141:第一半導體晶粒/半導體晶粒
142:低密度凸塊
143:高密度凸塊
144:第二半導體晶粒/半導體晶粒
145:低密度凸塊
146:高密度凸塊
150:底部填充物
160:囊封物

Claims (15)

  1. 一種半導體裝置，包括：低密度基板，包括：第一介電材料；低密度導電通孔，大致上垂直延伸穿過所述第一介電材料；以及空腔，在所述第一介電材料中；高密度嵌體，完全位於所述第一介電材料中的所述空腔內，所述高密度嵌體包括頂部嵌體側、未被所述第一介電材料覆蓋的底部嵌體側以及在所述頂部嵌體側和所述底部嵌體側之間延伸的橫向嵌體側；第一半導體晶粒，包括高密度凸塊和低密度凸塊；以及第二半導體晶粒，包括高密度凸塊和低密度凸塊，其中：所述第一半導體晶粒的所述高密度凸塊和所述第二半導體晶粒的所述高密度凸塊電連接至所述高密度嵌體；所述第一半導體晶粒的所述低密度凸塊和所述第二半導體晶粒的所述低密度凸塊電連接至所述低密度基板；以及所述低密度導電通孔中的每一個包括垂直跨越整個所述高密度嵌體的金屬柱。
  2. 如請求項1的半導體裝置，其中所述第一介電材料包括與所述底部嵌體側基本上共平面的底側。
  3. 如請求項1的半導體裝置，其中：所述高密度嵌體包括在所述頂部嵌體側處的高密度互連；以及所述高密度互連中的每一個包括未被所述第一介電材料覆蓋的頂表面。
  4. 如請求項3的半導體裝置，其中整個所述頂部嵌體側未被所述第 一介電材料覆蓋。
  5. 如請求項1的半導體裝置，其中：所述第一介電材料包括橫向界定所述空腔的內壁；以及所述高密度嵌體接觸所述內壁中的每一個。
  6. 如請求項1的半導體裝置，包括在所述高密度嵌體上的黏合材料，所述黏合材料與所述第一介電材料不同，整個所述黏著材料是在所述空腔中。
  7. 一種半導體裝置，包括：低密度基板，包括：第一介電材料；低密度導電通孔，大致上垂直延伸穿過所述第一介電材料，其中所述低密度導電通孔中的每一個包括相應的上平坦表面；以及空腔，在所述第一介電材料中；高密度嵌體，完全位於所述第一介電材料中的所述空腔內，所述高密度嵌體包括：頂部嵌體側、底部嵌體側以及在所述頂部嵌體側和所述底部嵌體側之間延伸的橫向嵌體側；互連結構，在所述頂部嵌體側處，其中所述互連結構中的每一個包括與所述低密度導電通孔的所述上平坦表面共平面之相應的上平坦表面；第一半導體晶粒，包括高密度凸塊和低密度凸塊；以及第二半導體晶粒，包括高密度凸塊和低密度凸塊，其中：所述第一半導體晶粒的所述高密度凸塊和所述第二半導體晶粒的所述高密度凸塊電連接至所述高密度嵌體；以及 所述第一半導體晶粒的所述低密度凸塊和所述第二半導體晶粒的所述低密度凸塊電連接至所述低密度基板。
  8. 如請求項7的半導體裝置，其中所述第一介電材料包括與所述互連結構的所述上平坦表面共平面的頂表面。
  9. 如請求項7的半導體裝置，其包括在所述頂部嵌體側上的第二介電材料，其中所述第二介電材料接觸且橫向圍繞所述互連結構中的每一個。
  10. 如請求項9的半導體裝置，其中所述第二介電材料不同於所述第一介電材料。
  11. 如請求項9的半導體裝置，其中整個所述第二介電材料是在所述空腔內。
  12. 如請求項9的半導體裝置，其中所述第一介電材料接觸且橫向圍繞所述第二介電材料。
  13. 如請求項7的半導體裝置，其中所述第一介電材料接觸所述橫向嵌體側。
  14. 如請求項13的半導體裝置，其中所述第一介電材料橫向跨越整個所述第一半導體晶粒和整個所述第二半導體晶粒。
  15. 如請求項7的半導體裝置，其中所述第一介電材料和所述低密度導電通孔垂直跨越所述高密度嵌體。
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