TWI703680B - 半導體封裝件及其形成方法 - Google Patents

半導體封裝件及其形成方法 Download PDF

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TWI703680B
TWI703680B TW107118118A TW107118118A TWI703680B TW I703680 B TWI703680 B TW I703680B TW 107118118 A TW107118118 A TW 107118118A TW 107118118 A TW107118118 A TW 107118118A TW I703680 B TWI703680 B TW I703680B
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Taiwan
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die
opening
molding material
rewiring
side wall
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TW107118118A
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TW201926585A (zh
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黃立賢
蘇安治
葉德強
林岳霆
葉名世
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台灣積體電路製造股份有限公司
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Abstract

一種形成半導體封裝件的方法，包含：將第一晶粒及第二晶粒貼合至載體；在第一晶粒與第二晶粒之間形成模製材料；以及在第一晶粒、第二晶粒以及模製材料上方形成重佈線結構，重佈線結構包含：第一重佈線區域；第二重佈線區域；以及第一重佈線區域與第二重佈線區域之間的切割區域。方法更包含：在切割區域中形成第一開口及第二開口，第一開口及第二開口延伸穿過重佈線結構且暴露模製材料；以及藉由自模製材料之第二側朝向模製材料之第一側切割與切割區域對準的模製材料之一部分來分離第一晶粒及第二晶粒，第二側與第一側相對。

Description

半導體封裝件及其形成方法
本發明的實施例是有關於半導體封裝件及其形成方法。
半導體行業歸因於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)之積體密度的持續改良已經歷快速增長。一般地，整合密度之此改良來自最小特徵大小之逐漸減小，此允許將更多的組件整合於給定區域中。由於最近對甚至更小的電子裝置之要求已增長，因此需要半導體晶粒之更小及更具創造性的封裝技術。
此等封裝技術之實例為疊層封裝(Package-on-Package；POP)技術。在PoP封裝中，頂部半導體封裝件堆疊於底部半導體封裝件之頂部上，以允許較高積體水平以及組件密度。另一實例為多晶片模組(Multi-Chip-Module；MCM)技術，其中多個半導體晶粒封裝於一個半導體封裝件中，以提供具有積體功能之半導體裝置。
高級封裝技術之較高積體水平能夠產生具有增強型功能及較小佔據面積的半導體裝置，此有利於諸如移動電話、平板電 腦以及數位音樂播放器之較小形式因子的裝置。另一優點為連接半導體封裝件內之互操作部件的導電路徑之縮短的長度。此改良半導體裝置之電學效能，此是由於電路之間的更短互連佈線產生更快信號傳播及減小之雜訊及串擾。
本發明實施例的一種形成半導體封裝件的方法，包括：將第一晶粒及第二晶粒貼合至載體；在第一晶粒與第二晶粒之間形成模製材料；以及在第一晶粒、第二晶粒以及模製材料上方形成重佈線結構，重佈線結構包括：第一晶粒上方之第一重佈線區域；第二晶粒上方之第二重佈線區域；以及第一重佈線區域與第二重佈線區域之間的切割區域。所述方法更包括：在切割區域中形成第一開口及第二開口，第一開口及第二開口延伸穿過重佈線結構且暴露模製材料之第一側；以及藉由切割與切割區域對準的模製材料之一部分以將第一晶粒及第二晶粒分離，其中自模製材料之第二側朝向模製材料之第一側執行切割，第二側與第一側相對。
本發明實施例的一種形成半導體封裝件的方法，包括：在載體之第一側上方形成第一導電柱及第二導電柱；將第一晶粒及第二晶粒貼合至載體之第一側，第一晶粒及第二晶粒分別鄰近於第一導電柱及第二導電柱；在載體之第一側上方形成模製材料，模製材料沿第一晶粒之側壁、第二晶粒之側壁、第一導電柱之側壁以及第二導電柱之側壁延伸；在第一晶粒、第二晶粒以及模製材料上方形成重佈線結構，重佈線結構包括第一晶粒上方之 第一重佈線區域、第二晶粒上方之第二重佈線區域以及第一重佈線區域與第二重佈線區域之間的切割區域；移除切割區域中之重佈線結構之部分以形成鄰近第一晶粒的第一開口及鄰近第二晶粒之第二開口，第一開口藉由切割區域中之重佈線結構的剩餘部分而與第二開口分離；剝離載體；將第一半導體封裝件電性耦接至第一導電柱；將第二半導體封裝件電性耦接至第二導電柱；以及自第一晶粒之背面使用刀片切割模製材料，所述切割將第一晶粒與第二晶粒分離。
本發明實施例的一種半導體封裝件，包括下部封裝件。下部封裝件包括晶粒、鄰近晶粒之導電柱以及模製材料。晶粒及導電柱在重佈線結構上方。模製材料在重佈線結構上方，模製材料插入於晶粒與導電柱之間，模製材料延伸超出重佈線結構之側向範圍。
100、200、300:區域
101:載體
110、142、144、146、148:介電層
116、311、311'、313、313':開口
118:黏著膜
119:導電柱
120、162:半導體晶粒
121:元件
126:墊
127:鈍化膜
128:晶粒連接件
129:介電材料
130、165:模製材料
130L:下部表面
130S1、130S2、311E、313E:側壁
140、140':重佈線結構
140R:剩餘部分
143:導線
145:通孔
147:凸塊下金屬化結構
155:連接件
157:框架
159:載帶
160、160A、160B:頂部封裝件
161:基底
163:導電墊
167:接線
168、173:導電接合點
169、175:底填充材料
171:電氣裝置
315:刀片
500、500A、500B:半導體封裝件
1100、1100A、1100B、1100C、1100D、1100E、1100F:底部封裝件/半導體封裝件
3000:方法
3010、3020、3030、3040、3050:步驟
H1、H2:高度
W1、W1'、W2、W3、W4、W5:寬度
當結合附圖閱讀時，自以下實施方式最佳地理解本揭露內容之態樣。應注意，根據行業中之標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見，而任意地增加或縮減各種特徵之尺寸。
圖1至圖6、圖7A、圖7B以及圖8至圖11繪示根據一實施例的在各個製造階段處之半導體封裝件之各種視圖。
圖12繪示根據一些實施例的用於形成半導體封裝件之方法的流程圖。
以下揭露內容提供用於實施本發明之不同特徵的許多不同實施例或實例。下文描述組件及配置之特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上之形成可包含第一特徵以及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。
另外，諸如“在...下方”、“在...下面”、“下部”、“在...上方”、“上部”及類似者的空間相對術語可在本文中用於便於描述如圖中所說明的一個元件或特徵與另一元件或特徵之關係。除圖中所描繪之定向以外，空間相對術語意欲涵蓋裝置在使用或操作中之不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用之空間相對描述詞可同樣相應地進行解釋。
本揭露內容之實施例在半導體封裝件及形成所述半導體封裝件之方法之上下文中論述，且尤其是積體扇出型(integrated fan-out；InFO)半導體封裝件。在一些實施例中，多個半導體晶粒及導電柱形成於載體上方，且模製材料形成於載體上方及晶粒周圍以及導電柱周圍。重佈線結構形成於模製材料、晶粒及導電柱上方，以形成包括多個個別的半導體封裝件之半導體結構，將在後續處理中切割所述個別的半導體封裝件。根據一些實施例，無密封環形成於晶粒周圍之重佈線結構中，此節省了用於密封環之空間且允許更多個別的半導體封裝件形成於載體上方，由此增 大製造製程之產率。在一些實施例中，為分離個別的半導體封裝件，執行預切製程以在半導體結構之第一側中(例如，在重佈線結構之切割區域中)形成開口，隨後自與第一側相對之半導體結構之第二側開始切割製程。由預切製程形成之開口可在切割製程期間防止或減小重佈線結構之分層(delamination)。
圖1至圖6、圖7A、圖7B以及圖8至圖11繪示根據一實施例的在各個製造階段處之疊層封裝(PoP)半導體封裝件500之各種視圖(例如，截面視圖、俯視圖)。詳言之，圖1至圖6、圖7A、圖7B以及圖8繪示PoP封裝件之一或多個底部封裝件1100(例如，底部封裝件1100A、底部封裝件1100B)之各種視圖，且圖9至圖11繪示在頂部封裝件160(例如，頂部封裝件160A、頂部封裝件160B)貼合至底部封裝件1100之後的PoP封裝件之截面視圖。
參考圖1，可為緩衝層之介電層110形成於載體101上方。導電柱119形成於介電層110上方。
載體101可由諸如矽、聚合物、聚合物複合物、金屬箔、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、載帶(tape)之材料或用於結構支撐的其他適合之材料製成。在一些實施例中，介電層110由以下形成：聚合物，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene；BCB)或其類似物；氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)或其類似物。介電層110可經合適沈積製程形成，所述沈 積製程諸如旋塗、化學氣相沈積(chemical vapor deposition；CVD)、疊層(laminating)、其類似製程或其組合。
在一些實施例中，黏著層(未繪示)在形成介電層110之前沈積或疊層於載體101上方。黏著層可為感光性的且可藉由例如在後續載體剝離製程中在載體101上照射紫外線(ultra-violet；UV)光而易於自載體101脫離。舉例而言，黏著層可為由明尼蘇達州聖保羅市(St.Paul,Minnesota)之3M公司或其他供應商製得之光-熱轉換(light-to-heat-conversion；LTHC)塗層。
仍參考圖1，導電柱119形成於介電層110上方。導電柱119可藉由以下來形成：在介電層110上方形成晶種層；在晶種層上方形成經圖案化光阻，其中經圖案化光阻中之開口中的每一者對應於待形成之導電柱119之位置；使用例如電鍍或無電極電鍍以諸如銅之導電材料填充開口；使用例如灰化(ashing)或剝離(stripping)製程移除光阻；以及移除不形成導電柱119的晶種層之部分。用於形成導電柱119之其他方法亦為可能的且全部意欲包含於本揭露內容之範疇內。在一些實施例中，省略介電層110，且導電柱119形成於黏著層(例如，LTHC塗層)上，所述黏著層沈積或疊層於載體101上方。
接著，在圖2中，半導體晶粒120(亦可稱為晶粒或積體電路(integrated circuit；IC)晶粒)貼合至介電層110之上部表面。諸如晶粒貼合膜(die attaching film；DAF)之黏著膜118可用於將晶粒120貼合至介電層110。
在黏著至介電層110之前，晶粒120可根據可應用的製 造製程處理以在晶粒120中形成積體電路。舉例而言，晶粒120可包含半導體基底及一或多個上覆金屬化層，共同地繪示為元件121。半導體基底可為例如經摻雜或未經摻雜之矽，或絕緣體上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底可包含其他半導體材料，諸如鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含矽鍺(SiGe)、磷化鎵砷(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵GaInAs)、磷化銦鎵(GaInP)及/或磷砷化銦鎵(GaInAsP)；或其組合。亦可使用其他基底，諸如多層基底或梯度基底(gradient substrate)。諸如電晶體、二極體、電容器、電阻器等之裝置(未繪示)可形成於半導體基底中及/或上，且可由金屬化層互連以形成積體電路，所述金屬化層例如半導體基底上方的一或多個介電層中之金屬化圖案。
晶粒120更包括進行外部連接之墊126，諸如鋁墊。墊126在可稱為晶粒120之主動側或前側的位置上。鈍化膜127形成於晶粒120之前側處且在墊126之一些部分上。形成穿過鈍化膜127而延伸至墊126的開口。諸如導電柱(例如，包括諸如銅之金屬)的晶粒連接件128延伸至鈍化膜127之開口中且機械地及電性地耦接至對應的墊126。晶粒連接件128可藉由例如電鍍或其類似方法形成。晶粒連接件128電性耦接至晶粒120之積體電路。
介電材料129形成於晶粒120之主動側處，諸如形成於鈍化膜127及/或晶粒連接件128上。介電材料129側向包封晶粒連接件128，且介電材料129與晶粒120側向上有共同邊界。介電材料129可為：聚合物，諸如聚苯并噁唑(PBO)、聚醯亞胺、苯 并環丁烯(BCB)或其類似物；氮化物，諸如氮化矽或其類似物；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻磷矽酸鹽玻璃(BPSG)或其類似物；或其組合，且可例如藉由旋塗、疊層、化學氣相沈積(CVD)或其類似方式形成。
接著，在圖3中，模製材料130形成於介電層110上方，形成於晶粒120周圍，且形成於導電柱119周圍。作為實例，模製材料130可包括環氧樹脂、有機聚合物、添加或不添加二氧化矽類或玻璃填充劑之聚合物或其他材料。在一些實施例中，模製材料130包括在應用時為凝膠型液體之液體模製化合物(liquid molding compound；LMC)。模製材料130在應用時亦可包括液體或固體。或者，模製材料130可包括其他絕緣及/或包封材料。在一些實施例中，使用晶圓級模製製程來應用模製材料130。模製材料130可使用例如壓縮模製(compressive molding)、轉移模製(transfer molding)或其他方法來模製。
接著，在一些實施例中，使用固化製程來固化模製材料130。固化製程可包括使用退火製程或其他加熱製程在預定時間段將模製材料130加熱至預定溫度。固化製程亦可包括紫外線(ultra-violet；UV)曝光製程、紅外(infrared；IR)能量暴光製程、其組合或其與加熱製程之組合。或者，可使用其他方法來固化模製材料130。在一些實施例中，不包含固化製程。
諸如化學及機械研磨(chemical and mechanical polish；CMP)之平坦化製程可視情況執行以移除晶粒120之前側上方的模製材料130之過量部分。在一些實施例中，在平坦化製程之後，模製材料130、導電柱119以及晶粒連接件128具有共面上部表面。
接著參考圖4，重佈線結構140(亦可稱為前側重佈線結構)形成於模製材料130、導電柱119以及晶粒120上方。重佈線結構140包括形成於一或多個介電層(例如，介電層142、介電層144、介電層146以及介電層148)中之一或多個導電特徵(例如，導線143、通孔145)層。
在一些實施例中，一或多個介電層(例如，介電層142、介電層144、介電層146以及介電層148)由以下形成：聚合物，諸如聚苯并噁唑(PBO)、聚醯亞胺、苯并環丁烯(BCB)或其類似物；氮化物，諸如氮化矽；氧化物，諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻磷矽酸鹽玻璃(BPSG)或其類似物。一或多個介電層可經合適沈積製程形成，所述沈積製程如旋塗、化學氣相沈積(CVD)、疊層、其類似製程或其組合。
在一些實施例中，重佈線結構140之導電特徵包括導線(例如，導線143)及導電通孔(例如，導電通孔145)，所述導電通孔由合適的導電材料形成，所述導電材料諸如銅、鈦、鎢、鋁或其類似物。在一些實施例中，導電特徵由以下形成：在重佈線結構140之介電層中形成開口以暴露底層導電特徵，在介電層上方及在開口中形成晶種層(未繪示)，在晶種層上方以經設計之圖案形成經圖案化之光阻(未繪示)，在經設計之圖案及晶種層上方電鍍(例如，電鍍或無電極電鍍)導電材料，且移除光阻及不形成導電材料之晶種層之部分。形成重佈線結構140之其他方法亦為可能的且全部意欲包含於本揭露內容之範疇內。
圖4之重佈線結構140中的介電層之數目及導電特徵層的數目僅為非限制性實例。介電層之其他數目及導電特徵層的其 他數目亦為可能的且全部意欲包含於本揭露內容之範疇內。
圖4亦繪示凸塊下金屬化(under bump metallization；UBM)結構147，其形成於重佈線結構140上方且電耦接至所述重佈線結構140。為形成UBM結構147，開口在重佈線結構140之最頂部介電層(例如，介電層142)中形成，以暴露重佈線結構140之導電特徵(例如，銅線或銅墊)。在形成開口之後，UBM結構147可形成為與所暴露之導電特徵電性接觸。在一實施例中，UBM結構147包括三個導電材料層，諸如鈦層、銅層以及鎳層。然而，存在許多合適的材料及層佈置，諸如鉻/鉻銅合金/銅/金佈置、鈦/鈦鎢/銅佈置或銅/鎳/金佈置，所述材料及層佈置適合於形成UBM結構147。可用於UBM結構147之任何適合的材料或材料層全部意欲包含於本揭露內容之範疇內。
UBM結構147可藉由以下形成：在最頂部介電層(例如，介電層142)上方及沿最頂部介電層中之開口的內部形成晶種層；在晶種層上方形成經圖案化罩幕層(例如，光阻)；在經圖案化罩幕層之開口中及晶種層上方(例如，藉由電鍍)形成一或多種導電材料；移除罩幕層，且移除不形成一或多種導電材料之晶種層之部分。用於形成UBM結構147之其他方法為可能的且全部意欲包含於本揭露內容之範疇內。圖4中之UBM結構147之上部表面僅作為一實例而繪示為平面的，UBM結構147之上部表面可不為平面的。舉例而言，每個UBM結構147之部分(例如，外圍部分)可形成於最頂部介電層(例如，介電層142)上方，且每個UBM結構147之其他部分(例如，中心部分)可沿最頂部介電層之側壁共形地形成，所述最頂部介電層之側壁由對應開口暴露 出，如熟習此項技術者所能理解。
接著，在圖5中，根據一些實施例，連接件155形成於UBM結構147上方。連接件155可為焊球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微型凸塊、無電鍍鎳-無電鍍鈀-浸鍍金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成式凸塊、其組合(例如，具有貼合至其的焊球的金屬柱)或其類似物。連接件155可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、其類似導電材料或其組合。在一些實施例中，作為實例，連接件155包括共晶(eutectic)材料，且可包括焊料凸塊或焊球。舉例而言，焊料材料可為鉛系以及無鉛焊料，諸如鉛系焊料Pb-Sn組成物；無鉛焊料包含InSb；錫、銀以及銅(SAC)組成物；以及具有共同熔點且在電應用中形成導電焊料連接的其他共晶材料。對於無鉛焊料，作為實例，可使用變化組合物的SAC焊料，諸如SAC 105(錫98.5%、銀1.0%、銅0.5%)、SAC 305以及SAC 405。諸如焊球之無鉛連接件亦可由SnCu化合物形成，而無需使用銀(Ag)。或者，無鉛焊料連接件可包含錫以及銀(Sn-Ag)，而無需使用銅。連接件155可形成柵格，諸如球柵陣列(ball grid array；BGA)。在一些實施例中，可執行回焊製程，從而在一些實施例中給予連接件155部分球面之形狀。或者，連接件155可包括其他形狀。連接件155亦可包括例如非球面導電連接件。
在一些實施例中，連接件155包括金屬柱(諸如銅柱)，所述金屬柱由濺鍍、印刷、電極電鍍、無電極電鍍、CVD或其類似方法形成，在所述金屬柱上具有或不具有焊料材料。金屬柱可 不含焊料，且具有實質上豎直之側壁或楔形側壁。
圖5進一步繪示電氣裝置171，諸如積體被動裝置(integrated passive device；IPID)，其通過例如UBM結構147電性耦接至重佈線結構140。諸如焊接接頭之導電接合點173可形成於電氣裝置171與重佈線結構140之間。導電接合點173可包括與連接件155相同之材料(例如，焊料)。另外，底填充材料175可形成於電氣裝置171與重佈線結構140之間的間隙中。
圖5之實例出於說明之目的繪示形成於載體101上方之一個半導體封裝件1100。所屬領域中具通常知識者將瞭解，數十、數百或甚至更多個半導體封裝件(例如，半導體封裝件1100)可在與圖1至圖5中所說明相同的處理步驟中形成於載體101上方。在理解多於兩個半導體封裝件可形成於載體101上方之情況下，圖6至圖10使用兩個半導體封裝件(例如，半導體封裝件1100A及半導體封裝件1100B)形成於載體101上方之實例來繪示圖5之半導體封裝件1100之進一步處理。
圖6繪示包括分別形成於半導體結構之區域100及區域200中之半導體封裝件1100A及半導體封裝件1100B的半導體結構。在所繪示之實施例中，半導體封裝件1100A及半導體封裝件1100B中的每一者與圖5中所繪示之半導體封裝件1100相同。
如圖6中所繪示，重佈線結構140'連續地形成於模製材料130上方及所有晶粒120上方。區域100中之重佈線結構140'之一部分在區域100中之晶粒120/導電柱119上方(例如，正上方)且電性耦接至所述晶粒120/導電柱119，且對應於諸如圖5中所繪示之重佈線結構140的重佈線結構。類似地，區域200中 之重佈線結構140'之一部分在區域200中之晶粒120/導電柱119上方(例如，正上方)且電性耦接至所述晶粒120/導電柱119，且對應於諸如圖5中所繪示之重佈線結構140的另一重佈線結構。
如圖6中所繪示，重佈線結構140'更包括在區域100與區域200之間的區域300(亦可稱為切割區域)中之部分。切割區域300之寬度可在約40微米與約260微米之間，諸如約40微米，但其他尺寸亦為可能的。在一些實施例中，區域300中之重佈線結構140'之部分僅包括介電層(參看，例如，圖4中之介電層142、介電層144、介電層146、介電層148)，且在區域300中不存在導電特徵(例如，導線、通孔)。另外，在所繪示之實施例中，在重佈線結構140'中未形成密封環。
密封環一般包括虛擬導電特徵，諸如形成於每個半導體封裝件(例如，半導體封裝件1100A及半導體封裝件1100B)之周邊周圍的重佈線結構(例如，重佈線結構140')中之金屬線及金屬通孔。換言之，在平面圖中，密封環中之每一者具有環形狀(例如，矩形)且環繞對應的半導體封裝件(例如，半導體封裝件1100A、半導體封裝件1100B)。密封環之金屬線及金屬通孔可以與重佈線結構140'之導線(參看例如，圖4中的導線143)及導電通孔(參看例如，圖4中之導電通孔145)相同之處理步驟且使用與所述導線及所述導電通孔相同的一或多種材料來形成。舉例而言，除了密封環之金屬線及金屬通孔為電絕緣之外，密封環之金屬線及金屬通孔可形成於形成重佈線結構140'之導線及導電通孔的相同介電層中。密封環經建構來保護例如半導體封裝件之重佈線結構在後續切割製程期間免於開裂及/或分層。舉例而言，當劃 片機之刀片切入兩個相鄰密封環之間的切割區域300中時，由刀片造成的重佈線結構140'中之開裂可由密封環阻止且可避免對半導體封裝件之破壞。類似地，可另外由於切割出現之重佈線結構140之分層亦可由密封環阻止或減小。
然而，密封環佔據半導體結構中之空間。舉例而言，密封環之寬度可為約40微米，且兩個半導體封裝件(例如，半導體封裝件1100A及半導體封裝件1100B)之間具有約80微米之總寬度的區域用於形成密封環。藉由不在重佈線結構140'中之半導體封裝件(例如，半導體封裝件1100A及半導體封裝件1100B)周圍形成任何密封環，本揭露內容釋放出更多空間以在載體101上形成半導體封裝件。舉例而言，約2%或多於2%半導體封裝件可藉由不形成密封環而形成於載體101上，由此達成更高產率。另外，下文中所揭露之預切製程及切割製程在不使用密封環之情況下避免或減小重佈線結構140'中之開裂/分層。
現參考圖7A，執行預切製程以形成切割區域300中之重佈線結構140'中之開口311/開口313。如圖7A中所繪示，開口311鄰近半導體封裝件1100A形成，且開口313鄰近半導體封裝件1100B形成。開口311之寬度W1在約20微米與約80微米之間，且開口313之寬度W1'在約20微米與約80微米之間。在一些實施例中，寬度W1與寬度W1'實質上相同。在其他實施例中，寬度W1與寬度W1'不同。在一些實施例中，開口311之側壁311E與開口313之側壁313E之間所測量的寬度W2在約20微米與約80微米之間，其中側壁311E為最接近於半導體封裝件1100A的開口311之側壁，且側壁313E為最接近於半導體封裝件1100B的 開口313之側壁。圖7A中所繪示之開口311及開口313之矩形橫截面僅為非限制性實例。用於開口311及開口313之橫截面的其他形狀為可能的且全部意欲包含於本揭露內容之範疇內。舉例而言，開口311及開口313之底部可取決於例如用於形成開口之方法而具有不規則形狀。
如圖7A中所繪示，移除切割區域300中之重佈線結構140'之介電層的部分以形成開口311/開口313。在圖7A之實例中，開口311及開口313藉由切割區域300中之重佈線結構140之介電層的剩餘部分140R而彼此實體上分離。在一些實施例中，剩餘部分140R之寬度W4在約140微米與200微米之間。另外，亦移除切割區域300中之模製材料130之部分以形成開口。因此，在所繪示之實施例中，開口311及開口313延伸穿過重佈線結構140且延伸至模製材料130中。舉例而言，開口311及開口313可延伸至模製材料130中約20微米與100微米之間的範圍內的深度。
在一示例性實施例中，兩個雷射光束用於同時形成開口311及開口313。換言之，代替相繼形成開口311及開口313，開口311及開口313使用兩個雷射光束來同時形成以增加生產量，儘管有可能使用一個雷射光束以例如相繼形成開口311及開口313。在一些實施例中，所使用之雷射器可為CO2雷射器、UV雷射器或綠光雷射器。諸如纖維雷射器及釔鋁石榴(Yttrium-Aluminum-Garnet；YAG)雷射器之其他類型的雷射器亦涵蓋於本揭露內容之範疇內。在一些實施例中，雷射器之平均輸出功率在約0.5瓦與約8瓦之間的範圍內，但其他輸出功率範圍亦為可能的且全部意欲包含於本揭露內容之範疇內。雷射器之平均 輸出功率藉由各種因素確定，所述因素諸如重佈線結構140'之介電層之材料、開口311/開口313的深度及所要求之處理速度。
在圖7A中，兩個開口311/開口313由預切製程形成，其中每個開口在後續切割製程中提供使鄰近半導體封裝件免於開裂及/或分層的保護，如將在下文中參考圖10更詳細地論述。詳言之，開口311保護半導體封裝件1100A之重佈線結構，且開口313保護半導體封裝件1100B之重佈線結構。可不必在兩個鄰近半導體封裝件之間形成多於兩個開口，因為若形成，則一或多個額外開口在切割期間不提供使重佈線結構140'免於開裂及/或分層之許多額外保護。另一方面，僅形成一個開口，例如，僅形成開口311或僅形成開口313，可不提供對兩個鄰近半導體封裝件中之一者的保護。儘管具有較寬寬度之開口，例如具有自311E至313E延伸之寬度的開口，可在兩個鄰近半導體封裝件之間形成以提供免於開裂及/或分層之保護，但形成此類較寬開口可能花費顯著更長時間且/或可能需要具有更高輸出功率之雷射器。因此，藉由預切製程與下文中參考圖10所論述之切割製程組合形成於兩個鄰近半導體封裝件之間的兩個開口(例如，開口311及開口313)提供高效(例如，更短構造時間及更高產率)及易於實施之製造方法，所述製造方法不需要密封環但仍提供免於開裂及分層之保護。
在一些實施例中，圖7B繪示圖7A之半導體結構之俯視圖。除半導體封裝件1100A及半導體封裝件1100B以外，形成於載體101上之額外半導體封裝件(例如，半導體封裝件1100C、半導體封裝件1100D、半導體封裝件1100E以及半導體封裝件1100F)亦繪示於圖7B中。為簡單起見，並非半導體封裝件之所 有細節均展示於圖7B中。如圖7B中所繪示，開口(例如，開口311、開口313、開口311'以及開口313')藉由預切製程形成於相鄰半導體封裝件之間的切割區域中。在圖7B之俯視圖中，兩個相鄰半導體封裝件(例如，半導體封裝件1100A及半導體封裝件1100B)之間的每對開口(例如，開口311及開口313)可形成兩個平行溝渠。預切製程可沿對應半導體封裝件之各側(例如，側壁)形成兩個平行溝渠。換言之，每個半導體封裝件可被例如俯視圖中之四對開口所環繞，其中半導體封裝件之各側具有一對開口(例如，兩個平行溝渠)，所述開口沿半導體封裝件之側面延伸。
接著，在圖8中，翻轉圖7A中所示之半導體結構，且外部連接件155貼合至由框架157支撐之載帶159(例如，切割帶)。接著，載體101藉由合適製程自介電層110剝離，所述製程諸如蝕刻、研磨或機械剝離。在黏著層(例如，LTHC膜)形成於載體101與介電層110之間的實施例中，藉由將載體101暴露於雷射光或UV光而剝離載體101。雷射光或UV光破壞黏合至載體101之黏著層的化學黏合，而載體101隨後可易於脫離。若形成黏著層，則所述黏著層可藉由載體剝離製程移除。若有任何黏著層之殘留物，則所述殘留物可藉由清潔製程移除，所述清潔製程在載體剝離製程之後執行。
在剝離載體101之後，開口116形成於介電層110中以暴露導電柱119。為形成開口116，可使用雷射鑽孔製程、蝕刻製程或其類似製程。在一些實施例中，蝕刻製程為電漿蝕刻製程。儘管未繪示，但焊錫膏可在用於貼合頂部封裝件之製備中使用例如焊錫膏印刷製程以形成於開口116中(參看圖9)。
在省略介電層110且導電柱119形成於黏著層(例如，LTHC塗層)上方且黏著層沈積或疊層於載體101上方的實施例中，在載體剝離製程之後，導電柱119可暴露在模製材料130之上部表面處。因此，可省略用於暴露導電柱119之鑽孔製程或蝕刻製程。圖8至圖11繪示形成有介電層110之實施例。在閱讀本揭露內容時，所屬領域中具通常知識者將能夠針對省略介電層110之實施例而修改圖8至圖11中所繪示的處理。
接著參考圖9，諸如記憶體封裝件之半導體封裝件160A及半導體封裝件160B(也稱為頂部封裝件)分別貼合至半導體封裝件1100A及半導體封裝件1100B(也稱為底部封裝件)，以形成圖9中之半導體封裝件500A及半導體封裝件500B，由此形成具有疊層封裝(PoP)結構之多個半導體封裝件500(例如，半導體封裝件500A、半導體封裝件500B)。
如圖9中所繪示，半導體封裝件160(例如，半導體封裝件160A、半導體封裝件160B)中之每一者具有基底161及一或多個半導體晶粒162(例如，記憶體晶粒)，所述半導體晶粒162貼合至基底161之上部表面。在一些實施例中，基底161包含矽、砷化鎵、絕緣體上矽(“silicon on insulator；SOI”)或其他類似材料。在一些實施例中，基底161為多層電路板。在一些實施例中，基底161包含雙馬來醯亞胺三嗪(bismaleimide triazine；BT)樹脂、FR-4(由編織玻璃纖維布與耐火之環氧樹脂黏合劑形成的複合材料)、陶瓷、玻璃、塑料、載帶、膜或其他支撐材料。基底161可包含形成於基底161中/上之導電特徵(例如，導線及通孔，未繪示)。如圖9中所繪示，基底161具有導電墊163，所述導電 墊163形成於基底161之上部表面及下部表面上，導電墊163電性耦接至基底161之導電特徵。一或多個半導體晶粒162藉由例如接線167電性耦接至導電墊163。可包括環氧樹脂、有機聚合物、聚合物或其類似物之模製材料165形成於基底161上方及半導體晶粒162周圍。在一些實施例中，如圖8中所繪示，模製材料165與基底161具有共同邊界。
在一些實施例中，執行回焊製程以通過導電接合點168將半導體封裝件160之導電墊163電性地耦接及機械地耦接至導電柱119。在一些實施例中，導電接合點168包括焊料區域、導電柱(例如，在銅柱之至少末端表面具有焊料區域之銅柱)或一或多種任何其他合適材料。
在回焊製程之後，可執行烘烤製程。烘烤製程可移除半導體結構上之水分。接著，底填充材料169形成於頂部封裝件160(例如，頂部封裝件160A、頂部封裝件160B)與對應底部封裝件1100(例如，底部封裝件1100A、底部封裝件1100B)之間的間隙中。底填充材料169可使用例如針或噴射分配器分配於頂部封裝件160與底部封裝件1100之間的間隙中。可執行固化製程以固化底填充材料169。儘管未繪示，但底填充材料169可沿頂部封裝件160之側壁延伸。
接著，在圖10中，執行切割製程以將PoP封裝件500(例如，PoP封裝件500A、PoP封裝件500B)分成多個個別的PoP封裝件。在一示例性實施例中，具有W3之寬度的刀片315用於切割PoP封裝件。在一些實施例中，寬度W3小於開口311之側壁311E與開口313之側壁313E之間所測量的寬度W2。在所繪示 之實施例中，刀片315放置於側壁311E與側壁313E之間的中心區域中，且因此，在切割製程期間，不交疊或接觸側壁311E/側壁313E。換言之，刀片315側向地在側壁311E與側壁313E之間。在一些實施例中，刀片315之寬度W3寬於安置於開口311與開口313之間的重佈線結構140'之剩餘部分140R之寬度W4。此可允許刀片315一刀移除剩餘部分140R以減小切割製程之處理時間。舉例而言，重佈線結構140'之剩餘部分140R可側向地在刀片315之相對豎直側壁之間，以使得隨著刀片315向下朝向重佈線結構140'切割，剩餘部分140R將一刀被移除。
如圖10中所繪示，刀片315自與開口311/開口313相對的半導體封裝件1100之一側切入切割區域300中。換言之，刀片315自鄰近晶粒120之背側的底部封裝件之上部表面開始切入圖10中所繪示之半導體結構。隨著刀片315朝向重佈線結構140'移動，除了重佈線結構140'之剩餘部分140R以外，由於開口311/開口313將刀片315與重佈線結構140'隔離，因此刀片315不接觸重佈線結構140'。因此，避免或減小重佈線結構140'之開裂及/或分層。
儘管未繪示，但圖7至圖10中所繪示之預切製程及切割製程可在其他切割區域中執行，例如PoP封裝件500A/500B與其他相鄰PoP封裝件(未展示)之間的切割區域。在完成切割製程之後，形成諸如圖11中所繪示之PoP封裝件500的多個個別的PoP封裝件。
如圖11中所繪示，個別的PoP封裝件500具有重佈線結構140，其中晶粒120及導電柱119電性耦接至重佈線結構140 之上部表面。模製材料130形成於晶粒120周圍及導電柱119周圍之重佈線結構140上方。在圖11之實例中，模製材料130延伸超出重佈線結構140之側向範圍。換言之，模製材料130寬於重佈線結構140，由此不與所述重佈線結構140具有共同邊界。舉例而言，模製材料130可以寬度W5側向延伸超出重佈線結構140之邊界(例如，側壁)，所述寬度W5可介於約1微米至約810微米範圍內。在一些實施例中，此為由於刀片315之寬度W3小於側壁311E與側壁313E之間的寬度W2。
如圖11中所繪示，模製材料130之上部部分(例如，遠離重佈線結構140之部分)具有延伸超出重佈線結構140之側向範圍的側壁130S1。另外，模製材料130之下部部分(例如，實體接觸重佈線結構140之部分)可具有與重佈線結構140之側壁對準的側壁130S2，例如，模製材料130之下部部分可具有與重佈線結構140相同的寬度。
仍參考圖11，延伸超出重佈線結構140之側向範圍的模製材料130之上部部分具有高度H1，所述高度H1小於設置於重佈線結構140之側向範圍內的模製材料130之部分的高度H2。前已述及，開口311/開口313可延伸至模製材料130中(參看例如，圖7A)。此意謂在一些實施例中移除切割區域300中之模製材料130之部分，由此導致設置於重佈線結構140之邊界(例如，側壁)外的模製材料130之上部部分的更小高度H1。在圖11中，模製材料130之上部部分之下部表面130L展示為扁平表面。此僅為實例。如上文所論述，取決於用於形成開口311/開口313之製程，下部表面130L可具有其他形狀(例如，不規則表面)。
所揭露實施例之變體為可能的且全部意欲包含於本揭露內容之範疇內。舉例而言，可修改每個PoP封裝件中之晶粒120之數目、每個PoP封裝件中的導電柱119之數目及/或位置。作為另一實例，介電層110可自PoP封裝件500完全移除。作為另一實例，可修改底填充材料169之量及/或形狀。舉例而言，底填充材料169可為持續體積之介電材料，所述介電材料填充頂部封裝件與底部封裝件之間的間隙且連續地自第一導電接合點168延伸至另一導電接合點168。或者，底填充材料169可包括多個部分，所述部分彼此實體上分離，其中底填充材料169之各部分包圍對應導電接合點168。
實施例可達成優勢。藉由省略重佈線結構中之密封環，更多空間可供用於形成半導體封裝件，由此達成較高產率。所揭露之預切製程及切割製程在不使用密封環之情況下避免或減小開裂/分層，由此允許產率增加而沒有開裂及分層相關之問題。
圖12繪示根據一些實施例的製造半導體裝置之方法3000之流程圖。應理解，圖12中所示之實施例方法僅為許多可能實施例方法之實例。所屬領域中具通常知識者將認識到許多變體、替代方式以及修改。舉例而言，可添加、移除、置換、重新佈置以及重複如圖12中所繪示之各種步驟。
參考圖12，在步驟3010處，第一晶粒及第二晶粒貼合至載體。在步驟3020處，模製材料形成於第一晶粒與第二晶粒之間。在步驟3030處，重佈線結構形成於第一晶粒、第二晶粒以及模製材料上方，重佈線結構包含：第一晶粒上方之第一重佈線區域；第二晶粒上方之第二重佈線區域；以及第一重佈線區域與第 二重佈線區域之間的切割區域。在步驟3040處，第一開口及第二開口形成於切割區域中，第一開口及第二開口延伸穿過重佈線結構且暴露模製材料之第一側。在步驟3050處，第一晶粒及第二晶粒藉由切割與切割區域對準的模製材料之一部分而分離開，其中切割自模製材料之第二側朝向模製材料之第一側執行，第二側與第一側相對。
在一實施例中，一種形成半導體封裝件的方法，包含：將第一晶粒及第二晶粒貼合至載體；在第一晶粒與第二晶粒之間形成模製材料；以及在第一晶粒、第二晶粒以及模製材料上方形成重佈線結構，重佈線結構包含：第一晶粒上方之第一重佈線區域；第二晶粒上方之第二重佈線區域；以及第一重佈線區域與第二重佈線區域之間的切割區域。所述方法更包含：在切割區域中形成第一開口及第二開口，第一開口及第二開口延伸穿過重佈線結構且暴露模製材料之第一側；以及藉由切割與切割區域對準的模製材料之一部分以將第一晶粒及第二晶粒分離，其中自模製材料之第二側朝向模製材料之第一側執行切割，第二側與第一側相對。在一實施例中，切割區域不含導電特徵。在一實施例中，第一開口及第二開口彼此實體上分離。在一實施例中，第一開口及第二開口延伸至模製材料中。在一實施例中，形成第一開口及第二開口包括使用第一雷射光束及第二雷射光束以移除切割區域中之重佈線結構之部分，以分別形成第一開口及第二開口。在一實施例中，第一雷射光束及第二雷射光束在相同時間施加於切割區域。在一實施例中，使用刀片執行切割。在一實施例中，第一開口側向地在第一晶粒與第二開口之間，其中刀片之第一寬度小於 第二寬度，所述第二寬度為最接近於第一晶粒的第一開口的第一側壁與最接近於第二晶粒之第二開口的第二側壁之間的寬度。在一實施例中，在切割期間，刀片側向地在第一開口之第一側壁與第二開口之第二側壁之間。在一實施例中，重佈線結構不含密封環。在一實施例中，所述方法更包含，在分離第一晶粒與第二晶粒之前：在鄰近於第一晶粒之模製材料中形成第一導電柱；在鄰近於第二晶粒之模製材料中形成第二導電柱；以及將第一封裝件及第二封裝件分別貼合至第一導電柱及第二導電柱。
在一實施例中，一種形成半導體封裝件的方法，包含：在載體之第一側上方形成第一導電柱及第二導電柱；將第一晶粒及第二晶粒貼合至載體之第一側，第一晶粒及第二晶粒分別鄰近於第一導電柱及第二導電柱；在載體之第一側上方形成模製材料，模製材料沿第一晶粒之側壁、第二晶粒之側壁、第一導電柱之側壁、以及第二導電柱之側壁延伸；在第一晶粒、第二晶粒以及模製材料上方形成重佈線結構，重佈線結構包括第一晶粒上方之第一重佈線區域、第二晶粒上方之第二重佈線區域以及第一重佈線區域與第二重佈線區域之間的切割區域；移除切割區域中之重佈線結構的部分以形成鄰近第一晶粒之第一開口及鄰近第二晶粒之第二開口，第一開口藉由切割區域中之重佈線結構的剩餘部分而與第二開口分離；剝離載體；將第一半導體封裝件電性耦接至第一導電柱；將第二半導體封裝件電性耦接至第二導電柱；以及自第一晶粒之背面使用刀片切割模製材料，所述切割將第一晶粒與第二晶粒分離。在一實施例中，移除切割區域中之重佈線結構之部分進一步移除模製材料之部分，以使得第一開口及第二開 口延伸至模製材料中。在一實施例中，移除切割區域中之重佈線結構之部分使用雷射器來執行。在一實施例中，刀片具有第一寬度，其中最接近於第一晶粒之第一開口的第一側壁以第二寬度與最接近於第二晶粒之第二開口的第二側壁間隔開，且其中第一寬度小於第二寬度。在一實施例中，在切割期間，刀片側向地在第一開口之第一側壁與第二開口之第二側壁之間，且不接觸第一開口之所述第一側壁及第二開口之所述第二側壁。在一實施例中，重佈線結構不含密封環。
在一實施例中，一種半導體封裝件包含：下部封裝件，其包含晶粒及鄰近晶粒的導電柱，晶粒及導電柱在重佈線結構上方；以及模製材料，其在重佈線結構上方，模製材料插入於晶粒與導電柱之間，模製材料延伸超出重佈線結構之側向範圍。在一實施例中，延伸超出重佈線結構之側向範圍的模製材料之第一部分具有第一高度，且與晶粒接觸之模製材料的第二部分具有第二高度，其中第一高度小於第二高度。在一實施例中，半導體封裝件更包含電性耦接至導電柱之頂部封裝件。
前文概述若干實施例之特徵，從而使得在所述領域中具通常知識者可較好地理解本揭露內容之態樣。所述領域中具通常知識者應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入之實施例的相同目的且/或達成相同優點的其他方法及結構的基礎。所述領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露內容之精神及範疇，且所述領域中具通常知識者可在不脫離本揭露內容之精神及範疇之情況下在本文中作出改變、替代及更改。
100、200、300‧‧‧區域
110‧‧‧介電層
311、313‧‧‧開口
120、162‧‧‧半導體晶粒
130、165‧‧‧模製材料
311E、313E‧‧‧側壁
140'‧‧‧重佈線結構
140R‧‧‧剩餘部分
157‧‧‧框架
159‧‧‧載帶
160A、160B‧‧‧頂部封裝件
161‧‧‧基底
163‧‧‧導電墊
167‧‧‧接線
169‧‧‧底填充材料
315‧‧‧刀片
500A、500B‧‧‧半導體封裝件
W2、W3、W4‧‧‧寬度

Claims (14)

  1. 一種形成半導體封裝件的方法，包括：將第一晶粒及第二晶粒貼合至載體；在所述第一晶粒與所述第二晶粒之間形成模製材料；在所述第一晶粒、所述第二晶粒以及所述模製材料上方形成重佈線結構，所述重佈線結構包括：所述第一晶粒上方之第一重佈線區域；所述第二晶粒上方之第二重佈線區域；以及所述第一重佈線區域與所述第二重佈線區域之間的切割區域；在所述切割區域中形成第一開口及第二開口，所述第一開口及所述第二開口延伸穿過所述重佈線結構且暴露所述模製材料之第一側；以及藉由切割與所述切割區域對準的所述模製材料之一部分以將所述第一晶粒及所述第二晶粒分離，其中自所述模製材料之第二側朝向所述模製材料之所述第一側執行所述切割，所述第二側與所述第一側相對。
  2. 如申請專利範圍第1項所述的方法，其中所述第一開口及所述第二開口延伸至所述模製材料中。
  3. 如申請專利範圍第1項所述的方法，其中所述切割使用刀片來執行。
  4. 如申請專利範圍第3項所述的方法，其中所述第一開口側向地在所述第一晶粒與所述第二開口之間，其中所述刀片之第一寬度小於第二寬度，所述第二寬度為最接近於所述第一晶粒之 所述第一開口的第一側壁與最接近於所述第二晶粒之所述第二開口的第二側壁之間的寬度。
  5. 如申請專利範圍第4項所述的方法，其中在所述切割期間，所述刀片側向地在所述第一開口之所述第一側壁與所述第二開口之所述第二側壁之間。
  6. 如申請專利範圍第1項所述的方法，其中所述重佈線結構不含密封環。
  7. 一種形成半導體封裝件的方法，包括：在載體之第一側上方形成第一導電柱及第二導電柱；將第一晶粒及第二晶粒貼合至所述載體之所述第一側，所述第一晶粒及所述第二晶粒分別鄰近於所述第一導電柱及所述第二導電柱；在所述載體之所述第一側上方形成模製材料，所述模製材料沿所述第一晶粒之側壁、所述第二晶粒之側壁、所述第一導電柱之側壁以及所述第二導電柱之側壁延伸；在所述第一晶粒、所述第二晶粒以及所述模製材料上方形成重佈線結構，所述重佈線結構包括所述第一晶粒上方之第一重佈線區域、所述第二晶粒上方之第二重佈線區域以及所述第一重佈線區域與所述第二重佈線區域之間的切割區域；移除所述切割區域中之所述重佈線結構之部分以形成鄰近所述第一晶粒的第一開口及鄰近所述第二晶粒之第二開口，所述第一開口藉由所述切割區域中之所述重佈線結構的剩餘部分而與所述第二開口分離；剝離所述載體； 將第一半導體封裝件電性耦接至所述第一導電柱；將第二半導體封裝件電性耦接至所述第二導電柱；以及自所述第一晶粒之背面使用刀片切割所述模製材料，所述切割將所述第一晶粒與所述第二晶粒分離。
  8. 如申請專利範圍第7項所述的方法，其中移除所述切割區域中之所述重佈線結構的部分進一步移除所述模製材料之部分，以使得所述第一開口及所述第二開口延伸至所述模製材料中。
  9. 如申請專利範圍第7項所述的方法，其中所述刀片具有第一寬度，其中最接近於所述第一晶粒之所述第一開口之第一側壁以第二寬度與最接近於所述第二晶粒之所述第二開口之第二側壁間隔開，並且其中所述第一寬度小於所述第二寬度。
  10. 如申請專利範圍第9項所述的方法，其中在所述切割期間，所述刀片側向地在所述第一開口之所述第一側壁與所述第二開口之所述第二側壁之間，且不接觸所述第一開口之所述第一側壁及所述第二開口之所述第二側壁。
  11. 如申請專利範圍第7項所述的方法，其中所述重佈線結構不含密封環。
  12. 一種半導體封裝件，包括：下部封裝件，包括：晶粒及鄰近所述晶粒之導電柱，所述晶粒及所述導電柱在重佈線結構上方；以及模製材料，在所述重佈線結構上方，所述模製材料插入於所述晶粒與所述導電柱之間，所述模製材料延伸超出所述重佈線結構之側向範圍，其中所述模製材料具有接觸所述重佈線結構 的下部部分，且具有遠離所述重佈線結構的上部部分，且其中所述模製材料的所述下部部分的第一側壁與所述模製材料的所述上部部分的第二側壁平行。
  13. 如申請專利範圍第12項所述的半導體封裝件，其中延伸超出所述重佈線結構之所述側向範圍的所述模製材料之第一部分具有第一高度，且與所述晶粒接觸的所述模製材料之第二部分具有第二高度，其中所述第一高度小於所述第二高度。
  14. 如申請專利範圍第12項所述的半導體封裝件，其中所述模製材料還具有下部表面，所述下部表面連接於所述第一側壁與所述第二側壁之間，且所述模製材料的所述下部表面垂直於所述第一側壁與所述第二側壁。
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