TWI716096B - 半導體封裝體及其形成方法 - Google Patents

半導體封裝體及其形成方法 Download PDF

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TWI716096B
TWI716096B TW108131660A TW108131660A TWI716096B TW I716096 B TWI716096 B TW I716096B TW 108131660 A TW108131660 A TW 108131660A TW 108131660 A TW108131660 A TW 108131660A TW I716096 B TWI716096 B TW I716096B
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Taiwan
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layer
composite
forming
die
package
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TW108131660A
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TW202025313A (zh
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余振華
謝靜華
林修任
裴浩然
蔡豪益
潘國龍
郭庭豪
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台灣積體電路製造股份有限公司
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Priority claimed from US16/529,989 external-priority patent/US11309294B2/en
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Publication of TW202025313A publication Critical patent/TW202025313A/zh
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Abstract

一種形成半導體封裝體的方法，包含：在載體上方形成 複合材料層，複合材料層包含併入至基礎材料中的填充物材料的多個顆粒；在複合材料層的第一側上方形成穿孔集合；在複合材料層的第一側上方貼合晶粒，晶粒與穿孔集合間隔開；在複合材料層的第一側上方形成模製材料，模製材料至少側向密封晶粒及穿孔集合中的多個穿孔；在晶粒及模製材料上方形成重佈線結構，重佈線結構電連接至多個穿孔；在複合材料層的與第一側相對的第二側中形成多個開口；以及在多個開口中形成多個導電連接件，多個導電連接件電連接至多個穿孔。

Description

半導體封裝體及其形成方法
本發明實施例是有關於一種半導體封裝體及其形成方法。
歸因於各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度的持續改良，半導體工業已經歷快速發展。一般而言，積體密度的此改良來自最小特徵大小的不斷減小，此允許將更多組件整合至給定面積中。隨著近年來對甚至更小的電子元件的需求已增長，對半導體晶粒的更小及更具創造性的封裝技術的需求已增長。
此等封裝技術的實例為疊層封裝(Package-on-Package；POP)技術。在PoP封裝中，頂部半導體封裝體堆疊於底部半導體封裝體的頂部上以允許高階的整合及組件密度。另一實例為多晶片模組(Multi-Chip-Module；MCM)技術，其中將多個半導體晶粒封裝於一個半導體封裝體中以提供具有整合功能性的半導體元件。
進階封裝技術的高階整合能夠產生具有增強的功能性及更小佔據面積的半導體元件，此有利於諸如行動電話、平板電腦 以及數位音樂播放器的較小外觀尺寸元件。另一優勢為連接半導體封裝內的互操作(interoperating)部件的導電路徑的長度縮短。此改良半導體元件的電氣效能，此是因為電路之間的內連線的更短佈線使得訊號傳播更快以及噪音及串擾減小。
根據本發明的實施例，一種形成半導體封裝體的方法，包括：在載體上方形成複合材料層，所述複合材料層包括併入至基礎材料中的填充物材料的多個顆粒；在所述複合材料層的第一側上方形成穿孔集合；在所述複合材料層的所述第一側上方貼合晶粒，所述晶粒與所述穿孔集合間隔開；在所述複合材料層的所述第一側上方形成模製材料，所述模製材料至少側向密封所述晶粒及所述穿孔集合中的所述多個穿孔；在所述晶粒及所述模製材料上方形成重佈線結構，所述重佈線結構電連接至所述多個穿孔；在所述複合材料層的與所述第一側相對的第二側中形成多個開口；以及在所述多個開口中形成多個導電連接件，所述多個導電連接件電連接至所述多個穿孔。
根據本發明的實施例，一種形成半導體封裝體的方法，包括：形成元件封裝體，其中形成所述元件封裝體包括：在複合層的第一表面上形成金屬化圖案，其中所述複合層包括複合材料且其中所述第一表面是有凹痕的；在所述複合層及所述金屬化圖案上方形成第一介電層；在所述第一介電層上方形成導電柱且所述導電柱電連接至所述金屬化圖案；在所述第一介電層上置放第一半導體元件，其中所述第一半導體元件與所述導電柱相鄰且與 所述導電柱分隔開；用密封體密封所述第一半導體元件及所述導電柱；以及在所述密封體上方形成重佈線結構。在所述複合層的第二表面中形成多個開口以暴露所述金屬化圖案；以及使用多個導電連接件將頂部封裝體貼合至所述元件封裝體，其中所述多個導電連接件延伸穿過所述複合層中的所述多個開口。
根據本發明的實施例，一種半導體封裝體，包括下部封裝體以及頂部封裝體。下部封裝體包括晶粒、穿孔、模製材料以及複合層。晶粒位於重佈線結構上，所述晶粒電連接至重佈線結構。穿孔靠近所述晶粒且電連接至所述重佈線結構。模製材料位於所述重佈線結構上方，所述模製材料插入於所述晶粒與所述穿孔之間。複合層位於所述晶粒及所述穿孔上方，所述複合層在所述晶粒的與所述重佈線結構相對的一側上方。頂部封裝體包括多個外部連接件，其中所述多個外部連接件經由所述複合層連接至所述下部封裝體。
100、200、A、B、C:區域
101:載體
103:釋放層
110:複合層
112:金屬化圖案
113:基礎材料
114、148:介電層
115:填充物材料
116:開口
117:凹痕
118:黏著膜
119:穿孔
120、162:半導體晶粒
121:構件
126:墊
127:鈍化膜
128:晶粒連接件
129:介電材料
130、165:模製材料
140:重佈線結構
143:導電線
145:通孔
147:凸塊下金屬化結構
155:連接件
157:框架
159:載帶
160、160A、160B:頂部封裝體
161:基底
163:導電墊
167:接合線
168、173:導電連接件
169、175:底填充材料
170:焊料材料
171:電氣元件
500、500A、500B、600:封裝結構
1100、1100A、1100B、1200:元件封裝體
當結合隨附圖式閱讀時，自以下詳細描述最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見而任意地增大或減小各種特徵的尺寸。
圖1示出根據實施例的處於製造階段的半導體封裝體中的複合層的橫截面視圖。
圖2至圖13示出根據實施例的處於各種製造階段的半導體封裝體的橫截面視圖。
圖14示出根據實施例的半導體封裝體的橫截面視圖。
圖15A至圖15D示出根據一些實施例的處於各種製造階段的半導體封裝體中的複合層的各種視圖。
圖16示出根據實施例的半導體封裝體的橫截面視圖。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露內容。當然，此等僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或在第二特徵上形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含可在第一特徵與第二特徵之間形成額外特徵，使得第一特徵與第二特徵可以不直接接觸的實施例。
此外，為易於描述，本文中可使用諸如「在......之下(beneath)」、「在......下方(below)」、「下部(lower)」、「在......之上(above)」、「上部(upper)」以及類似者的空間相對術語來描述如圖式中所示出的一個構件或特徵與另一構件或特徵的關係。除圖式中所描繪的定向以外，空間相對術語意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
本揭露內容的實施例在半導體封裝體及形成所述半導體封裝體(且尤其形成積體扇出(integrated fan-out；InFO)型半導體封裝體)的方法的上下文中論述。包含併入至介電材料(例如， 聚合物)中的填充物材料(例如，顆粒)的複合材料層形成於載體上方，且接著一或多個半導體晶粒及/或導電柱形成於複合材料上方。模製材料形成於載體上方以及晶粒周圍及導電柱周圍。重佈線結構形成於模製材料、晶粒以及導電柱上方。在一些情況下，複合材料層的使用可改良半導體封裝體的結構剛性。複合材料層亦可減少因其他層(諸如重佈線結構的彼等層)而導致的翹曲或彎曲。此外，複合材料層可具有粗糙或有凹痕的(pitted)表面，此可改良後續沈積於複合材料上的材料的黏著力。
圖1示出根據實施例的處於製造階段的封裝結構500中的複合層110的橫截面視圖。圖2至圖13示出根據實施例的處於各種製造階段的封裝結構500的橫截面視圖。圖14示出根據實施例的封裝結構500的橫截面視圖。圖15A至圖15C示出根據一些實施例的處於各種製造階段的封裝結構500中的複合層110的各種視圖。圖16示出根據實施例的封裝結構600的橫截面視圖。
參看圖1，釋放層103及複合層110形成於載體101上方。載體101可為晶圓、面板結構或類似者，且可由諸如矽、氧化矽、鋁、氧化鋁、聚合物、聚合物複合物、金屬箔、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、載帶、類似者或組合的材料製成。載體101為後續形成的結構提供支撐。
在一些實施例中，釋放層103在複合層110形成之前沈積或疊層於載體101上方。釋放層103可由聚合物類材料形成，所述聚合物類材料可與載體101一起自形成於後續步驟中的上覆結構中移除。在一些實施例中，釋放層103為在加熱時失去其黏著性質之環氧類熱釋放材料，諸如光熱轉換 (Light-to-Heat-Conversion；LTHC)釋放塗層。在其他實施例中，釋放層103可為在暴露於紫外(ultra-violet；UV)光時失去其黏著性質的感光性材料，諸如UV膠。釋放層103可作為液體施配且固化、可為疊層至載體101上的疊層膜，或類似者。釋放層103的頂部表面可經水平化，且可具有高度共面性。
仍參看圖1，複合層110形成於釋放層103上方。圖1亦示出複合層110的放大部分。在一些實施例中，複合層110為包含併入基礎材料113內的填充物材料115的複合材料。填充物材料115可提高複合層110的機械強度或剛性，下文更詳細地描述。基礎材料113可為聚合物、環氧樹脂、樹脂、底填充材料、材料的組合或類似者。
複合層110的填充物材料115可包括顆粒、纖維、類似者或組合。在一些實施例中，填充物材料115包括氧化矽、氧化鋁、類似者或組合的顆粒。在一些實施例中，顆粒具有約0.5微米與約30微米之間的直徑，但顆粒在其他實施例中可具有其他直徑。在一些實施例中，複合層110的填充物材料115可經選擇以具有特定的直徑範圍或以具有平均直徑。舉例而言，在一些實施例中，填充物材料115可經選擇以具有約0.5微米與約30微米之間的平均直徑。在一些實施例中，複合層110內的填充物材料115的體積可在複合層110的總體積的約30%與約80%之間。在一些實施例中，填充物材料115與基礎材料113的體積比可在約0.5：1與約3：1之間。填充物材料115的特性可經選擇以向複合層110提供特定特性，諸如剛性。舉例而言，具有更大平均直徑的填充物材料115的複合層110可比具有更小平均直徑的填充物材料的 複合層110具有更大剛性(例如，更大楊氏模數)。藉由使用具有更高剛性的用於複合層110的材料，可改良在其上形成的結構(例如，圖14中的封裝結構500)的剛性，且可減少結構的翹曲或彎曲(下文更詳細地描述)。
在一些實施例中，複合層110為複合聚合物材料、底填充材料、模製化合物、環氧樹脂、樹脂、材料的組合或類似者。在一些實施例中，複合層110可具有大於約10ppm/℃的熱膨脹係數(coefficient of thermal expansion；CTE)，諸如約22ppm/℃。在一些實施例中，複合層110可具有大於約10GPa的楊氏模數，諸如約23GPa。在一些實施例中，複合層110可具有約10微米與約100微米之間的厚度，諸如約35微米。複合層110可使用適合的沈積製程形成於載體101上方，所述沈積製程諸如旋轉塗佈、化學氣相沈積(chemical vapor deposition；CVD)、疊層、類似者或其組合。在一些實施例中，複合層110在沈積之後使用固化製程固化。固化製程可包括使用退火製程或其他加熱製程將複合層110加熱至預定溫度持續預定時間段。固化製程亦可包括紫外(UV)光曝光製程、紅外(infrared；IR)能量曝光製程、其組合或其與加熱製程的組合。替代性地，複合層110可使用其他技術來固化。在一些實施例中，不包含固化製程。
在一些情況下，如圖1中所繪示，複合層110的一或多個表面可為有凹痕的(pitted)，且因而包含多個凹痕117。凹痕117可例如由以下引起：填充物材料115的暴露出的塊片(piece)自基礎材料113脫落或以其他方式自基礎材料113移除，因而在先前填充物材料115的塊片的位置處留下凹痕117。舉例而言，填充 物材料115的暴露塊片可在後續清潔製程期間或在另一後續製程步驟期間移位。在一些情況下，多個凹痕117中的一些可具有約等於或小於填充物材料115的尺寸(例如，直徑)的尺寸(例如，直徑或深度)。舉例而言，在一些實施例中，多個凹痕117中的一些可具有約0.5微米與約30微米之間的直徑或深度。然而，在一些情況下，一些凹痕117可具有小於填充物材料115尺寸的尺寸或大於填充物材料115尺寸的尺寸。在一些情況下，凹痕117的存在可改良上覆層的黏著力，所述上覆層諸如圖3中所繪示的介電層114。在一些情況下，凹痕117的存在可引起複合層110的表面具有約0.1微米及約10微米之間的粗糙度。在一些情況下，凹痕117可覆蓋複合層110的表面的約50%與約90%之間。
轉向圖2，金屬化圖案112形成於複合層110上。在一些實施例中，金屬化圖案112藉由在複合層110上方形成晶種層(未繪示)來形成。晶種層可為金屬層或另一類型的層，且可包含一或多種不同材料的一或多個層。在一些實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。接著，在晶種層上形成光阻並圖案化光阻。光阻可藉由旋轉塗佈或類似者來形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案112。圖案化形成穿過光阻的開口以暴露晶種層。導電材料在光阻的開口中及晶種層的暴露部分上形成。導電材料可藉由鍍覆，諸如電鍍或化學鍍或類似者形成。導電材料可包括金屬，如銅、鈦、鎢、鋁、組合或類似者。接著，移除光阻及晶種層的其上未形成導電材料的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。在一些實施例中，一 旦移除光阻，則使用蝕刻製程(諸如濕式蝕刻製程或乾式蝕刻製程)來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成金屬化圖案112。
圖3，介電層114形成於金屬化圖案112及複合層110上。在一些實施例中，介電層114由聚合物形成，所述聚合物可為可使用微影罩幕來圖案化的感光性材料，諸如PBO、聚醯亞胺、BCB或類似者。在其他實施例中，介電層114由諸如氮化矽的氮化物、諸如氧化矽的氧化物、PSG、BSG、BPSG或類似者形成。介電層114可藉由旋轉塗佈、疊層、CVD、類似者或其組合來形成。使介電層114圖案化以暴露金屬化圖案112的部分。介電層114可使用可接受的製程來圖案化，諸如當介電層114為感光性材料時藉由使介電層114暴露於光來圖案化。在一些實施例中，介電層114可使用蝕刻罩幕及適合的蝕刻製程(諸如非等向性蝕刻製程)來圖案化。在一些實施例中，使用類似技術，額外金屬化圖案及介電層可形成於金屬化圖案112及介電層114上方的堆疊中。
轉向圖4，多個穿孔119形成於金屬化圖案112及介電層114上方。在一些實施例中，穿孔119可藉由以下步驟來形成：在介電層114上方形成晶種層，且接著在晶種層上方形成圖案化光阻，其中圖案化光阻中的多個開口中的每一者對應於待形成的多個穿孔119的位置。使用諸如電鍍或化學鍍的適合技術用諸如銅的導電材料填充介電層114中的開口。接著使用諸如灰化或剝離製程的適合的製程來移除光阻。接著，可使用適合的蝕刻製程來移除晶種層的其上未形成穿孔119的部分。穿孔119可形成為在金屬化圖案112及介電層114之上延伸的導電柱。用於形成穿孔 119的其他技術亦為可能的，且完全意欲包含於本揭露內容的範圍內。
接下來，在圖5中，將半導體晶粒120(亦可稱為晶粒，或積體電路(integrated circuit；IC)晶粒)貼合至介電層114的上部表面。諸如晶粒貼合膜(die attach film；DAF)的黏著膜118可用於將晶粒120貼合至介電層114。晶粒120可使用適合的製程(諸如取放(pick-and-place)製程)來貼合。在一些實施例中，DAF可在貼合晶粒120之後固化。
在黏著至介電層114之前，晶粒120可根據可應用的製造製程來處理以在晶粒120中形成積體電路。舉例而言，晶粒120可包含半導體基底及一或多個上覆金屬化層，在圖5中共同示出為構件121。半導體基底可為例如經摻雜或未經摻雜的矽，或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層。半導體基底可包含其他半導體材料，諸如：鍺；化合物半導體，包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；其組合或類似者。亦可使用其他基底，諸如多層基底或梯度基底。晶粒120可包含形成於半導體基底中及/或所述半導體基底上的元件(未繪示)，諸如電晶體、二極體、電容器、電阻器等，且可由金屬化層內連以形成積體電路。金屬化層可包含半導體基底上方的一或多個介電層中的金屬化圖案(例如，作為重佈線結構)。
晶粒120更包括墊126(例如，接觸墊、鋁墊或類似者)，外部連接可與所述墊進行連接。墊126可位於晶粒120的前側(例 如，「主動側」)上。鈍化膜127可在晶粒120的前側上方及墊126的部分上形成。可形成穿過鈍化膜127延伸至墊126的開口。晶粒連接件128延伸至鈍化膜127的開口中，且機械耦接及電耦接至各別墊126。晶粒連接件128可為例如導電墊或導電柱。晶粒連接件128可包括一或多種導電材料(諸如銅)，且可使用諸如鍍覆的適合的製程來形成。晶粒連接件128電耦接至晶粒120的元件及/或積體電路。
介電材料129形成於晶粒120的主動側處，諸如鈍化膜127及/或晶粒連接件128上。介電材料129側向密封晶粒連接件128，且介電材料129與晶粒120側向共端。介電材料129可為聚合物，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯環丁烷(benzocyclobutene；BCB)；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽；磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)、組合或類似者。介電材料129可例如藉由旋轉塗佈、疊層、CVD或類似者形成。
接下來，在圖6中，模製材料130形成於介電層114上方。模製材料側向包圍晶粒120且側向包圍穿孔119，使穿孔119與晶粒120分隔開且使多個穿孔119彼此分隔開。作為實例，模製材料130可包括環氧樹脂、有機聚合物、添加或不添加矽石類或玻璃填充劑之聚合物或其他材料。在一些實施例中，模製材料130包括在塗敷時為凝膠型液體之液體模製化合物(liquid molding compound；LMC)。模製材料130在塗敷時亦可包括液體或固體。替代性地，模製材料130可包括其他絕緣或密封材料。模製材料 130在一些實施例中使用晶圓級模製製程來塗敷。模製材料130可使用例如壓縮模製、轉移模製或其他技術來模製。
在一些實施例中，模製材料130可使用固化製程來固化。固化製程可包括使用退火製程或其他加熱製程將模製材料130加熱至預定溫度持續預定時間段。固化製程亦可包括紫外(UV)暴露製程、紅外(IR)能量暴露製程、其組合或類似者。替代性地，可使用其他技術來固化模製材料130。在一些實施例中，不執行固化製程。
仍參看圖6，可任選地執行平坦化製程，諸如化學機械研磨(chemical-mechanical polish；CMP)，以移除晶粒120的前側上方的模製材料130的過剩部分。在平坦化製程之後，模製材料130、穿孔119以及晶粒連接件128可具有共面的頂部表面。
接下來參看圖7及圖8，根據一些實施例，重佈線結構140形成於模製材料130、穿孔119以及晶粒120的前側上方。重佈線結構140包括形成於一或多個介電層(例如，介電層148)中的一或多個導電特徵層(例如，包含導電線143、通孔145以及類似者的金屬化圖案)。
在一些實施例中，一或多個介電層(例如，介電層148)由聚合物(諸如聚苯并噁唑(PBO)、聚醯亞胺、苯環丁烷(BCB)、感光性聚合物或類似者)形成。在一些實施例中，介電層中的一或多者可包含其他材料，諸如氮化物(例如，氮化矽)、氧化物(例如，氧化矽)、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻磷矽酸鹽玻璃(BPSG)或類似者。一或多個介電層可藉由適合的沈積製程形成，所述沈積製程諸如旋轉塗佈、化學氣相沈積 (CVD)、疊層、類似者或其組合。
在圖7中，介電層148形成於模製材料130、穿孔119以及晶粒120的前側上方，且接著圖案化。圖案化形成多個開口以暴露穿孔119的部分及晶粒120的晶粒連接件128的部分。介電層148可使用可接受的製程來圖案化，諸如藉由當介電層148為感光性材料時使介電層148暴露於光，且在暴露之後使介電層148顯影以形成開口。介電層148亦可藉由使用例如非等向性蝕刻進行蝕刻來圖案化。
仍參看圖7，包含導電線143及通孔145的金屬化圖案形成於介電層148上。在一些實施例中，晶種層(未繪示)首先形成於介電層148上方及穿過介電層148的開口中。在一些實施例中，晶種層為金屬層，所述金屬層可為包括由不同材料形成的多個子層的單層或複合層。在一些實施例中，晶種層包括鈦層及鈦層上方的銅層。可使用例如PVD或類似者來形成晶種層。接著，在晶種層上形成光阻並圖案化光阻。光阻可藉由旋轉塗佈或類似者來形成，且可暴露於光以用於圖案化。光阻的圖案對應於金屬化圖案。圖案化形成穿過光阻的開口以暴露晶種層。導電材料在光阻的開口中及晶種層的暴露部分上形成。導電材料可藉由鍍覆，諸如電鍍或化學鍍或類似者形成。導電材料可包括金屬，如銅、鈦、鎢、鋁或類似者。在形成導電材料之後，移除光阻及晶種層的其上未形成導電材料的部分。可藉由可接受的灰化或剝離製程，諸如使用氧電漿或類似者來移除光阻。一旦移除光阻，則例如使用可接受的蝕刻製程(諸如濕式蝕刻製程或乾式蝕刻製程)來移除晶種層的暴露部分。晶種層的剩餘部分及導電材料形成導 電線143及通孔145。通孔145形成於穿過介電層148的開口中以與介電層下的特徵進行電連接，所述特徵諸如穿孔119及/或晶粒連接件128。
轉向圖8，可在介電層148及導電線143上方形成額外介電層(未單獨標記)及額外導電特徵(未單獨標記)，從而形成重佈線結構140。額外介電層可與介電層148類似，且額外導電特徵可與導電線143及通孔145類似。額外介電層或額外導電特徵可與介電層148或導電線143及通孔145類似地形成。舉例而言，導電特徵可藉由以下步驟形成：在重佈線結構140的介電層中形成開口以暴露底層導電特徵；在介電層上方及開口中形成晶種層(未繪示)；在晶種層上方形成具有經設計圖案的圖案化光阻(未繪示)；將導電材料鍍覆(例如，電鍍或化學鍍)於經設計圖案中及晶種層上方；以及移除光阻及晶種層的其上未形成導電材料的部分。形成重佈線結構140的其他方法亦為可能的且完全意欲包含於本揭露內容的範圍內。
圖8的重佈線結構140中的介電層的數目及導電特徵層的數目僅為非限制性實例。介電層的其他數目及導電特徵層的其他數目亦為可能的且完全意欲包含於本揭露內容的範圍內。
圖8亦示出凸塊下金屬化(under bump metallization；UBM)結構147，其形成於重佈線結構140上方且電耦接至所述重佈線結構。在一些實施例中，UBM結構147藉由首先在重佈線結構140的最頂部介電層中形成開口以暴露重佈線結構140的導電特徵(例如，導電線或導電墊)來形成。在開口形成之後，UBM結構147可形成為與暴露的導電特徵處於電接觸。在實施例中， UBM結構147包括三個導電材料層，諸如鈦層、銅層以及鎳層。然而，存在諸多適合的材料及層的配置，諸如鉻/鉻銅合金/銅/金的配置，鈦/鈦鎢/銅的配置，或銅/鎳/金的配置，所述配置適用於形成UBM結構147。可用於UBM結構147的任何適合的材料或材料層完全意欲包含於本揭露內容的範圍內。
UBM結構147可藉由以下步驟形成：在最頂部介電層(例如，介電層142)上方及沿最頂部介電層中的開口的內部形成晶種層；在晶種層上方形成圖案化罩幕層(例如，光阻)；在圖案化罩幕層的開口中及晶種層上方(例如，藉由電鍍)形成導電材料；移除罩幕層且移除晶種層的其上未形成導電材料的部分。用於形成UBM結構147的其他方法為可能的且完全意欲包含於本揭露內容的範圍內。圖4中的UBM結構147的上部表面僅作為實例而示出為平面的，UBM結構147的上部表面可以不為平面的。舉例而言，各UBM結構147的部分(例如，外圍部分)可形成於最頂部介電層(例如，介電層142)上方，且各UBM結構147的其他部分(例如，中心部分)可沿著對應開口所暴露的最頂部介電層的側壁共形地形成，如所屬技術領域中具有通常知識者所容易瞭解。
接下來，在圖9中，根據一些實施例，電氣元件171貼合至UBM結構147，且連接件155形成於結構147上方。電氣元件171可為元件、晶粒、晶片或封裝體，諸如積體被動元件(integrated passive device；IPD)或類似者。電氣元件171藉由導電連接件173經由UBM結構147電耦接至重佈線結構140。導電連接件173可為例如形成於電氣元件171與重佈線結構140之間的焊料連接件。導電連接件173可包括與連接件155相同的材料 (例如，焊料)(參見下文)。在一些實施例中，在置放電氣元件171之前，可使焊劑(flux material)(未繪示)沈積於相關聯的UBM結構147上。電氣元件171可使用例如取放製程來置放。另外，底填充材料175可形成於電氣元件171與重佈線結構140之間的間隙中。電氣元件171為選擇性的，且可不包含於一些實施例中。
仍參看圖9，連接件155可為焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊、微型凸塊、化學鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique；ENEPIG)形成的凸塊、其組合(例如，具有貼合至其的焊料球的金屬柱)或類似者。連接件155可包含導電材料，諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其組合。在一些實施例中，作為實例，連接件155包括共晶材料，且可包括焊料凸塊或焊料球。舉例而言，焊料材料可為鉛類及無鉛焊料，諸如鉛類焊料的Pb-Sn組成物、包含InSb的無鉛焊料；錫、銀以及銅(SAC)組成物；以及具有共同熔點且在電氣應用中形成導電焊料連接的其他共晶材料。對於無鉛焊料，作為實例，可使用不同組成物的SAC焊料，諸如SAC 105(98.5%的Sn、1.0%的Ag、0.5%的Cu)、SAC 305以及SAC 405。諸如焊球的無鉛連接件亦可由SnCu化合物形成，而無需使用銀(Ag)。替代性地，無鉛焊料連接件可包含錫及銀(Sn-Ag)，而無需使用銅。連接件155可形成柵，諸如球柵陣列封裝(ball grid array；BGA)。在一些實施例中，可執行回焊製程，從而在一些實施例中給予連接件155部分球面的形狀。在一些情況下，可對導電連接件173及連接件155兩者執行回焊製程。替代性地，連接件155可包括其他形 狀。舉例而言，連接件155亦可包括非球面導電連接件。在一些實施例中，在形成連接件155之前，焊劑(未繪示)可在相關聯的UBM結構147上方形成。
在一些實施例中，連接件155包括金屬柱(諸如銅柱)，所述金屬柱可藉由濺鍍、列印、電鍍、化學鍍、CVD或類似者形成，且可在其上形成有或未形成有焊料材料。金屬柱可不含焊料，且具有實質上豎直的側壁或錐形側壁。
圖9中所繪示的結構為形成於載體101上方的單個元件封裝體1100。所屬技術領域中具有通常知識者將瞭解，諸多封裝體(例如，元件封裝體1100)可使用如圖1至圖9中所示出的類似處理步驟來形成於載體基底(例如，載體101)上方。根據一些實施例，圖10至圖14示出對圖9的半導體封裝體1100的進一步處理。圖10至圖14的處理使用形成於載體101上方的兩個元件封裝體(例如，元件封裝體1100A及元件封裝體1100B)來繪示，應瞭解，在其他實施例中，可在載體101上方形成大於兩個元件封裝體。
圖10示出根據一些實施例的包括元件封裝體1100A及元件封裝體1100B的結構。元件封裝體1100A及元件封裝體1100B分別形成於載體101上方的區域100及區域200中。元件封裝體1100A及元件封裝體1100B中的每一者可與圖9中所示出的元件封裝體1100類似。
轉向圖11，根據一些實施例，翻轉圖10中所繪示的結構，且外部連接件155貼合至由框架157支撐的載帶159(例如，切割帶)。接下來，藉由適合的製程(諸如蝕刻、磨削(grinding)或 機械剝除(peel off))將載體101自複合層110剝離。在黏著層(例如，LTHC膜)形成於載體101與複合層110之間的一些實施例中，可藉由使載體101暴露於雷射或UV光來剝離載體101。雷射或UV光使黏著層的將所述黏著層黏合至載體101的化學鍵斷裂，且接著可拆卸載體101。可藉由載體剝離製程移除黏著層。在剝離載體101之後，可在複合層110上執行清潔製程以移除(例如，來自黏著層的)任何殘餘物。
轉向圖12，根據一些實施例，在剝離載體101之後，多個開口116形成於複合層110中以暴露金屬化圖案112。在一些實施例中，複合層110中的開口116可使用諸如雷射鑽孔製程、蝕刻製程或類似者的適合的製程來形成。在一些實施例中，蝕刻製程為電漿蝕刻製程。在一些實施例中，在形成開口116之後執行清潔製程以便移除(例如，來自雷射鑽孔製程的)任何殘餘物。儘管未繪示，但焊錫膏可形成於開口116中，準備用於貼合頂部封裝體(參見圖13)。焊錫膏可使用焊錫膏列印製程或另一適合的製程來形成。
接下來參看圖13，根據一些實施例，將頂部封裝體160貼合至元件封裝體1100以形成封裝結構500。在圖13中，實例頂部封裝體160A及實例頂部封裝體160B分別繪示為貼合至實例元件封裝體1100A及實例元件封裝體1100B，以形成實例封裝結構500A及實例封裝結構500B。在一些實施例中，封裝結構500可為疊層封裝體(PoP)或積體扇出(InFO-PoP)型結構。
如圖13中所示出，多個頂部封裝體160(例如，頂部封裝體160A、頂部封裝體160B)中的每一者包括基底161及貼合至 基底161的上部表面的一或多個半導體晶粒162(例如，記憶體晶粒)。在一些實施例中，基底161包含矽、砷化鎵、絕緣體上矽(「silicon on insulator；SOI」)、類似者或組合。在一些實施例中，基底161為多層電路板。在一些實施例中，基底161由一或多種材料形成，諸如雙馬來亞醯胺三嗪(bismaleimide triazine；BT)樹脂、FR-4(由編織玻璃纖維布與耐火環氧樹脂黏合劑構成的複合材料)、陶瓷、玻璃、塑膠、載帶、膜或其他支撐材料。基底161可包含形成於基底161中或所述基底上的導電特徵(例如，導電線及通孔，未繪示)。如圖13中所示出，基底161可具有形成於基底161的上部表面及下部表面上的多個導電墊163。導電墊163電耦接至基底161的導電特徵，諸如穿孔或導電線。一或多個半導體晶粒162藉由例如接合線167電耦接至導電墊163。可包括環氧樹脂、有機聚合物、聚合物、密封體或類似者的模製材料165形成於基底161上方及半導體晶粒162周圍。在一些實施例中，如圖13中所示出，模製材料165與基底161相接。
仍參看圖13，頂部封裝體160可藉由導電墊163上的導電連接件168連接至元件封裝體1100。導電連接件168在元件封裝體1100的金屬化圖案112與頂部封裝體160的導電墊163之間進行電連接。在一些實施例中，焊料材料170沈積於經由複合層110中的開口暴露的金屬化圖案112上方。導電連接件168貼合至焊料材料170。在一些實施例中，導電連接件168包括焊料區域、導電柱(例如，在至少銅柱的末端表面上具有焊料區域的銅柱)或類似者。在一些實施例中，執行回焊製程以接合焊料材料170與導電連接件168。在回焊製程之後，可執行烘烤製程以移除水分。
底填充材料169可接著形成於頂部封裝體160與對應的底部封裝體1100之間的間隙中。底填充材料169可使用例如針或噴射施配器施配於頂部封裝體160與元件封裝體1100之間的間隙中。在一些實施例中，可執行固化製程以固化底填充材料169。儘管圖13中未繪示，但底填充材料169可在多個頂部封裝體160的多個側壁之間或沿所述多個側壁延伸。
接下來，在圖14中，執行單體化製程以將封裝結構500(例如，封裝結構500A、封裝結構500B)分隔成多個單個封裝結構。在完成單體化製程之後，形成多個單個封裝結構，諸如圖14中所示出的封裝結構500。單體化製程可例如使用鋸切製程、雷射製程、另一適合的製程或製程的組合。
在一些情況下，將複合材料用於複合層110(先前關於圖1描述)可提供諸如封裝結構500的封裝體的經改良剛性。在封裝體(例如，封裝結構500)中使用複合層110可減少封裝體的翹曲，諸如減少元件結構1100的翹曲及/或減少整個封裝結構500的翹曲。舉例而言，在一些情況下，重佈線結構(例如，重佈線結構140)可在封裝體上施加彎曲力，此導致封裝體翹曲或彎曲。複合層110的剛性可減輕因此等彎曲力而導致的翹曲，且因此減少封裝體的總體翹曲。在一些情況下，使用複合層(諸如複合層110)可將翹曲封裝體的彎曲距離(bending distance)減小到約0微米與約250微米之間。在一些情況下，使用複合層110可允許封裝結構具有小於約200微米的彎曲距離，諸如小於約80微米或小於約10微米。在一些情況下，使用複合層(諸如複合層110)可將封裝體的翹曲減少到約50%與約100%之間。在一些實施例中，可 藉由將複合層110及重佈線結構140安置於晶粒120的相對側上來提高翹曲的減少。
轉向圖15A至圖15D，根據一些實施例繪示複合層110的表面的示例性近距離視圖。圖15A示出在圖14中標記為「A」的區域的近距離視圖，其中底填充材料169已沈積於複合層110上方。如圖15A中所繪示，複合層110具有有凹痕的表面(亦關於圖1在上文描述)。複合層110的有凹痕的表面可提供底填充材料169的改良黏著力，此可改良封裝結構的總體剛性且減小分層的機率。圖15B示出在圖14中標記為「B」的區域的近距離視圖，其包含複合層110的側壁。如圖15B中所繪示，複合層110的側壁亦具有有凹痕的表面，此可改良沈積於封裝結構500上的其他材料(例如，模製化合物、密封體或類似者，其未在圖式中繪示)的黏著力。圖15C至圖15D示出在圖14中標記為「C」的區域的近距離視圖，其包含複合層110中的開口，焊料材料170延伸穿過所述開口(先前關於圖12描述)。圖15C繪示具有錐形開口的複合層110，且圖15D繪示具有實質上垂直開口的複合層，但在其他實施例中，開口可具有其他形狀。如圖15C至圖15D中所繪示，開口的側壁可為有凹痕的，且焊料材料170可在沈積期間或在回焊製程期間流入凹痕中。以此方式，焊料材料170可具有對應於開口的側壁中的凹痕的「凸塊」。在一些情況下，凹痕可提供焊料材料170對複合層110的更佳黏著力。此外，在一些情況下，開口內的焊料材料170的因凹痕的存在而增大的體積可減小焊料材料170的電阻，且因此改良封裝結構500的電氣效能。
接下來參看圖16，根據一些實施例繪示封裝結構600。 封裝結構600包含頂部封裝體160，其可與先前描述的頂部封裝體160類似(參見圖13)。頂部封裝體160貼合至元件封裝體1200以形成封裝結構600。元件封裝體1200與先前描述的元件封裝體1100類似(參見圖9)，但介電層114及金屬化圖案112未形成於複合層110上方(參見圖3)。因此，穿孔119及模製材料130直接形成於複合層110上。模製材料130的部分可延伸至複合層110的有凹痕的表面的凹痕中。在一些情況下，複合層110的有凹痕的表面可提供模製材料130的改良的黏著力。形成具有複合層110的封裝結構的此等及其他變體意欲在本揭露內容的範圍內。
實施例可達成優點。藉由在包括複合材料(例如，聚合物及填充劑)的層中形成具有導電構件(例如，焊料材料170)的封裝體，可改良封裝體的剛性。以此方式，可減少封裝體的翹曲，且因此可減少與翹曲相關聯的諸如破裂或分層的問題。此外，複合材料可形成具有有凹痕的表面的層，此可改良其他層對複合材料的黏著力，因此進一步改良封裝體的可靠性及穩定性。
在實施例中，一種方法包含：在載體上方形成複合材料層，複合材料層包含併入至基礎材料中的填充物材料的多個顆粒；在複合材料層的第一側上方形成穿孔集合；在複合材料層的第一側上方貼合晶粒，晶粒與穿孔集合間隔開；在複合材料層的第一側上方形成模製材料，模製材料至少側向密封晶粒及穿孔集合中的多個穿孔；在晶粒及模製材料上方形成重佈線結構，重佈線結構電連接至多個穿孔；在複合材料層的與第一側相對的第二側中形成多個開口；以及在多個開口中形成多個導電連接件，多個導電連接件電連接至多個穿孔。在實施例中，填充物材料的多 個顆粒具有0.5微米與30微米之間的平均直徑。在實施例中，基礎材料包含聚合物。在實施例中，填充物材料包含氧化物。在實施例中，方法包含：在複合材料層上方形成介電層，其中介電層的材料不同於複合材料層的材料，且其中穿孔集合形成於介電層上。在實施例中，方法包含：在複合材料層上形成介電層之前，在複合材料層上形成金屬化圖案。在實施例中，在複合材料層的第二側中形成多個開口包含雷射鑽孔製程。在實施例中，在複合材料層的第二側中的多個開口具有多個有凹痕的側壁。在實施例中，多個導電連接件包含焊料材料，其中複合材料層內的多個導電連接件的多個側壁包含側向延伸至複合材料層中的多個凸塊。在實施例中，模製材料實體地接觸複合材料層的第一側。在實施例中，晶粒實體地貼合至複合材料層的第一側。
在實施例中，一種方法包含：形成元件封裝體，其中形成元件封裝體包含：在複合層的第一表面上形成金屬化圖案，其中複合層包含複合材料且其中第一表面是有凹痕的；在複合層及金屬化圖案上方形成第一介電層；在第一介電層上方形成導電柱且導電柱電連接至金屬化圖案；在第一介電層上置放第一半導體元件，其中第一半導體元件與導電柱相鄰且與導電柱分隔開；用密封體密封第一半導體元件及導電柱；以及在密封體上方形成重佈線結構；在複合層的第二表面中形成多個開口以暴露金屬化圖案；以及使用多個導電連接件將頂部封裝體貼合至元件封裝體，其中多個導電連接件延伸穿過複合層中的多個開口。在實施例中，複合層具有10GPa與50GPa之間的楊氏模數。在實施例中，方法包含：在元件封裝體與頂部封裝體之間沈積底填充料，底填 充料包圍多個導電連接件，其中底填充料延伸至複合層的有凹痕的頂部表面的多個凹痕中。在實施例中，元件封裝體具有小於80微米的彎曲距離。在實施例中，方法包含：使元件封裝體單體化，其中元件封裝體的側壁表面包括多個凹痕。在實施例中，複合層包含併入至聚合材料中的氧化鋁。
在實施例中，一種半導體封裝體包含：下部封裝體，包含：晶粒，位於重佈線結構上，晶粒電連接至重佈線結構；穿孔，靠近晶粒且電連接至重佈線結構；模製材料，位於重佈線結構上方，模製材料插入於晶粒與穿孔之間；以及複合層，位於晶粒及穿孔上方，複合層在晶粒的與重佈線結構相對的一側上方；以及頂部封裝體，包括多個外部連接件，其中外部連接件經由複合層連接至下部封裝體。在實施例中，複合層的暴露側壁具有有凹痕的表面。在實施例中，半導體封裝體包含在複合層與頂部封裝體之間延伸的底填充材料，其中底填充材料與複合層之間的介面為包含多個有凹痕的區域的表面。
前文概述若干實施例的特徵以使得所屬技術領域中具有通常知識者可更佳地理解本揭露內容的態樣。所屬技術領域中具有通常知識者應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範圍，且所屬技術領域中具有通常知識者可在不脫離本揭露內容的精神及範圍的情況下在本文中作出改變、替代以及更改。
101:載體
103:釋放層
110:複合層
112:金屬化圖案
114:介電層
119:穿孔
120:半導體晶粒
130:模製材料
140:重佈線結構
147:凸塊下金屬化結構
155:連接件
171:電氣元件
173:導電連接件
175:底填充材料
1100:元件封裝體

Claims (10)

  1. 一種形成半導體封裝體的方法，包括：在載體上方形成複合材料層，所述複合材料層包括併入至基礎材料中的填充物材料的多個顆粒；在所述複合材料層的第一側上方形成穿孔集合；在所述複合材料層的所述第一側上方貼合晶粒，所述晶粒與所述穿孔集合間隔開；在所述複合材料層的所述第一側上方形成模製材料，所述模製材料至少側向密封所述晶粒及所述穿孔集合中的所述多個穿孔；在所述晶粒及所述模製材料上方形成重佈線結構，所述重佈線結構電連接至所述多個穿孔；在所述複合材料層的與所述第一側相對的第二側中形成多個開口；以及在所述多個開口中形成多個導電連接件，所述多個導電連接件電連接至所述多個穿孔。
  2. 如申請專利範圍第1項所述的方法，更包括在所述複合材料層上方形成介電層，其中所述介電層的材料不同於所述複合材料層的材料，且其中所述穿孔集合形成於所述介電層上。
  3. 如申請專利範圍第2項所述的方法，更包括在所述複合材料層上形成所述介電層之前，在所述複合材料層上形成金屬化圖案。
  4. 如申請專利範圍第1項所述的方法，其中所述複合材料層的所述第二側中的所述多個開口具有多個有凹痕的側壁，其中 所述多個有凹痕的側壁是經由所述填充物材料的所述多個顆粒當中的暴露部分自所述基礎材料脫落或移除而形成。
  5. 如申請專利範圍第1項所述的方法，其中所述多個導電連接件包括焊料材料，其中所述複合材料層內的所述多個導電連接件的多個側壁包括側向延伸至所述複合材料層中的多個凸塊。
  6. 如申請專利範圍第1項所述的方法，其中所述模製材料實體地接觸所述複合材料層的所述第一側。
  7. 一種形成半導體封裝體的方法，包括：形成元件封裝體，其中形成所述元件封裝體包括：在複合層的第一表面上形成金屬化圖案，其中所述複合層包括複合材料且其中所述第一表面是有凹痕的；在所述複合層的所述第一表面上形成所述金屬化圖案之後，在所述複合層及所述金屬化圖案上方形成第一介電層；在所述第一介電層上方形成導電柱且所述導電柱電連接至所述金屬化圖案；在所述第一介電層上置放第一半導體元件，其中所述第一半導體元件與所述導電柱相鄰且與所述導電柱分隔開；用密封體密封所述第一半導體元件及所述導電柱；以及在所述密封體上方形成重佈線結構；在所述複合層的第二表面中形成多個開口以暴露所述金屬化圖案；以及使用多個導電連接件將頂部封裝體貼合至所述元件封裝體，其中所述多個導電連接件延伸穿過所述複合層中的所述多個開口。
  8. 如申請專利範圍第7項所述的方法，更包括在所述元件封裝體與所述頂部封裝體之間沈積底填充料，所述底填充料包圍所述多個導電連接件，其中所述底填充料延伸至所述複合層的有凹痕的頂部表面的多個凹痕中。
  9. 一種半導體封裝體，包括：下部封裝體，包括：晶粒，位於重佈線結構上，所述晶粒電連接至重佈線結構；穿孔，靠近所述晶粒且電連接至所述重佈線結構；模製材料，位於所述重佈線結構上方，所述模製材料插入於所述晶粒與所述穿孔之間；以及複合層，位於所述晶粒及所述穿孔上方，所述複合層在所述晶粒的與所述重佈線結構相對的一側上方；以及頂部封裝體，包括多個外部連接件，其中所述多個外部連接件經由所述複合層連接至所述下部封裝體。
  10. 如申請專利範圍第9項所述的半導體封裝體，其中所述複合層的暴露側壁具有有凹痕的表面，其中所述複合層的所述暴露側壁與所述模製材料的側壁實質上對準。
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TW201820571A (zh) * 2016-11-29 2018-06-01 台灣積體電路製造股份有限公司 具有虛設晶粒的扇出型封裝結構
TW201824488A (zh) * 2016-11-29 2018-07-01 台灣積體電路製造股份有限公司 封裝結構

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