TWI695438B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI695438B
TWI695438B TW108115243A TW108115243A TWI695438B TW I695438 B TWI695438 B TW I695438B TW 108115243 A TW108115243 A TW 108115243A TW 108115243 A TW108115243 A TW 108115243A TW I695438 B TWI695438 B TW I695438B
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Taiwan
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dielectric layer
die
layer
encapsulant
hydroxylated
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TW108115243A
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TW202002110A (zh
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潘國龍
張志鴻
郭鴻毅
蔡豪益
郭庭豪
羅登元
淑蓉 鄭
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台灣積體電路製造股份有限公司
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Abstract

在實施例中，一種裝置包括：第一重佈線結構，包括第 一介電層；晶粒，黏附至第一重佈線結構的第一側；包封體，橫向地包封晶粒，包封體用第一共價鍵接合至第一介電層；穿孔，延伸穿過包封體；以及第一導電連接件，電性連接至第一重佈線結構的第二側，第一導電連接件的子集和包封體與晶粒的介面交疊。

Description

半導體裝置及其形成方法
本發明實施例是有關於一種半導體裝置及其形成方法。
由於各種電子組件(例如，電晶體、二極體、電阻器、電容器等)積體密度持續提高，半導體行業經歷了快速發展。在很大程度上，積體密度提高起因於最小特徵大小(minimum feature size)的重複減小，此使得更多組件能夠被整合於給定區域中。隨著縮小電子裝置需求的增長，更小且更具創作性的半導體晶粒封裝技術的需求浮現。此種封裝系統的實例是疊層封裝(Package-on-Package，PoP)技術。在PoP裝置中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高積體程度及高組件密度。PoP技術一般而言能夠生產功能得到增強且在印刷電路板(printed circuit board，PCB)上佔用面積小的半導體裝置。
本發明實施例提供一種半導體裝置，包括第一重佈線結 構、晶粒、包封體、穿孔以及第一導電連接件。所述第一重佈線結構包括第一介電層。所述晶粒黏附至所述第一重佈線結構的第一側。所述包封體橫向地包封所述晶粒，所述包封體用第一共價鍵接合至所述第一介電層。所述穿孔延伸穿過所述包封體。所述第一導電連接件電性連接至所述第一重佈線結構的第二側，所述第一導電連接件的子集與所述包封體與所述晶粒的介面交疊。
本發明實施例提供一種半導體裝置的形成方法，包括以下步驟。在第一金屬化圖案之上形成第一介電層。形成延伸穿過所述第一介電層的穿孔，所述穿孔電性連接至所述第一金屬化圖案。將晶粒黏附至所述第一介電層的第一表面。用第一共價鍵將包封體接合至所述第一介電層的所述第一表面，所述包封體橫向地包封所述晶粒及所述穿孔。在所述包封體之上形成第二介電層。形成延伸穿過所述第二介電層的第二金屬化圖案，所述第二金屬化圖案電性連接至所述晶粒及所述穿孔。
本發明實施例提供一種半導體裝置的形成方法，包括以下步驟。用晶種層對穿過第一介電層的穿孔進行鍍覆。對所述晶種層的被暴露出的部分進行蝕刻，在對所述晶種層進行蝕刻之後保留所述晶種層的殘餘金屬。對所述第一介電層的第一表面進行處理以對所述第一表面進行羥基化並自所述第一表面移除所述晶種層的所述殘餘金屬。將晶粒黏附至經羥基化的所述第一表面。用第一共價鍵將包封體接合至經羥基化的所述第一表面，所述包封體橫向地包封所述晶粒及所述穿孔。在所述包封體及所述晶粒 之上形成第二介電層。
10、12、14、16、18:區
100A:第一封裝區
100B:第二封裝區
102:載體基底
104:釋放層
106:背側重佈線結構
108、112、146、148、150、152:介電層
110、154、156、158:金屬化圖案
110A、110B、134:墊
114、166:開口
116:穿孔
116A:晶種層
116B:導電材料
118:凹坑
120:殘餘金屬
122、124:表面處理製程
126:積體電路晶粒
128:黏合劑
130:半導體基底
132:內連結構
136:鈍化膜
138:晶粒連接件
140:介電材料
142:包封體
144:前側重佈線結構
160:凸塊下金屬
162、314:導電連接件
164:膠帶
200:第一封裝
300:第二封裝
302:基底
303、304、402:接合墊
306:導通孔
308A、308B:晶粒
310:導線接合件
312:模塑材料
316:底部填充物
400:封裝基底
500:封裝結構
D1、D2、D3、D4、D5、D6、D7:距離
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖12示出根據一些實施例的形成裝置封裝的製程期間的中間步驟的剖視圖。
圖13A至圖14示出根據一些實施例的形成封裝結構的製程期間的中間步驟的剖視圖。
以下揭露內容提供用於實施本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例而不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵，進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複參考編號及/或字母。此種重複是出於簡潔及清晰的目的，而不是自身表示所論述的各種實 施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例，在背側重佈線結構上形成封裝之前，利用若干表面處理製程對所述背側重佈線結構的最頂部介電層進行清潔。所述表面處理製程可減少嵌置於最頂部介電層中的殘餘金屬量。殘餘金屬可為來自例如形成於最頂部介電層上的晶種層的金屬殘留物。所述表面處理製程亦可對最頂部介電層進行羥基化。隨後形成的模塑化合物包含親核劑，所述親核劑與經羥基化的表面形成共價鍵。藉由移除殘餘金屬以及與模塑化合物形成共價鍵，所述模塑化合物與所述最頂部介電層之間的介面的強度可增大，此可幫助避免隨後形成的特徵的分層(delamination)。各特徵可因此形成於所述封裝的經受更高的機械應變的區中。
圖1至圖12示出根據一些實施例的在形成第一封裝200(參見圖12)的製程期間的中間步驟的剖視圖。圖中示出第一封裝區100A及第二封裝區100B，且在每一封裝區中形成有第一封裝200。第一封裝200亦可被稱為積體扇出型(integrated fan-out， InFO)封裝。
在圖1中，提供載體基底102，且在載體基底102上形成釋放層104。載體基底102可為玻璃載體基底、陶瓷載體基底等。載體基底102可為晶圓，進而使得可在載體基底102上同時形成多個封裝。釋放層104可由聚合物系材料形成，所述聚合物系材料可與載體基底102一起自將在後續步驟中形成的上覆結構被移除。在一些實施例中，釋放層104為當受熱時會失去其黏附性質的環氧樹脂系熱釋放材料，例如光熱轉換(light-to-heat-conversion，LTHC)釋放塗層。在其他實施例中，釋放層104可為當暴露至紫外(ultraviolet，UV)光時會失去其黏附性質的紫外(UV)膠。釋放層104可以液體形態被分配並被固化，可為疊層至載體基底102上的疊層膜(laminate film)或可為類似材料。釋放層104的頂表面可被整平且可具有高的共面程度。
在圖2中，在釋放層104上形成背側重佈線結構106。在所示出的實施例中，背側重佈線結構106包括介電層108、金屬化圖案110(有時被稱為重佈線層或重佈線走線)及介電層112。
在釋放層104上形成介電層108。介電層108的底表面可接觸釋放層104的頂表面。在一些實施例中，介電層108是由例如聚苯並噁唑(polybenzoxazole，PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene，BCB)等聚合物形成。在其他實施例中，介電層108是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸 鹽玻璃(borosilicate glass，BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)等；或者類似材料。介電層108可藉由任何可接受的沉積製程來形成，例如旋轉塗佈(spin coating)、化學氣相沉積(chemical vapor deposition，CVD)、疊層、類似製程、或其組合。
在介電層108上形成金屬化圖案110。作為形成金屬化圖案110的實例，在介電層108之上形成晶種層(未示出)。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積(physical vapor deposition，PVD)等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露於光以進行圖案化。光阻的圖案對應於金屬化圖案110。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆(例如，電鍍或無電鍍覆)等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程(ashing process)或剝除製程(stripping process)來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化 圖案110。
在金屬化圖案110及介電層108上形成介電層112。在一些實施例中，介電層112是由聚合物形成，所述聚合物可為可使用光微影罩幕進行圖案化的感光性材料(例如PBO、聚醯亞胺、BCB等)。在其他實施例中，介電層112是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、PSG、BSG、BPSG；或者類似材料。可藉由旋轉塗佈、疊層、CVD、類似製程、或其組合來形成介電層112。接著將介電層112圖案化以形成開口114來暴露出金屬化圖案110的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層112為感光性材料時將介電層112暴露至光或者藉由使用例如非等向性蝕刻(anisotropic etch)進行蝕刻來進行。在一些實施例中，介電層112是具有高的熱膨脹係數(coefficient of thermal expansion，CTE)的材料，例如聚醯亞胺。在一些實施例中，介電層112具有介於約45ppm/℃至約55ppm/℃範圍內的CTE。
應理解，背側重佈線結構106可包括任何數目的介電層及金屬化圖案。可藉由重複進行形成金屬化圖案110及介電層112的製程來形成附加的介電層及金屬化圖案。金屬化圖案可包括導電線及導通孔。導通孔可在形成金屬化圖案期間藉由在下伏介電層的開口中形成金屬化圖案的晶種層及導電材料來形成。導通孔可因此對各種導電線進行內連及電性耦合。
在圖3A中，在開口114中形成穿孔116，且穿孔116遠 離背側重佈線結構106的最頂部介電層(例如，所示實施例中的介電層112)延伸。圖3B是區10的詳細視圖且結合圖3A進行闡述。作為形成穿孔116的實例，在背側重佈線結構106之上(例如，在介電層112以及金屬化圖案110的被開口114暴露出的部分上)形成晶種層116A。在一些實施例中，晶種層116A是金屬層，可為單層或包括由不同材料形成的多個子層的複合層。在特定實施例中，晶種層116A包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等來形成晶種層116A。在晶種層116A上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於導通孔。所述圖案化會形成穿過光阻的開口以暴露出晶種層116A。在光阻的開口中及在晶種層116A的被暴露出的部分上形成導電材料116B。導電材料116B可藉由鍍覆(例如，電鍍或無電鍍覆等)形成。導電材料116B可包括金屬，例如銅、鈦、鎢、鋁等。移除光阻以及晶種層116A的上面未形成有導電材料116B的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層116A的被暴露出的部分。晶種層116A的剩餘部分與導電材料116B形成穿孔116。
圖3C是在將晶種層116A(參見圖3B)的被暴露出的部分移除之後背側重佈線結構106的區12的詳細視圖。在其中晶種層116A包括鈦層及位於所述鈦層之上的銅層的實施例中，晶種層 116A是藉由PVD製程(例如濺鍍)形成。PVD製程可包括預蝕刻步驟，所述預蝕刻步驟會增大介電層112的頂表面的粗糙度且在介電層112的頂表面中形成凹坑118。在介電層112上對鈦層進行濺鍍時，可向介電層112中植入一些殘餘金屬120(例如，鈦)。具體而言，殘餘金屬120可被陷獲於在介電層112的粗糙頂表面中形成的凹坑118中。
在圖4A中，利用第一表面處理製程122對背側重佈線結構106的最頂部介電層(例如，所示出的實施例中的介電層112)進行清潔。在一些實施例中，第一表面處理製程122包括對介電層112的頂表面進行的蝕刻製程以暴露出被掩埋的殘餘金屬120，且更包括對介電層112的頂表面進行的羥基化製程。舉例而言，在一些實施例中，第一表面處理製程122是電漿處理製程。可用前驅物執行電漿處理製程，所述前驅物在經處理的表面上留下羥基，所述前驅物例如為Ar、O2、N2、CF4、或其組合。在此種實施例中，電漿處理製程可在約25℃至約100℃的溫度(例如約70℃)下執行，且可被執行約30秒至約180秒的時間(例如少於約180秒)。在一些實施例中，前驅物可包括少量H2，例如為約0.1%至約10%的濃度。包括H2可幫助產生電漿，所述電漿移除介電層112的材料。在實施例中，電漿處理製程的前驅物包括O2及H2。如此，電漿處理製程可被認為是乾式蝕刻與表面羥基化的組合。在第一表面處理製程122之後，電漿處理前驅物的一些殘基可保留在介電層112的頂表面上。
圖4B是在第一表面處理製程122之後背側重佈線結構106的區12的詳細視圖。在第一表面處理製程122之後，以距離D1來薄化介電層112，進而使陷獲於介電層112的凹坑118中的殘餘金屬120較第一表面處理製程122之前被更多地暴露出。此外，在第一表面處理製程122之後，在介電層112的頂表面上形成懸空的羥基。
在圖5A中，利用第二表面處理製程124對背側重佈線結構106的最頂部介電層(例如，所示出的實施例中的介電層112)進行清潔。在一些實施例中，第二表面處理製程124會移除被暴露出的殘餘金屬120。在一些實施例中，第二表面處理製程124包括蝕刻製程，例如濕式蝕刻。在實施例中，濕式蝕刻製程的蝕刻劑包括氫氟酸。濕式蝕刻製程可對殘餘金屬120的材料具有選擇性以使介電層112的厚度實質上不減小。在一些實施例中，第二表面處理製程124是移除殘餘金屬120的電漿蝕刻製程。在第二表面處理製程124之後，電漿處理前驅物的一些殘基可保留在介電層112的頂表面上。
圖5B是在第二表面處理製程124之後背側重佈線結構106的區12的詳細視圖。在第二表面處理製程124之後，陷獲於介電層112的凹坑118中的殘餘金屬120被消除或至少其量被減小。
在圖6中，藉由黏合劑128將積體電路晶粒126黏附至介電層112。積體電路晶粒126可為邏輯晶粒(例如，中央處理單 元、微控制器等)、記憶體晶粒(例如，動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒等)、電源管理晶粒(例如，電源管理積體電路(power management integrated circuit，PMIC)晶粒)、射頻(radio frequency，RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、訊號處理晶粒(例如，數位訊號處理(digital signal processing，DSP)晶粒)、前端晶粒(例如，類比前端(analog front-end，AFE)晶粒)、類似晶粒、或其組合。此外，在一些實施例中，積體電路晶粒126可為不同大小(例如，不同高度及/或表面積)，且在其他實施例中，積體電路晶粒126可為相同大小(例如，相同高度及/或表面積)。
在將積體電路晶粒126黏附至介電層112之前，可根據適用於在積體電路晶粒126中形成積體電路的製造製程來對積體電路晶粒126進行處理。舉例而言，積體電路晶粒126各自包括半導體基底130(例如經摻雜或未經摻雜的矽)或絕緣體上半導體(semiconductor-on-insulator，SOI)基底的主動層。半導體基底可包含例如以下其他半導體材料：鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用例如多層式基底或梯度基底(gradient substrate)等其他基底。可在半導體基底130中及/或半 導體基底130上形成例如電晶體、二極體、電容器、電阻器等裝置且可藉由由例如位於半導體基底130上的一或多個介電層中的金屬化圖案形成的內連結構132而使各所述裝置內連以形成積體電路。
積體電路晶粒126更包括與外部連接的墊134(例如，鋁墊)。墊134位於可被稱為積體電路晶粒126的相應主動側的位置上。積體電路晶粒126上及墊134的一些部分上具有鈍化膜136。開口延伸穿過鈍化膜136到達墊134。晶粒連接件138(例如，導電柱(例如，包含例如銅等金屬))延伸穿過鈍化膜136中的開口並且機械地且電性地耦合至相應的墊134。晶粒連接件138可藉由例如鍍覆等來形成。晶粒連接件138電性耦合積體電路晶粒126的相應的積體電路。
在積體電路晶粒126的主動側上，例如在鈍化膜136及晶粒連接件138上具有介電材料140。介電材料140橫向地包封晶粒連接件138，且介電材料140橫向地鄰接相應的積體電路晶粒126。介電材料140可為：聚合物，例如PBO、聚醯亞胺、BCB等；氮化物，例如氮化矽等；氧化物，例如氧化矽、PSG、BSG、BPSG等；類似材料或其組合，且可例如藉由旋轉塗佈、疊層、CVD等來形成。
黏合劑128位於積體電路晶粒126的背側上且將積體電路晶粒126黏附至背側重佈線結構106(例如，介電層112)。黏合劑128可為任何適合的黏合劑、環氧樹脂、晶粒貼合膜(die attach film，DAF)等。在實施例中，黏合劑128包括親核添加劑。所述親核添加劑可為任何親核劑，例如乙二醇、2-乙氧基乙醇或乙醇胺鹽酸鹽等。在實施例中，黏合劑128是具有親核劑的環氧樹脂。黏合劑128可被施加至積體電路晶粒126的背側或者可被施加於載體基底102的表面之上。舉例而言，可在進行單體化以將積體電路晶粒126分開之前將黏合劑128施加至積體電路晶粒126的背側。
儘管圖中示出在第一封裝區100A及第二封裝區100B中的每一者中黏附有一個積體電路晶粒126，然而應理解，在每一封裝區中可黏附有更多的積體電路晶粒126。舉例而言，在每一區中可黏附有多個積體電路晶粒126。此外，積體電路晶粒126的大小可變化。在一些實施例中，積體電路晶粒126可為具有大的佔用面積的晶粒(例如，系統晶片(system-on-chip，SoC)裝置)。在其中積體電路晶粒126具有大的佔用面積的實施例中，封裝區中可供用於穿孔116的空間可為有限的。使用背側重佈線結構106使得能夠在封裝區具有有限的可供用於穿孔116的空間時實現改善的內連排列方式。
在圖7A中，在各種組件上形成包封體142。在包封體142形成之後，包封體142橫向地包封穿孔116及積體電路晶粒126。包封體142可為模塑化合物、環氧樹脂等。包封體142的CTE可相似於介電層112的CTE，此可減少CTE失配(mismatch)，進而減少翹曲。在一些實施例中，包封體142具有介於約10ppm/℃至 約65ppm/℃範圍內的CTE。在實施例中，包封體142包括親核添加劑。所述親核添加劑可為任何親核劑，例如乙二醇、2-乙氧基乙醇或乙醇胺鹽酸鹽等。所述親核添加劑可與黏合劑128中的親核添加劑相同。包封體142可藉由壓縮模塑(compression molding)、轉移模塑(transfer molding)等施加，且可形成於載體基底102之上以使得穿孔116及/或積體電路晶粒126被掩埋或被覆蓋。接著將包封體142固化。
圖7B是將包封體142固化之後包封體142的區14的詳細視圖。亦可將黏合劑128固化。在所述固化之後，包封體142及黏合劑128的一些親核添加劑與介電層112的頂表面上的懸空的羥基發生反應以在介電層112與包封體142之間形成共價鍵。具體而言，親核添加劑的氧原子使羥基斷裂，藉此在親核添加劑與介電層112的材料之間形成鍵。此種反應的實例在圖7C中示出。一些親核添加劑可不形成共價鍵，而是可保留於包封體142中。因此，介電層112與包封體142之間的介面的黏附性可被改善。在實施例中，黏附性可相較於缺乏共價鍵的介面增加多達22%，且介電層112與包封體142之間的介面可以能夠耐受達14.8克力(gf)的力。黏合劑128與介電層112之間的介面的黏附性可類似地被改善。改善介電層112與包封體142/黏合劑128之間的介面的黏附性可減少後續處理步驟中的介面分層的機會。在一些實施例中，共價鍵不會耗用介電層112的頂表面上的全部懸空的羥基，而是痕量的羥基會保留於介電層112上或介電層112中。
在圖8中，對包封體142執行平坦化製程以暴露出穿孔116及晶粒連接件138。平坦化製程亦可對介電材料140進行磨削。在平坦化製程之後，穿孔116的頂表面、晶粒連接件138的頂表面、介電材料140的頂表面及包封體142的頂表面是共面的。平坦化製程可為例如化學機械研磨(chemical-mechanical polish，CMP)、磨削製程等。在一些實施例中，舉例而言，若已暴露出穿孔116及晶粒連接件138，則可省略平坦化。
在圖9中，在穿孔116、包封體142及積體電路晶粒126之上形成前側重佈線結構144。前側重佈線結構144包括：介電層146、148、150及152；以及金屬化圖案154、156及158。金屬化圖案亦可被稱為重佈線層或重佈線走線。
所示出的前側重佈線結構144僅為實例。可在前側重佈線結構144中形成更多或更少的介電層及金屬化圖案。若欲形成更少的介電層及金屬化圖案，則可省略以上論述的步驟及製程。若欲形成更多的介電層及金屬化圖案，則可重複以上論述的步驟及製程。
作為形成前側重佈線結構144的實例，在包封體142、穿孔116及晶粒連接件138上沉積介電層146。在一些實施例中，介電層146是由可使用微影罩幕進行圖案化的感光性材料(例如，PBO、聚醯亞胺、BCB等)形成。可藉由旋轉塗佈、疊層、CVD、類似製程、或其組合來形成介電層146。接著將介電層146圖案化。所述圖案化會形成開口(未示出)，暴露出穿孔116的一些部 分及晶粒連接件138的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層146是感光性材料時將介電層146暴露至光或者藉由使用例如非等向性蝕刻的蝕刻來進行。若介電層146是感光性材料，則可在所述曝光後將介電層146顯影。
接著形成金屬化圖案154。金屬化圖案154包括導電線，所述導電線位於介電層146的主表面上且沿介電層146的主表面延伸。金屬化圖案154更包括導通孔，所述導通孔延伸穿過介電層146以實體地及電性地連接至穿孔116及積體電路晶粒126。為形成金屬化圖案154，在介電層146之上以及在延伸穿過介電層146的開口中形成晶種層(未示出)。在一些實施例中，晶種層是金屬層，可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等來形成晶種層。接著在晶種層上形成光阻(未示出)並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於金屬化圖案154。所述圖案化會形成穿過光阻的開口以暴露出晶種層。接著在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。導電材料可藉由鍍覆(例如，電鍍或無電鍍覆等)形成。所述導電材料可包括金屬，例如銅、鈦、鎢、鋁等。導電材料與下伏晶種層的一些部分的組合形成金屬化圖案154。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如 使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的被暴露出的部分。
在介電層146及金屬化圖案154上沉積介電層148。介電層148可採用與介電層146類似的方式來形成，且可由與介電層146相同的材料形成。
接著形成金屬化圖案156。金屬化圖案156包括導電線，所述導電線位於介電層148的主表面上且沿介電層148的主表面延伸。金屬化圖案156更包括導通孔，所述導通孔延伸穿過介電層148以實體地及電性地連接至金屬化圖案154。金屬化圖案156可採用與金屬化圖案154相似的方式來形成，且可由與金屬化圖案154相同的材料形成。
在介電層148及金屬化圖案156上沉積介電層150。介電層150可採用與介電層146類似的方式來形成，且可由與介電層146相同的材料形成。
接著形成金屬化圖案158。金屬化圖案158包括導電線，所述導電線位於介電層150的主表面上且沿介電層150的主表面延伸。金屬化圖案158更包括導通孔，所述導通孔延伸穿過介電層150以實體地及電性地連接至金屬化圖案156。金屬化圖案158可採用與金屬化圖案154相似的方式來形成，且可由與金屬化圖案154相同的材料形成。
在介電層150及金屬化圖案158上沉積介電層152。介電層152可採用與介電層146類似的方式來形成，且可由與介電層 146相同的材料形成。
在圖10中，在介電層152上形成凸塊下金屬(under bump metallurgy，UBM)160且UBM 160延伸穿過介電層152。作為形成UBM 160的實例，可將介電層152圖案化以形成開口(未示出)，暴露出金屬化圖案158的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層152是感光性材料時將介電層152暴露至光或者藉由使用例如非等向性蝕刻的蝕刻來進行。若介電層152是感光性材料，則可在所述曝光後將介電層152顯影。UBM 160的開口可較金屬化圖案154、156及158的導通孔部分的開口寬。在介電層152之上以及在開口中形成晶種層(未示出)。在一些實施例中，晶種層是金屬層，可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如PVD等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於UBM 160。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。導電材料可藉由鍍覆(例如，電鍍或無電鍍覆等)形成。所述導電材料可包括金屬，例如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻 或乾式蝕刻)來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成UBM 160。在其中UBM 160以不同方式形成的實施例中，可利用更多的光阻及圖案化步驟。
在圖11A中，在UBM 160上形成導電連接件162。導電連接件162可為球柵陣列(ball grid array，BGA)連接件、焊料球、金屬柱、受控塌陷晶粒連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊等。導電連接件162可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料、或其組合。在一些實施例中，導電連接件162藉由以下方式來形成：在開始時藉由例如蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等常用方法形成焊料層。一旦已在所述結構上形成焊料層，則可執行回焊(reflow)以將材料塑形成所期望的凸塊形狀。在另一個實施例中，導電連接件162包括藉由濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱(例如銅柱)。金屬柱可為無焊料的(solder free)且具有實質上垂直的側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層(未示出)。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料、或其組合，且可藉由鍍覆製程來形成。
圖11B是圖11A所示的區16的詳細視圖，其示出在形成導電連接件162之後的積體電路晶粒126及前側重佈線結構144。 在俯視圖中，導電連接件162的子集沿積體電路晶粒126的邊緣或隅角放置。積體電路晶粒126的邊緣是由積體電路晶粒126與包封體142的介面界定。積體電路晶粒126的邊緣及隅角通常經受更高的機械應變。舉例而言，沿積體電路晶粒126的邊緣及隅角的導電連接件162可經受比積體電路晶粒126的中心中的導電連接件162多達10%的應變。UBM 160類似地經受增加的應變。藉由在先前步驟中(例如，利用表面處理製程122及124)改善介電層112與包封體142/黏合劑128之間的介面的黏附性，包封體142及積體電路晶粒126較少可能地對前側重佈線結構144施加力。因此，當處於增加的應變下時，UBM 160與前側重佈線結構144分層的機率可減小。由此可避免更昂貴的分層解決方案，例如對積體電路晶粒126或導電連接件162的位置進行重新排列。此可使得積體電路晶粒126能夠更均勻地分佈於所得第一封裝200中，進而使得包封體142能夠更均勻地分佈在積體電路晶粒126周圍。
可形成沿積體電路晶粒126的邊緣及隅角的導電連接件162，導電連接件162與積體電路晶粒126的邊緣及隅角交疊。在實施例中，導電連接件162設置在接近積體電路晶粒126的邊緣或隅角的邊緣區域中。邊緣區域的邊界被設置成距積體電路晶粒126的邊緣或隅角有距離D2。在實施例中，距離D2可為約25微米。整個邊緣區域可被導電連接件162佔用。導電連接件162的第一側被設置在邊緣區域之外的距離D3處，且導電連接件162的 第二側被設置在邊緣區域之外的距離D4處。在實施例中，距離D3及D4可分別為相應的導電連接件162的總寬度的至少四分之一。換言之，當導電連接件162具有寬度時，每一相應的導電連接件162的至少四分之一的寬度設置於積體電路晶粒126之上，且每一相應的導電連接件162的至少四分之一的寬度設置於包封體142之上。沿積體電路晶粒126的邊緣及隅角形成導電連接件162可使導電連接件162的數量能夠增加，由此增加所得第一封裝200的輸入/輸出(I/O)計數。
在圖12中，執行載體基底剝離(carrier substrate de-bonding)以將載體基底102自背側重佈線結構106(例如，介電層108)分離(「剝離」)。在剝離之後留下的特徵(例如，在第一封裝區100A及第二封裝區100B中)形成第一封裝200。根據一些實施例，所述剝離包括在釋放層104上投射例如雷射光或紫外光等光，以使得釋放層104在光的熱作用下分解，且可移除載體基底102。接著將所述結構翻轉並放置於膠帶164上。此外，穿過介電層108形成開口166以暴露出金屬化圖案110的一些部分。可例如使用雷射鑽孔(laser drilling)、蝕刻等來形成開口166。
圖13A至圖14示出根據一些實施例的形成封裝結構500(參見圖14)的製程期間的中間步驟的剖視圖。封裝結構500可被稱為疊層封裝(PoP)結構。
在圖13A中，將第二封裝300貼合至第一封裝200中的每一者。第二封裝300包括基底302及耦合至基底302的一或多 個經堆疊晶粒308A、308B。儘管圖中示出晶粒308A、308B的單個堆疊，然而在其他實施例中，可並排地設置多個經堆疊晶粒308A、308B(每一個經堆疊晶粒308A、308B具有一或多個經堆疊的晶粒)，所述多個經堆疊晶粒308A、308B耦合至基底302的同一表面。基底302可由例如矽、鍺、金剛石等半導體材料製成。在一些實施例中，亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、砷磷化鎵、磷化鎵銦、其組合等化合物材料。另外，基底302可為絕緣體上矽(silicon-on-insulator，SOI)基底。一般而言，SOI基底包括例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺(silicon germanium on insulator，SGOI)或其組合等半導體材料的層。在一個替代實施例中，基底302是基於例如被纖維玻璃強化的樹脂芯體等絕緣芯體。一種示例性芯體材料是纖維玻璃樹脂(例如，FR4)。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪(bismaleimide-triazine，BT)樹脂，或者作為另外一種選擇，為其他印刷電路板(PCB)材料或膜。可對基底302使用例如味之素構成膜(Ajinomoto Build up Film，ABF)等構成膜或其他疊層。
基底302可包括主動裝置及被動裝置(未示出)。可使用例如電晶體、電容器、電阻器、該些的組合等各種各樣的裝置來產生第二封裝300的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
基底302亦可包括金屬化層(未示出)及導通孔306。金屬化層可在主動裝置及被動裝置之上形成並被設計成連接各種裝 置以形成功能性電路系統。金屬化層可由交錯的介電材料(例如，低介電常數介電材料)層及導電材料(例如，銅)層形成且可藉由任何適合的製程(例如沉積、鑲嵌、雙鑲嵌等)來形成，其中由通孔對各層導電材料進行內連。在一些實施例中，基底302實質上無主動裝置及被動裝置。
基底302可具有位於基底302的第一側上的接合墊303以耦合至經堆疊晶粒308A、308B，並具有位於基底302的第二側上的接合墊304以耦合至導電連接件314，基底302的第二側與基底302的第一側相對。在一些實施例中，藉由在基底302的第一側及第二側上的介電層(未示出)中形成凹陷(未示出)來形成接合墊303及304。所述凹陷可被形成為使得接合墊303及304能夠嵌置於介電層中。在其他實施例中，由於可在介電層上形成接合墊303及304，因此省略所述凹陷。在一些實施例中，接合墊303及304包括由銅、鈦、鎳、金、鈀等、或其組合製成的薄晶種層(未示出)。可在所述薄晶種層之上沉積接合墊303及304的導電材料。可藉由電化學鍍覆製程(electro-chemical plating process)、無電鍍覆製程、化學氣相沉積、原子層沉積(atomic layer deposition，ALD)、物理氣相沉積等或其組合來形成所述導電材料。在實施例中，接合墊303及304的導電材料為銅、鎢、鋁、銀、金等、或其組合。
在實施例中，接合墊303及304為包含三個導電材料層(例如鈦層、銅層、及鎳層)的凸塊下金屬。可利用其他材料及 層的排列(例如鉻/鉻-銅合金/銅/金的排列、鈦/鈦鎢/銅的排列、或銅/鎳/金的排列)來形成接合墊303及304。可用於接合墊303及304的任何適合的材料或材料層全部旨在包含於本申請案的範圍內。在一些實施例中，導通孔306延伸貫穿基底302且將至少一個接合墊303耦合至至少一個接合墊304。
在所示實施例中，經堆疊晶粒308A、308B是藉由導線接合件310耦合至基底302，然而可使用其他連接(例如導電凸塊)。在實施例中，經堆疊晶粒308A、308B為經堆疊記憶體晶粒。舉例而言，經堆疊晶粒308A、308B可為例如低功率(low-power，LP)雙倍資料速率(double data rate，DDR)記憶體模組(例如LPDDR1、LPDDR2、LPDDR3、LPDD4、或類似的記憶體模組)等記憶體晶粒。
可藉由模塑材料312來包封經堆疊晶粒308A、308B及導線接合件310。可例如使用壓縮模塑將模塑材料312模塑於經堆疊晶粒308A、308B及導線接合件310上。在一些實施例中，模塑材料312為模塑化合物、聚合物、環氧樹脂、氧化矽填充材料等、或其組合。可執行固化製程以固化模塑材料312；所述固化製程可為熱固化、紫外固化等或其組合。
在一些實施例中，將經堆疊晶粒308A、308B及導線接合件310掩埋於模塑材料312中，且在模塑材料312固化之後，執行平坦化步驟(例如磨削)以移除模塑材料312的多餘部分並為第二封裝300提供實質上平坦的表面。
在形成第二封裝300之後，經由導電連接件314、接合墊304及金屬化圖案110而將第二封裝300機械地且電性地接合至第一封裝200。在一些實施例中，可經由導線接合件310、接合墊303及304、導通孔306、導電連接件314及穿孔116而將經堆疊晶粒308A、308B耦合至積體電路晶粒126。
在一些實施例中，在基底302的與經堆疊晶粒308A、308B相對的側上形成阻焊劑(未示出)。導電連接件314可在阻焊劑中的開口中被設置成電性地且機械地耦合至基底302中的導電特徵(例如，接合墊304)。阻焊劑可用於保護基底302的一些區域不受外部損壞。
在一些實施例中，在導電連接件314被回焊之前在導電連接件314上形成有環氧樹脂焊劑(未示出)，其中所述環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分在第二封裝300貼合至第一封裝200之後剩餘。
在一些實施例中，在第一封裝200與第二封裝300之間形成環繞導電連接件314的底部填充物316。底部填充物316可減小應力並保護由對導電連接件314進行回焊而形成的接頭(joint)。底部填充物316可在貼合第一封裝200之後藉由毛細流動製程(capillary flow process)來形成或者可在貼合第一封裝200之前藉由適合的沉積方法來形成。在其中形成環氧樹脂焊劑的實施例中，環氧樹脂焊劑可充當底部填充物316。
圖13B是在將第二封裝300貼合至第一封裝200之後的 導電連接件314的區18的詳細視圖。在俯視圖中，導電連接件314的子集沿積體電路晶粒126的邊緣或隅角放置。類似於導電連接件162，沿積體電路晶粒126的邊緣及隅角放置的導電連接件314可經受增加的應變。舉例而言，沿積體電路晶粒126的邊緣及隅角的導電連接件314可經受比積體電路晶粒126的中心中的導電連接件314多超過200%的應變。藉由在先前步驟中(例如，利用表面處理製程122及124)改善介電層112與包封體142/黏合劑128之間的介面的黏附性，當處於增加的應變下時，介電層112與積體電路晶粒126分層的機率可減小。因此可避免更昂貴的分層解決方案，例如對積體電路晶粒126或導電連接件314的位置進行重新排列。此可使積體電路晶粒126能夠更均勻地分佈在所得第一封裝200中，進而使包封體142能夠更均勻地分佈在積體電路晶粒126周圍。
可形成沿積體電路晶粒126的邊緣及隅角的導電連接件314，導電連接件314與積體電路晶粒126的邊緣及隅角交疊。在實施例中，在接近積體電路晶粒126的邊緣或隅角的邊緣區域中設置導電連接件314。邊緣區域的邊界設置成距積體電路晶粒126的邊緣或隅角有距離D5。距離D5可等於距離D2。在實施例中，距離D5可為約25微米。整個邊緣區域可被導電連接件314佔用。導電連接件314的第一側被設置在邊緣區域之外的距離D6處，且導電連接件314的第二側被設置在邊緣區域之外的距離D7處。在實施例中，距離D6及D7可分別為相應的導電連接件314的總寬 度的至少四分之一。換言之，當導電連接件314具有寬度時，每一相應的導電連接件314的至少四分之一的寬度設置於積體電路晶粒126之上，且每一相應的導電連接件314的至少四分之一的寬度設置於包封體142之上。
圖13C是示出圖13A所示裝置的一些特徵的俯視圖。為說明清晰起見省略圖13C中的一些特徵或一些層。圖中示出積體電路晶粒126的隅角，且所述隅角被包封體142包封。圖中示出導電連接件314所耦合的金屬化圖案110的一些部分。導電連接件314耦合至金屬化圖案110中的墊110A及110B。一些墊110B設置於接近積體電路晶粒126的邊緣或隅角的邊緣區域中(例如，設置成距積體電路晶粒126的邊緣小於距離D5處)。在一些實施例中，墊110A的第一形狀設置在積體電路晶粒126之上，且墊110B的第二形狀設置在包封體142之上。在其他實施例中，所述墊均具有相同的形狀。
在圖14中，藉由沿切割道區(例如，在第一封裝區100A與第二封裝區100B之間)進行鋸切來執行單體化製程。所述鋸切使第一封裝區100A自第二封裝區100B單體化。所得的經單體化的第一封裝200及第二封裝300來自第一封裝區100A或第二封裝區100B中的一者。在一些實施例中，單體化製程是在將第二封裝300貼合至第一封裝200之後執行的。在其他實施例(未示出)中，單體化製程是在將第二封裝300貼合至第一封裝200之前執行的，例如在剝離載體基底102且形成開口166之後執行。
接著使用導電連接件162將第一封裝200安裝至封裝基底400。封裝基底400可由例如矽、鍺、金剛石等半導體材料製成。作為另外一種選擇，亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、砷磷化鎵、磷化鎵銦、其組合等化合物材料。另外，封裝基底400可為SOI基底。一般而言，SOI基底包括例如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合等半導體材料的層。在一個替代實施例中，封裝基底400是基於例如被玻璃纖維強化的樹脂芯體等絕緣芯體。一種示例性芯體材料為玻璃纖維樹脂(例如FR4)。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪BT樹脂，或者作為另外一種選擇，為其他PCB材料或膜。可對封裝基底400使用例如ABF等構成膜或其他疊層。
封裝基底400可包括主動裝置及被動裝置(未示出)。如此項技術中具有通常知識者將認識到，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生封裝結構500的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
封裝基底400亦可包括金屬化層及通孔(未示出)以及位於所述金屬化層及通孔之上的接合墊402。金屬化層可在主動裝置及被動裝置之上形成並被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交錯的介電材料(例如低介電常數介電材料)層與導電材料(例如銅)層形成且可藉由任何適合的製程(例如沉積、鑲嵌、雙鑲嵌等)來形成，其中由通孔對各層導電材料 進行內連。在一些實施例中，封裝基底400實質上無主動裝置及被動裝置。
在一些實施例中，將導電連接件162回焊以將第一封裝200貼合至接合墊402。導電連接件162將封裝基底400(包括封裝基底400中的金屬化層)電性地及/或實體地耦合至第一封裝200。在一些實施例中，可將被動裝置(例如，表面安裝裝置(surface mount device，SMD)，未示出)在安裝於封裝基底400之前貼合至第一封裝200(例如，接合至接合墊402)。在該些實施例中，可將被動裝置接合至第一封裝200的與導電連接件162相同的表面。
在對導電連接件162進行回焊之前導電連接件162上可形成有環氧樹脂焊劑(未示出)，其中環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分在第一封裝200貼合至封裝基底400之後剩餘。此剩餘的環氧樹脂部分可充當底部填充物以減小應力並保護由對導電連接件162進行回焊而形成的接頭。在一些實施例中，可在第一封裝200與封裝基底400之間形成環繞導電連接件162的底部填充物(未示出)。可在貼合第一封裝200之後藉由毛細流動製程來形成底部填充物或者可在貼合第一封裝200之前藉由適合的沉積方法來形成所述底部填充物。
各個實施例可達成各種優點。自介電層112移除殘餘金屬120可改善介電層112與包封體142/黏合劑128之間的介面的黏附性。此可使導電連接件314能夠在不分層的情況下以更加靠 近積體電路晶粒126的邊緣及隅角的方式形成。此外，藉由改善介面的黏附性，包封體142及積體電路晶粒126會較少可能地對前側重佈線結構144施加力。此亦可使導電連接件162能夠在不分層的情況下以更加靠近積體電路晶粒126的邊緣及隅角的方式形成。因此可增加所得裝置的輸入/輸出(I/O)計數。
在實施例中，一種裝置包括：第一重佈線結構，包括第一介電層；晶粒，黏附至所述第一重佈線結構的第一側；包封體，橫向地包封所述晶粒，所述包封體用第一共價鍵接合至所述第一介電層；穿孔，延伸穿過所述包封體；以及第一導電連接件，電性連接至所述第一重佈線結構的第二側，所述第一導電連接件的子集和所述包封體與所述晶粒的介面交疊。
在所述裝置的一些實施例中，所述包封體包含模塑化合物及親核劑。在所述裝置的一些實施例中，所述親核劑是乙二醇、2-乙氧基乙醇或乙醇胺鹽酸鹽。在一些實施例中，所述裝置更包括：黏合劑，將所述晶粒黏附至所述第一介電層，所述黏合劑用第二共價鍵接合至所述第一介電層。在所述裝置的一些實施例中，所述黏合劑包括環氧樹脂及所述親核劑。在所述裝置的一些實施例中，所述第一導電連接件的所述子集的每一相應的導電連接件具有寬度，其中每一相應的導電連接件的至少四分之一的所述寬度設置於所述晶粒之上，其中每一相應的導電連接件的至少四分之一的所述寬度設置於所述包封體之上。在一些實施例中，所述裝置更包括：第二重佈線結構，電性連接至所述穿孔及所述 晶粒，所述包封體設置於所述第一重佈線結構與第二重佈線結構之間；以及第二導電連接件，電性連接至所述第二重佈線結構，所述第二導電連接件的子集和所述包封體與所述晶粒的所述介面交疊。在一些實施例中，所述裝置更包括：裝置封裝，用所述第一導電連接件連接至所述第一重佈線結構；以及封裝基底，用所述第二導電連接件連接至所述第二重佈線結構。
在實施例中，一種方法包括：在第一金屬化圖案之上形成第一介電層；形成延伸穿過所述第一介電層的穿孔，所述穿孔電性連接至所述第一金屬化圖案；將晶粒黏附至所述第一介電層的第一表面；用第一共價鍵將包封體接合至所述第一介電層的所述第一表面，所述包封體橫向地包封所述晶粒及所述穿孔；在所述包封體之上形成第二介電層；以及形成延伸穿過所述第二介電層的第二金屬化圖案，所述第二金屬化圖案電性連接至所述晶粒及所述穿孔。
在一些實施例中，所述方法更包括：形成電性連接至所述第一金屬化圖案的第一導電連接件，所述第一導電連接件的子集與所述晶粒的邊緣或隅角交疊；以及用所述第一導電連接件將裝置封裝連接至所述第一金屬化圖案。在一些實施例中，所述方法更包括：形成電性連接至所述第二金屬化圖案的第二導電連接件，所述第二導電連接件的子集與所述晶粒的所述邊緣或所述隅角交疊；以及用所述第二導電連接件將封裝基底連接至所述第二金屬化圖案。在一些實施例中，所述方法更包括：對所述第一介 電層的所述第一表面進行處理以在所述第一介電層的所述第一表面上形成懸空的羥基。在所述方法的一些實施例中，將所述包封體接合至所述第一介電層的所述第一表面包括：將所述包封體分配於所述第一介電層的所述第一表面上，所述包封體包括模塑化合物及親核劑；以及將所述包封體固化以在所述懸空的羥基與所述親核劑之間形成所述第一共價鍵。在所述方法的一些實施例中，將所述晶粒黏附至所述第一介電層的所述第一表面包括：將黏合劑分配於所述晶粒上，所述黏合劑包括環氧樹脂及親核劑；以及將所述黏合劑固化以使所述懸空的羥基與所述親核劑反應並形成第二共價鍵。在所述方法的一些實施例中，對所述第一介電層的所述第一表面進行處理包括：執行第一表面處理製程以對所述第一介電層的所述第一表面同時進行蝕刻及羥基化；以及執行第二表面處理製程以移除藉由對所述第一介電層的所述第一表面進行蝕刻而暴露出的殘餘金屬。在所述方法的一些實施例中，所述第一表面處理製程是電漿處理製程且所述第二表面處理製程是濕式蝕刻製程，其中所述電漿處理製程的前驅物包括O2及H2。
在實施例中，一種方法包括：用晶種層對穿過第一介電層的穿孔進行鍍覆；對所述晶種層的被暴露出的部分進行蝕刻，在對所述晶種層進行蝕刻之後，保留下來所述晶種層的殘餘金屬；對所述第一介電層的第一表面進行處理以對所述第一表面進行羥基化並自所述第一表面移除所述晶種層的所述殘餘金屬；將晶粒黏附至經羥基化的所述第一表面；以及用第一共價鍵將包封 體接合至經羥基化的所述第一表面，所述包封體橫向地包封所述晶粒及所述穿孔；以及在所述包封體及所述晶粒之上形成第二介電層。
在所述方法的一些實施例中，將所述晶粒黏附至經羥基化的所述第一表面包括：用第二共價鍵將黏合劑接合至經羥基化的所述第一表面，所述黏合劑將所述晶粒黏附至經羥基化的所述第一表面。在所述方法的一些實施例中，對所述第一介電層的所述第一表面進行處理包括：執行第一表面處理製程以對所述第一介電層的所述第一表面進行羥基化；以及執行第二表面處理製程以自經羥基化的所述第一表面移除所述晶種層的所述殘餘金屬。在所述方法的一些實施例中，將所述包封體接合至經羥基化的所述第一表面包括：將包封體分配於經羥基化的所述第一表面上，所述包封體包括模塑化合物及親核劑；以及將所述包封體固化以在經羥基化的所述第一表面與所述親核劑之間形成所述第一共價鍵。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應知，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
14:區
102:載體基底
104:釋放層
108、112:介電層
110:金屬化圖案
116:穿孔
126:積體電路晶粒
128:黏合劑
142:包封體

Claims (10)

  1. 一種半導體裝置，包括：第一重佈線結構，包括第一介電層，所述第一介電層具有經羥基化的表面；晶粒，黏附至所述第一介電層的所述經羥基化的表面；包封體，橫向地包封所述晶粒，所述包封體用第一共價鍵接合至所述第一介電層的所述經羥基化的表面；穿孔，延伸穿過所述包封體；以及第一導電連接件，電性連接至所述第一重佈線結構的第二側，所述第一導電連接件的子集與所述包封體與所述晶粒的介面交疊。
  2. 如申請專利範圍第1項所述的裝置，其中所述包封體包含模塑化合物及親核劑。
  3. 如申請專利範圍第2項所述的裝置，更包括：黏合劑，將所述晶粒黏附至所述第一介電層，所述黏合劑用第二共價鍵接合至所述第一介電層。
  4. 如申請專利範圍第1項所述的裝置，其中所述第一導電連接件的所述子集中的每一相應的導電連接件具有寬度，其中所述每一相應的導電連接件的至少四分之一的所述寬度設置於所述晶粒之上，其中所述每一相應的導電連接件的至少四分之一的所述寬度設置於所述包封體之上。
  5. 如申請專利範圍第1項所述的裝置，更包括： 第二重佈線結構，電性連接至所述穿孔及所述晶粒，所述包封體設置於所述第一重佈線結構與所述第二重佈線結構之間；以及第二導電連接件，電性連接至所述第二重佈線結構，所述第二導電連接件的子集與所述包封體與所述晶粒的所述介面交疊。
  6. 一種半導體裝置的形成方法，包括：在第一金屬化圖案之上形成第一介電層；形成延伸穿過所述第一介電層的穿孔，所述穿孔電性連接至所述第一金屬化圖案；將晶粒黏附至所述第一介電層的第一表面；用第一共價鍵將包封體接合至所述第一介電層的所述第一表面，所述包封體橫向地包封所述晶粒及所述穿孔；在所述包封體之上形成第二介電層；以及形成延伸穿過所述第二介電層的第二金屬化圖案，所述第二金屬化圖案電性連接至所述晶粒及所述穿孔。
  7. 如申請專利範圍第6項所述的方法，更包括：形成電性連接至所述第一金屬化圖案的第一導電連接件，所述第一導電連接件的子集與所述晶粒的邊緣或隅角交疊；以及用所述第一導電連接件將裝置封裝連接至所述第一金屬化圖案。
  8. 一種半導體裝置的形成方法，包括：用晶種層對穿過第一介電層的穿孔進行鍍覆； 對所述晶種層的被暴露出的部分進行蝕刻，在對所述晶種層進行蝕刻之後保留所述晶種層的殘餘金屬；對所述第一介電層的第一表面進行處理以對所述第一表面進行羥基化並自所述第一表面移除所述晶種層的所述殘餘金屬；將晶粒黏附至經羥基化的所述第一表面；用第一共價鍵將包封體接合至經羥基化的所述第一表面，所述包封體橫向地包封所述晶粒及所述穿孔；以及在所述包封體及所述晶粒之上形成第二介電層。
  9. 如申請專利範圍第8項所述的方法，其中將所述晶粒黏附至經羥基化的所述第一表面包括：用第二共價鍵將黏合劑接合至經羥基化的所述第一表面，所述黏合劑將所述晶粒黏附至經羥基化的所述第一表面。
  10. 如申請專利範圍第8項所述的方法，其中對所述第一介電層的所述第一表面進行處理包括：執行第一表面處理製程以對所述第一介電層的所述第一表面進行羥基化；執行第二表面處理製程以自經羥基化的所述第一表面移除所述晶種層的所述殘餘金屬。
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