CN110660753A - 半导体封装件和方法 - Google Patents

半导体封装件和方法 Download PDF

Info

Publication number
CN110660753A
CN110660753A CN201910454554.1A CN201910454554A CN110660753A CN 110660753 A CN110660753 A CN 110660753A CN 201910454554 A CN201910454554 A CN 201910454554A CN 110660753 A CN110660753 A CN 110660753A
Authority
CN
China
Prior art keywords
dielectric layer
die
encapsulant
redistribution structure
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910454554.1A
Other languages
English (en)
Other versions
CN110660753B (zh
Inventor
潘国龙
郑淑蓉
罗登元
郭鸿毅
张志鸿
郭庭豪
蔡豪益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110660753A publication Critical patent/CN110660753A/zh
Application granted granted Critical
Publication of CN110660753B publication Critical patent/CN110660753B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/8301—Cleaning the layer connector, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

在实施例中，一种器件包括：第一再分布结构，包括第一介电层；管芯，粘附至第一再分布结构的第一侧；密封剂，横向密封管芯，密封剂通过第一共价键与第一介电层接合；穿过密封剂的通孔；第一导电连接器，电连接至第一再分布结构的第二侧，第一导电连接器的子集与密封剂和管芯的界面重叠。本发明实施例涉及半导体封装件和方法。

Description

半导体封装件和方法
技术领域
本发明实施例涉及半导体封装件和方法。
背景技术
由于各种电子组件(例如，晶体管，二极管，电阻器，电容器等)的集成密度的不断提高，半导体工业经历了快速增长。在大多数情况下，集成密度的提高是由于最小部件尺寸的迭代减少所致，这允许将更多组件集成到给定区域中。随着对缩小电子器件的需求的增长，出现了对更小和更有创意的半导体管芯的封装技术的需求。这种封装系统的一个实例是叠层封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上，以提供高水平的集成度和元件密度。PoP技术通常能够在印刷电路板(PCB)上生产具有增强功能和小占用面积的半导体器件。
发明内容
根据本发明的一些是实施例，提供了一种半导体器件，包括：第一再分布结构，包括第一介电层；管芯，粘附至所述第一再分布结构的第一侧；密封剂，横向密封所述管芯，所述密封剂通过第一共价键接合至所述第一介电层；通孔，延伸穿过所述密封剂；和第一导电连接器，电连接至所述第一再分布结构的第二侧，所述第一导电连接器的子集与所述密封剂和所述管芯的界面重叠。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在第一金属化图案上方形成第一介电层；形成延伸穿过所述第一介电层的通孔，所述通孔电连接至所述第一金属化图案；将管芯粘附至所述第一介电层的第一表面；利用第一共价键将密封剂接合至所述第一介电层的第一表面，所述密封剂横向密封所述管芯和所述通孔；在所述密封剂上方形成第二介电层；和形成延伸通过所述第二介电层的第二金属化图案，所述第二金属化图案电连接至所述管芯和所述通孔。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：穿过第一介电层利用晶种层镀通孔；蚀刻所述晶种层的暴露部分，蚀刻所述晶种层后保留晶种层的残余金属；处理所述第一介电层的第一表面以使所述第一表面羟基化并且从所述第一表面去除所述晶种层的残余金属；将管芯粘附至羟基化的第一表面；和利用第一共价键将密封剂接合至所述羟基化的第一表面，所述密封剂横向密封所述管芯和所述通孔；和在所述密封剂和所述管芯上方形成第二介电层。
附图说明
当接合附图阅读时，从以下详细描述中可以最好地理解本公开的各方面。应注意，根据工业中的标准实践，各种部件未按比例绘制。实际上，为了清楚讨论，可以任意增加或减少各种部件的尺寸。
图1至图12示出了根据一些实施例的用于形成器件封装件的工艺期间的中间步骤的截面图。
图13A至图14示出了根据一些实施例的用于形成封装结构的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例，在背侧再分布结构上形成封装件之前，利用若干表面处理工艺清洁背侧再分布结构的最顶部介电层。表面处理工艺可以减少嵌入最顶部介电层中的残余金属的量。残余金属可以是来自例如形成在最顶部介电层上的晶种层的金属剩余物。表面处理工艺还可以使最顶部介电层羟基化。随后形成的模塑料包括亲核试剂，其与羟基化表面形成共价键。通过去除残余金属并与模塑料形成共价键，可以增加模塑料和最顶部介电层之间界面的强度，这可以帮助避免随后形成的部件的分层。因此，可以在经受较高机械应变的封装件的区域中形成部件。
图1至图12根据一些实施例示出了用于形成第一封装件200(见图12)的工艺期间的中间步骤的截面图。示出了第一封装件区域100A和第二封装件区域100B，并且在每个封装件区域中形成第一封装件200。第一封装件200也被称为集成扇出(InFO)封装件。
在图1中，提供载体衬底102，并且在载体衬底102上形成释放层104。载体衬底102可以是玻璃载体衬底，陶瓷载体衬底等。载体衬底102可以是晶圆，使得可以同时在载体衬底102上形成多个封装件。释放层104可以由基于聚合物的材料形成，其可以与载体衬底102从将在后续步骤中形成的上面的结构一起去除。在一些实施例中，释放层104是基于环氧树脂的热释放材料，其在加热时失去其粘合性，诸如光-热-转换(LTHC)释放涂层。在其他实施例中，释放层104可以是紫外(UV)胶，当暴露于UV光时其失去其粘合性。释放层104可以作为液体分配并固化，可以是层压到载体衬底102上的层压膜，或者可以是类似物。释放层104的顶面可以是水平的并且可以具有高度的共面性。
在图2中，在释放层104上形成背侧再分布结构106。在所示实施例中，背侧再分布结构106包括介电层108，金属化图案110(有时称为再分布层或再分布线)和介电层112。
在释放层104上形成介电层108。介电层108的底面可以与释放层104的顶面接触。在一些实施例中，介电层108由聚合物形成，诸如聚苯并恶唑(PBO)，聚酰亚胺，苯并环丁烯(BCB)等。在其他实施例中，介电层108由诸如氮化硅的氮化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等的氧化物等形成。介电层108可以通过任何可接受的沉积工艺形成，诸如旋涂，化学气相沉积(CVD)，层压等，或其组合。
在介电层108上形成金属化图案110。作为形成金属化图案110的示例，在介电层108上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用例如物理气相沉积(PVD)等形成晶种层。然后在晶种层上形成并图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶暴露于光以用于图案化。光刻胶的图案对应于金属化图案110。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可包括金属，如铜，钛，钨，铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成金属化图案110。
在金属化图案110和介电层108上形成介电层112。在一些实施例中，介电层112由聚合物形成，该聚合物可以是诸如PBO，聚酰亚胺，BCB等的光敏材料，并且可以使用光刻掩模图案化。在其他实施例中，介电层112由诸如氮化硅的氮化物，诸如氧化硅、PSG、BSG、BPSG等的氧化物等形成。介电层112可以通过旋涂，层压，CVD等或其组合形成。然后图案化介电层112以形成暴露金属化图案110的部分的开口114。图案化可以通过可接受的工艺，诸如当介电层112是光敏材料时通过将介电层112暴露于光或者通过使用例如各向异性蚀刻进行蚀刻。在一些实施例中，介电层112是具有高热膨胀系数(CTE)的材料，诸如聚酰亚胺。在一些实施例中，介电层112的CTE在约45ppm/℃至约55ppm/℃的范围内。
应了解，背侧再分布结构106可包括任何数量的介电层和金属化图案。可以通过重复用于形成金属化图案110和介电层112的工艺来形成额外的介电层和金属化图案。金属化图案可以包括导电线和导电通孔。可以在形成金属化图案期间，通过在下面的介电层的开口中形成金属化图案的导电材料和晶种层来形成导电通孔。因此，导电通孔可以互连并电连接各条导电线。
在图3A中，通孔116形成在开口114中并且远离背侧再分布结构106的最顶部介电层(例如，在所示实施例中的介电层112)延伸。图3B是区域10的详细视图，并结合图3A进行描述。作为形成通孔116的示例，晶种层116A形成在背侧再分布结构106上方，例如，在介电层112上以及由开口114暴露的金属化图案110的部分上。在一些实施例中，晶种层116A是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层116A包括钛层和钛层上方的铜层。晶种层116A可以使用例如PVD等形成。在晶种层116A上形成并图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶暴露于光以用于图案化。光刻胶的图案对应于导电通孔。图案化形成穿过光刻胶的开口以暴露晶种层116A。导电材料116B形成在光刻胶的开口中和晶种层116A的暴露部分上。导电材料116B可以通过镀形成，诸如电镀或化学镀等。导电材料116B可包括金属，如铜，钛，钨，铝等。去除光刻胶和晶种层116A的其上未形成导电材料116B的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除了光刻胶，就去除晶种层116A的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻。晶种层116A的剩余部分和导电材料116B形成通孔116。
图3C是在去除晶种层116A(参见图3B)的暴露部分之后的背侧再分布结构106的区域12的详细视图。在晶种层116A包括钛层和钛层上方的铜层的实施例中，晶种层116A通过诸如溅射的PVD工艺形成。PVD工艺可以包括预蚀刻步骤，其增加介电层112的顶面的粗糙度并在介电层112的顶面中形成凹坑118。当钛层溅射在介电层112上时，一些残余金属120(例如，钛)可以被注入到介电层112中。具体地，残余金属120可以被捕获在形成在介电层112的粗糙顶面中的凹坑118中。
在图4A中，利用第一表面处理工艺122清洁背侧再分布结构106的最顶部介电层(例如，所示实施例中的介电层112)。在一些实施例中，第一表面处理工艺122包括在介电层112的顶面上的蚀刻工艺以暴露掩埋的残余金属120，并且还包括在介电层112的顶面上的羟基化工艺。例如，在一些实施例中，第一表面处理工艺122是等离子体处理工艺。等离子体处理工艺可以用在处理过的表面上留下羟基的前体实施，诸如Ar、O2、N2、CF4或其组合。在这样的实施例中，等离子体处理工艺可以在约25℃至约100℃(诸如约70℃)的温度下进行，并且可以进行约30秒至约180秒的时间(诸如小于约180秒)。在一些实施例中，前体可包含少量H2，例如浓度为约0.1％至约10％。包括H2可以帮助产生去除介电层112的材料的等离子体。在一个实施例中，等离子体处理工艺的前体包括O2和H2。因此，等离子体处理工艺可以被认为是干蚀刻和表面羟基化的组合。在第一表面处理工艺122之后，等离子体处理前体的一些残余物可以保留在介电层112的顶面上。
图4B是在第一表面处理工艺122之后的背侧再分布结构106的区域12的详细视图。在第一表面处理工艺122之后，将介电层112减薄距离D1，使得与在第一表面处理工艺122之前相比，捕获在介电层112的凹坑118中的残余金属120更多地暴露。此外，在第一表面处理工艺122之后，在介电层112的顶面上形成悬垂的羟基基团。
在图5A中，用第二表面处理工艺124清洁背侧再分布结构106的最顶部介电层(例如，所示实施例中的介电层112)。在一些实施例中，第二表面处理工艺去除暴露的残余金属120。在一些实施例中，第二表面处理工艺124包括蚀刻工艺，诸如湿蚀刻。在一个实施例中，湿蚀刻工艺的蚀刻剂包括氢氟酸。湿蚀刻工艺可以对残余金属120的材料具有选择性，使得介电层112的厚度基本上不减小。在一些实施例中，第二表面处理工艺124是去除残余金属120的等离子体蚀刻工艺。在第二表面处理工艺124之后，等离子体处理前体的一些残余物可保留在介电层112的顶面上。
图5B是在第二表面处理工艺124之后的背侧再分布结构106的区域12的详细视图。在第二表面处理工艺124之后，消除或至少减少了被捕获在介电层112的凹坑118中的残余金属120的数量。
在图6中，集成电路管芯126通过粘合剂128粘附至介电层112。集成电路管芯126可以是逻辑管芯(例如，中央处理单元，微控制器等)，存储器管芯(例如，动态随机存取存储器(DRAM)管芯，静态随机存取存储器(SRAM)管芯等)，电源管理管芯(例如，电源管理集成电路(PMIC)管芯)，射频(RF)管芯，传感器管芯，微型机电系统(MEMS)管芯，信号处理管芯(例如，数字信号处理(DSP)管芯)，前端管芯(例如，模拟前端(AFE)管芯)等，或其组合。而且，在一些实施例中，集成电路管芯126可以是不同的尺寸(例如，不同的高度和/或表面区域)，并且在其他实施例中，集成电路管芯126可以是相同的尺寸(例如，相同的高度和/或表面区域)。
在粘附至介电层112之前，可以根据适用的制造工艺处理集成电路管芯126，以在集成电路管芯126中形成集成电路。例如，每个集成电路管芯126都包括半导体衬底130，诸如掺杂或未掺杂的硅，或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料，诸如锗；化合物半导体，包括碳化硅，砷化镓，磷化镓，磷化铟，砷化铟和/或锑化铟；合金半导体，包括SiGe，GaAsP，AlInAs，AlGaAs，GaInAs，GaInP和/或GaInAsP；或其组合。也可以使用其他衬底，诸如多层或梯度衬底。诸如晶体管，二极管，电容器，电阻器等的器件可以形成在半导体衬底130中和/或上，并且可以通过互连结构132互连以形成集成电路，互连结构132由半导体衬底130上的一个或多个介电层中的金属化图案形成。
集成电路管芯126还包括焊盘134，诸如铝焊盘，外部连接形成在焊盘134上。焊盘134位于所谓的集成电路管芯126的相应有源侧上。钝化膜136位于集成电路管芯126上和焊盘134的部分上。开口延伸穿过钝化膜136至焊盘134。诸如导电柱(例如，包括诸如铜的金属)的管芯连接器138延伸穿过钝化膜136中的开口并且机械地和电气地连接至相应的焊盘134。管芯连接器138可以通过例如镀等形成。管芯连接器138电连接集成电路管芯126的相应集成电路。
介电材料140位于集成电路管芯126的有源侧上，诸如在钝化膜136和管芯连接器138上。介电材料140横向密封管芯连接器138，并且介电材料140与相应的集成电路管芯126横向相连。介电材料140可以是诸如PBO，聚酰亚胺，BCB等的聚合物；诸如氮化硅的氮化物；诸如氧化硅，PSG，BSG，BPSG等的氧化物；或者它们的组合，并且可以通过例如旋涂，层压，CVD等形成。
粘合剂128位于集成电路管芯126的背侧上，并且将集成电路管芯126粘附至背侧再分布结构106，诸如粘附至介电层112。粘合剂128可以是任何合适的粘合剂，环氧树脂，管芯附接膜(DAF)等。在一个实施例中，粘合剂128包括亲核添加剂。亲核添加剂可以是任何亲核试剂，诸如乙二醇，2-乙氧基乙醇，乙醇胺盐酸盐等。在一个实施例中，粘合剂128是具有亲核试剂的环氧树脂。粘合剂128可以施加到集成电路管芯126的背侧，或者可以施加在载体衬底102的表面上。例如，在分割以分离集成电路管芯126之前，粘合剂128可以施加到集成电路管芯126的背侧。
尽管一个集成电路管芯126被示出为粘附在第一封装件区域100A和第二封装件区域100B中的每一个中，但是应当理解，可以在每个封装件区域中粘附更多的集成电路管芯126。例如，可以在每个区域中粘附多个集成电路管芯126。此外，集成电路管芯126的尺寸可以变化。在一些实施例中，集成电路管芯126可以是具有大占用面积的管芯，诸如片上系统(SoC)器件。在集成电路管芯126具有大占用面积的实施例中，封装件区域中的通孔116的可用空间可能是有限的。当封装件区域具有可用于通孔116的有限空间时，使用背侧再分布结构106允许改进的互连布置。
在图7A中，在各个组件上形成密封剂142。在形成之后，密封剂142横向地密封通孔116和集成电路管芯126。密封剂142可以是模塑料，环氧树脂等。密封剂142可以具有与介电层112的CTE类似的CTE，这可以减少CTE失配，减少翘曲。在一些实施例中，密封剂142的CTE在约10ppm/℃至约65ppm/℃的范围内。在一个实施例中，密封剂142包括亲核添加剂。亲核添加剂可以是任何亲核试剂，诸如乙二醇，2-乙氧基乙醇，乙醇胺盐酸盐等。亲核添加剂可以是粘合剂128中的相同亲核添加剂。密封剂142可以通过压缩模塑，传递模塑等施加，并且可以形成在载体衬底102上方，使得通孔116和/或集成电路管芯126被掩埋或覆盖。然后使密封剂142固化。
图7B是在密封剂142固化之后密封剂142的区域14的详细视图。粘合剂128也可以固化。在固化之后，密封剂142和粘合剂128的一些亲核添加剂与介电层112的顶面上的悬空羟基反应，以在介电层112和密封剂142之间形成共价键。具体地，亲核添加剂的氧原子使羟基断裂，从而在亲核添加剂和介电层112的材料之间形成键。这种反应的一个实例示于图7C中。一些亲核添加剂可能不形成共价键，并且可以保留在密封剂142中。结果，可以改善介电层112和密封剂142之间的界面的粘附性。在一个实施例中，与缺少共价键的界面相比，粘附力可以增加多达22％，并且介电层112和密封剂142之间的界面可以承受高达14.8gf的力。可以类似地改善粘合剂128和介电层112之间的界面的粘附性。改善介电层112和密封剂142/粘合剂128之间的界面的粘附性可以减少后续处理步骤中界面分层的机会。在一些实施例中，共价键不消耗介电层112的顶面上的所有悬空羟基，并且一些痕量羟基保留在介电层112上或中。
在图8中，对密封剂142执行平坦化工艺以暴露通孔116和管芯连接器138。平坦化工艺还可以研磨介电材料140。在平坦化工艺之后，通孔116、管芯连接器138、介电材料140和密封剂142的顶面共面。平坦化工艺可以是例如化学机械抛光(CMP)，研磨工艺等。在一些实施例中，例如，如果通孔116和管芯连接器138已经暴露，则可以省略平坦化。
在图9中，在通孔116，密封剂142和集成电路管芯126上方形成前侧再分布结构144。前侧再分布结构144包括介电层146,148,150和152；以及金属化图案154，156和158。金属化图案也可以称为再分布层或再分布线。
前侧再分布结构144被示出为示例。可以在前侧再分布结构144中形成更多或更少的介电层和金属化图案。如果要形成更少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
作为形成前侧再分布结构144的示例，介电层146沉积在密封剂142上，穿过通孔116和管芯连接器138。在一些实施例中，介电层146由诸如PBO，聚酰亚胺，BCB等的光敏材料形成并且可以使用光刻掩模图案化。介电层146可以通过旋涂，层压，CVD等或其组合形成。然后图案化介电层146。图案化形成暴露通孔116和管芯连接器138的部分的开口(未示出)。图案化可以通过可接受的工艺，诸如当介电层146是光敏材料时将介电层146暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层146是光敏材料，则可以在曝光之后显影介电层146。
然后形成金属化图案154。金属化图案154包括在介电层146的主表面上并沿着介电层146的主表面延伸的导电线。金属化图案154还包括延伸穿过介电层146的导电通孔，以物理和电连接至通孔116和集成电路管芯126。为了形成金属化图案154，在介电层146上方和在穿过介电层146延伸的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶(未示出)。光刻胶可以通过旋涂等形成，并且可以曝光以进行图案化。光刻胶的图案对应于金属化图案154。图案化形成穿过光刻胶的开口以暴露晶种层。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可包括金属，如铜，钛，钨，铝等。导电材料和下面的晶种层的部分的组合形成金属化图案154。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻。
介电层148沉积在介电层146和金属化图案154上。介电层148可以以与介电层146类似的方式形成，并且可以由与介电层146相同的材料形成。
然后形成金属化图案156。金属化图案156包括在介电层148的主表面上并沿着介电层148的主表面延伸的导电线。金属化图案156还包括延伸穿过介电层148的导电通孔，以物理和电连接至金属化图案154。金属化图案156可以以与金属化图案154类似的方式形成，并且可以由与金属化图案154相同的材料形成。
介电层150沉积在介电层148和金属化图案156上。介电层150可以以与介电层146类似的方式形成，并且可以由与介电层146相同的材料形成。
然后形成金属化图案158。金属化图案158包括在介电层150的主表面上并沿着介电层150的主表面延伸的导电线。金属化图案158还包括延伸穿过介电层150的导电通孔，以物理和电连接至金属化图案156。金属化图案158可以以与金属化图案154类似的方式形成，并且可以由与金属化图案154相同的材料形成。
介电层152沉积在介电层150和金属化图案158上。介电层152可以以与介电层146类似的方式形成，并且可以由与介电层146相同的材料形成。
在图10中，UBM160形成在介电层152上并且延伸穿过介电层152。作为形成UBM160的示例，介电层152可以被图案化以形成暴露金属化图案158的部分的开口(未示出)。图案化可以通过可接受的工艺，诸如在介电层152是光敏材料时通过将介电层152暴露于光，或者通过使用例如各向异性蚀刻进行蚀刻。如果介电层152是光敏材料，则可以在曝光之后显影介电层152。用于UBM160的开口可以比用于金属化图案154、156和158的导电通孔部分的开口宽。在介电层152上方和在开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。可以通过旋涂等形成光刻胶，并且可以将光刻胶暴露于光以用于图案化。光刻胶的图案对应于UBM160。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过镀形成，诸如电镀或化学镀等。导电材料可包括金属，如铜，钛，钨，铝等。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，就去除晶种层的暴露部分，诸如通过使用可接受的蚀刻工艺，诸如通过湿或干蚀刻。晶种层的剩余部分和导电材料形成UBM160。在UBM160不同地形成的实施例中，可以使用更多的光刻胶和图案化步骤。
在图11A中，导电连接器162形成在UBM160上。导电连接器162可以是球栅阵列(BGA)连接器，焊球，金属柱，可控塌陷芯片连接(C4)凸块，微凸块，化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块等。导电连接器162可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，导电连接器162通过首先通过诸如蒸发，电镀，印刷，焊料转移，球放置等常用方法形成焊料层而形成。一旦在结构上形成了焊料层，就可以实施回流以将材料成形为所需的凸块形状。在另一实施例中，导电连接器162包括通过溅射，印刷，电镀，化学镀，CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，金属盖层(未示出)形成在金属柱的顶部上。金属盖层可以包括镍，锡，锡-铅，金，银，钯，铟，镍-钯-金，镍-金等，或它们的组合，并且可以通过镀工艺形成。
图11B是图11A的区域16的详细视图，示出了在形成导电连接器162之后的集成电路管芯126和前侧再分布结构144。在俯视图中，导电连接器162的子集沿着集成电路管芯126的边缘或拐角放置。集成电路管芯126的边缘由集成电路管芯126和密封剂142的界面限定。集成电路管芯126的边缘和拐角通常承受更高的机械应变。例如，沿集成电路管芯126的边缘和拐角的导电连接器162可能比集成电路管芯126的中心的导电连接器162承受高出10％的应变。UBM160类似地受到增加的应变。通过在先前步骤(例如，利用表面处理工艺122和124)中改进介电层112和密封剂142/粘合剂128之间的界面的粘附性，密封剂142和集成电路管芯126不太可能在前侧再分布结构144上施加压力。因此，在增加的应变下，UBM160从前侧再分布结构144分层的机会可以减小。因此可以避免更昂贵的分层解决方案，例如，重新布置集成电路管芯126或导电连接器162的位置。这可以允许集成电路管芯126更均匀地分布在所得到的第一封装件200中，允许密封剂142更均匀地分布在集成电路管芯126周围。
沿着集成电路管芯126的边缘和拐角的导电连接器162可以形成为与集成电路管芯126的边缘和拐角重叠。在一个实施例中，导电连接器162设置在集成电路管芯126的边缘或拐角附近的边缘区域中。边缘区域的边界设置在距集成电路管芯126的边缘或拐角的距离D2处。在一个实施例中，距离D2可以是约25μm。整个边缘区域可以被导电连接器162占据。导电连接器162的第一侧设置在边缘区域外部的距离D3处，并且导电连接器162的第二侧设置在边缘区域外部的距离D4处。在一个实施例中，距离D3和D4每个可以是相应导电连接器162的总宽度的至少四分之一。换句话说，当导电连接器162具有宽度时，每个相应的导电连接器162的宽度的至少四分之一设置在集成电路管芯126上方，并且每个相应导电连接器126的宽度的至少四分之一设置在密封剂142上方。沿着集成电路管芯126的边缘和拐角形成导电连接器162可以允许导电连接器162的数量增加，从而增加所得的第一封装件200的输入/输出(I/O)数量。
在图12中，执行载体衬底去接合以将载体衬底102与背侧再分布结构106(例如，介电层108)分离(去接合)。在去接合之后保留的部件(例如，在第一封装件区域100A和第二封装件区域100B中)形成第一封装件200。根据一些实施例，去接合包括在释放层104上投射诸如激光或UV光的光，使得释放层104在光的热量下分解，并且可以去除载体衬底102。然后将该结构翻转并放置在带164上。此外，穿过介电层108形成开口166以暴露金属化图案110的部分。开口166可以例如使用激光钻孔，蚀刻等形成。
图13A至图14示出了根据一些实施例的用于形成封装结构500(参见图14)的工艺期间的中间步骤的截面图。封装结构500可以称为叠层封装(PoP)结构。
在图13A中，第二封装件300附接到第一封装件200中的每一个。第二封装件300包括衬底302和连接到衬底302的一个或多个堆叠管芯308(308A和308B)。尽管示出了单数个堆叠的管芯308(308A和308B)，但是在其他实施例中，多个堆叠的管芯308(各自具有一个或多个堆叠的管芯)可以并排设置并连接到衬底302的同一表面。衬底302可以由诸如硅，锗，金刚石等的半导体材料制成。在一些实施例中，还可以使用诸如硅锗，碳化硅，砷化镓，砷化铟，磷化铟，碳化硅锗，磷砷化镓，磷化镓铟等化合物材料，以及它们的组合等。另外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括半导体材料层，诸如外延硅，锗，硅锗，SOI，绝缘体上硅锗(SGOI)，或其组合。在一个替代实施例中，衬底302基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。芯材料的替代物包括双马来酰亚胺-三嗪(BT)树脂，或者可选地，其他印刷电路板(PCB)材料或膜。诸如味之素构建膜(ABF)或其他层压板的构建膜可用于衬底302。
衬底302可以包括有源和无源器件(未示出)。诸如晶体管，电容器，电阻器，这些的组合等的各种器件可用于产生第二封装件300的设计的结构和功能要求。可使用任何合适的方法形成器件。
衬底302还可以包括金属化层(未示出)和导电通孔306。金属化层可以形成在有源器件和无源器件上，并且被设计为连接各个器件以形成功能电路。金属化层可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，其中通孔互连导电材料层并且可以通过任何合适的工艺(诸如沉积，镶嵌，双镶嵌等)形成。在一些实施例中，衬底302基本上没有有源和无源器件。
衬底302可以具有位于衬底302的第一侧上的接合焊盘303以连接到堆叠的管芯308，以及位于衬底302的第二侧上的接合焊盘304以连接至导电连接器314，第二侧与衬底302的第一侧相对。在一些实施例中，通过在衬底302的第一侧和第二侧上的介电层(未示出)内形成凹槽(未示出)来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入介电层中。在其他实施例中，省略凹槽，因为接合焊盘303和304可以形成在介电层上。在一些实施例中，接合焊盘303和304包括由铜，钛，镍，金，钯等或其组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304的导电材料。导电材料可以通过电化学镀工艺，化学镀工艺，CVD，原子层沉积(ALD)，PVD等或其组合形成。在一个实施例中，接合焊盘303和304的导电材料是铜，钨，铝，银，金等，或其组合。
在一个实施例中，接合焊盘303和304是UBM，其包括三层导电材料，诸如钛层，铜层和镍层。材料和层的其他布置，诸如铬/铬铜合金/铜/金的布置，钛/钛钨/铜的布置，或铜/镍/金的布置可用于形成接合焊盘303和304。可用于接合焊盘303和304的任何合适的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中，导电通孔306延伸穿过衬底302并将至少一个接合焊盘303连接到至少一个接合焊盘304。
在所示实施例中，堆叠的管芯308通过引线接合件310连接到衬底302，但是可以使用其他连接，诸如导电凸块。在一个实施例中，堆叠的管芯308是堆叠的存储器管芯。例如，堆叠的管芯308可以是存储器管芯，诸如低功率(LP)双倍数据速率(DDR)存储器模块，诸如LPDDR1，LPDDR2，LPDDR3，LPDDR4等存储器模块。
堆叠的管芯308和引线接合件310可以由模制材料312封装。模制材料312可以模制在堆叠的管芯308和引线接合件310上，例如，使用压缩模制。在一些实施例中，模制材料312是模制化合物，聚合物，环氧树脂，氧化硅填充材料等，或其组合。可以实施固化工艺以固化模制材料312；固化工艺可以是热固化，UV固化等，或它们的组合。
在一些实施例中，堆叠的管芯308和引线接合件310被掩埋在模制材料312中，并且在固化模制材料312之后，执行诸如研磨的平坦化步骤，以去除模制材料312的多余部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过导电连接器314，接合焊盘304和金属化图案110将第二封装件300机械地和电气地接合到第一封装件200。在一些实施例中，堆叠的管芯308可以通过引线接合件310，接合焊盘303和304，导电通孔306，导电连接器314和通孔116连接到集成电路管芯126。
在一些实施例中，阻焊剂(未示出)形成在衬底302的与堆叠管芯308相对的一侧上。导电连接器314可以设置在阻焊剂中的开口中以电气和机械地连接到衬底302中的导电部件(例如，接合焊盘304)。阻焊剂可用于保护衬底302的区域免受外部损坏。
在一些实施例中，导电连接器314在其回流之前具有形成在其上的环氧树脂焊剂(未示出)，其中在第二封装件300附接到第一封装件200之后保留环氧树脂焊剂的至少一些环氧树脂部分。
在一些实施例中，底部填充物316形成在第一封装件200和第二封装件300之间并围绕导电连接器314。底部填充物316可以减小应力并保护由导电连接器314的回流导致的接头。底部填充物316可以在附接第一封装200之后通过毛细管流动工艺形成，或者可以在附接第一封装件200之前通过合适的沉积方法形成。在形成环氧树脂焊剂的实施例中，它可以用作底部填充物316。
图13B是在第二封装件300附接到第一封装件200之后导电连接器314的区域18的详细视图。在自上而下的视图中，导电连接器314的子集沿着集成电路管芯126的边缘或拐角放置。类似于导电连接器162，沿集成电路管芯126的边缘和拐角放置的导电连接器314可能经受增加的应变。例如，沿着集成电路管芯126的边缘和拐角的导电连接器314可比集成电路管芯126的中心处的导电连接器314承受超过200％的更多应变。通过在先前步骤(例如，利用表面处理工艺122和124)中，改善介电层112和密封剂142/粘合剂128之间的界面的粘附性，可以降低介电层112在增加的应变下从集成电路管芯126分层的机会。因此可以避免更昂贵的分层解决方案，例如，重新布置集成电路管芯126或导电连接器314的位置。这可以允许集成电路管芯126更均匀地分布在所得到的第一封装件200中，允许密封剂142更均匀地分布在集成电路管芯126周围。
沿着集成电路管芯126的边缘和拐角的导电连接器314可以形成为与集成电路管芯126的边缘和拐角重叠。在一个实施例中，导电连接器314设置在集成电路管芯126的边缘或拐角附近的边缘区域中。边缘区域的边界设置在距集成电路管芯126的边缘或拐角的距离D5处。距离D5可以等于距离D2。在一个实施例中，距离D5可以是约25μm。整个边缘区域可以被导电连接器314占据。导电连接器314的第一侧设置在边缘区域外侧的距离D6处，并且导电连接器314的第二侧设置在边缘区域外侧的距离D7处。在一个实施例中，距离D6和D7可以各自为相应导电连接器314的总宽度的至少四分之一。换句话说，当导电连接器314具有宽度时，每个相应的导电连接器314的宽度的至少四分之一设置在集成电路管芯126上方，并且每个相应的导电连接器314的宽度的至少四分之一设置在密封剂142上方。
图13C是示出图13A的器件的一些部件的俯视图。为清楚起见，图13C中省略了一些部件或层。示出了集成电路管芯126的拐角，并且由密封剂142封装。示出了导电连接器314连接的金属化图案110的部分。导电连接器314连接到金属化图案110中的焊盘110A和110B。一些焊盘110B设置在集成电路管芯126的边缘或拐角附近的边缘区域中(例如，设置为小于距离集成电路管芯126的边缘的距离D5)。在一些实施例中，第一形状的焊盘110A设置在集成电路管芯126上方，并且第二形状的焊盘110B设置在密封剂142上方。在其他实施例中，焊盘都具有相同的形状。
在图14中，通过沿着划线区域(例如，在第一封装件区域100A和第二封装件区域100B之间)进行锯切来执行分割工艺。锯切从第二封装件区域100B分割第一封装件区域100A。得到的分割的第一封装件200和第二封装件300来自第一封装件区域100A或第二封装件区域100B中的一个。在一些实施例中，在第二封装件300附接到第一封装件200之后执行分割工艺。在其他实施例(未示出)中，在将第二封装件300附接到第一封装件200之前执行分割工艺，诸如在载体衬底102去接合并形成开口166之后。
然后使用导电连接器162将第一封装件200安装到封装衬底400。封装衬底400可以由诸如硅，锗，金刚石等的半导体材料制成。或者，也可以使用诸如硅锗，碳化硅，砷化镓，砷化铟，磷化铟，碳化硅锗，磷化镓砷，磷化镓铟，它们的组合等的化合物材料。另外，封装衬底400可以是SOI衬底。通常，SOI衬底包括半导体材料层，诸如外延硅，锗，硅锗，SOI，SGOI或其组合。在一个替代实施例中，封装衬底400基于绝缘芯，诸如玻璃纤维增强树脂芯。一种示例性芯材料是玻璃纤维树脂，诸如FR4。核心材料的替代物包括双马来酰亚胺-三嗪BT树脂，或者替代地，其他PCB材料或膜。诸如ABF或其他层压板的构建膜可以用于封装衬底400。
封装衬底400可以包括有源和无源器件(未示出)。如本领域普通技术人员将认识到的，可以使用诸如晶体管、电容器、电阻器、这些的组合等的各种各样的器件来产生封装结构500的设计的结构和功能要求。可以使用任何合适的方法形成器件。
封装衬底400还可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方，并且被设计成连接各个器件以形成功能电路。金属化层可以由交替的介电材料(例如，低k介电材料)和导电材料(例如，铜)形成，其中通孔互连导电材料层并且可以通过任何合适的工艺(诸如沉积，镶嵌，双镶嵌等)形成。在一些实施例中，封装衬底400基本上没有有源和无源器件。
在一些实施例中，导电连接器162被回流以将第一封装件200附接到接合焊盘402。导电连接器162将封装衬底400(包括封装衬底400中的金属化层)电气地和/或物理地连接到第一封装件200。在一些实施例中，在安装在封装衬底400上之前，无源器件(例如，表面安装器件(SMD)，未示出)可以附接至第一封装件200(例如，接合至接合焊盘402)。在这样的实施例中，无源器件可以与导电连接器162接合到第一封装件200的相同表面。
导电连接器162在其回流之前具有形成在其上的环氧树脂焊剂(未示出)，其中在第一封装件200附接到封装衬底400之后环氧树脂焊剂的至少一些环氧树脂部分保留。这些保留的环氧树脂部分可以用作底部填充物以减小应力并保护由回流导电连接器162所产生的接头。在一些实施例中，底部填充物(未示出)可以形成在第一封装件200和封装衬底400之间并围绕导电连接器162。在附接第一封装件200之后，可以通过毛细管流动工艺形成底部填充物，或者可以在附接第一封装200之前通过合适的沉积方法形成。
实施例可以实现优点。从介电层112去除残余金属120可以改善介电层112和密封剂142/粘合剂128之间的界面的粘附性。这可以允许导电连接器314形成为更靠近集成电路管芯126的边缘和拐角而没有分层。此外，通过改善界面的粘附性，密封剂142和集成电路管芯126不太可能在前侧再分布结构144上施加压力。这还可以允许导电连接器162形成为更靠近集成电路管芯126的边缘和角落而没有分层。因此可以增加所得器件的I/O数量。
在一个实施例中，一种器件包括：第一再分布结构，包括第一介电层；管芯，粘附至第一再分布结构的第一侧；密封剂，横向封装管芯，密封剂通过第一共价键与第一介电层接合；延伸穿过密封剂的通孔；第一导电连接器，电连接至第一再分布结构的第二侧，第一导电连接器的子集与密封剂和管芯的界面重叠。
在该器件的一些实施例中，密封剂包括模塑料和亲核试剂。在该器件的一些实施例中，亲核试剂是乙二醇，2-乙氧基乙醇或盐酸乙醇胺。在一些实施例中，该器件还包括：将管芯粘附至第一介电层的粘合剂，该粘合剂通过第二共价键接合到第一介电层。在该器件的一些实施例中，粘合剂包括环氧树脂和亲核试剂。在该器件的一些实施例中，第一导电连接器的子集中的每个相应导电连接器具有宽度，其中每个相应导电连接器的宽度的至少四分之一设置在管芯上方，其中每个相应导电连接器的宽度的至少四分之一设置在密封剂上方。在一些实施例中，该器件还包括：第二再分布结构，电连接至通孔和管芯，该密封剂设置在第一再分布结构和第二再分布结构之间；第二导电连接器电连接至第二再分布结构，第二导电连接器的子集与密封剂和管芯的界面重叠。在一些实施例中，该器件还包括：器件封装件，利用第一导电连接器连接至第一再分布结构；封装衬底，利用第二导电连接器连接至第二再分布结构。
在一个实施例中，一种方法包括：在第一金属化图案上方形成第一介电层；形成贯穿第一介电层的通孔，通孔电连接至第一金属化图案；将管芯粘附至第一介电层的第一表面；用第一共价键将密封剂粘合到第一介电层的第一表面上，密封剂横向密封管芯和通孔；在密封剂上方形成第二介电层；形成延伸穿过第二介电层的第二金属化图案，第二金属化图案电连接至管芯和通孔。
在一些实施例中，该方法还包括：形成电连接至第一金属化图案的第一导电连接器，第一导电连接器的子集与管芯的边缘或拐角重叠；用第一导电连接器将器件封装件连接到第一金属化图案。在一些实施例中，该方法还包括：形成电连接至第二金属化图案的第二导电连接器，第二导电连接器的子集与管芯的边缘或拐角重叠；用第二导电连接器将封装衬底连接到第二金属化图案。在一些实施例中，该方法还包括：处理第一介电层的第一表面以在第一介电层的第一表面上形成悬空羟基。在该方法的一些实施例中，将密封剂接合到第一介电层的第一表面包括：将密封剂分配在第一介电层的第一表面上，密封剂包括模塑料和亲核试剂；并且固化密封剂以在悬空羟基和亲核试剂之间形成第一共价键。在该方法的一些实施例中，将管芯粘附至第一介电层的第一表面包括：在管芯上分配粘合剂，该粘合剂包括环氧树脂和亲核试剂；并固化粘合剂以使悬空羟基与亲核试剂反应并形成第二共价键。在该方法的一些实施例中，处理第一介电层的第一表面包括：执行第一表面处理工艺以同时蚀刻和羟基化第一介电层的第一表面；并且执行第二表面处理工艺以去除通过蚀刻第一介电层的第一表面而暴露的残余金属。在该方法的一些实施例中，第一表面处理工艺是等离子体处理工艺，第二表面处理工艺是湿蚀刻工艺，其中等离子体处理工艺的前体包括O2和H2。
在一个实施例中，一种方法包括：通过具有晶种层的第一介电层镀通孔；蚀刻晶种层的暴露部分，蚀刻晶种层后晶种层的残余金属保留；处理第一介电层的第一表面以使第一表面羟基化并从第一表面除去晶种层的残余金属；将管芯粘附至羟基化的第一表面；用第一共价键将密封剂接合至羟基化的第一表面，密封剂横向密封管芯和通孔；以及在密封剂和管芯上方形成第二介电层。
在该方法的一些实施例中，将管芯粘附至羟基化的第一表面包括：用第二共价键将粘合剂接合至羟基化的第一表面，粘合剂将管芯粘附至羟基化的第一表面上。在该方法的一些实施例中，处理第一介电层的第一表面包括：执行第一表面处理工艺以使第一介电层的第一表面羟基化；并实施第二表面处理工艺以从羟基化的第一表面去除晶种层的残余金属。在该方法的一些实施例中，将密封剂接合到羟基化的第一表面包括：将密封剂分配在羟基化的第一表面上，密封剂包括模塑料和亲核试剂；并且固化密封剂以在羟基化的第一表面和亲核试剂之间形成第一共价键。
根据本发明的一些是实施例，提供了一种半导体器件，包括：第一再分布结构，包括第一介电层；管芯，粘附至所述第一再分布结构的第一侧；密封剂，横向密封所述管芯，所述密封剂通过第一共价键接合至所述第一介电层；通孔，延伸穿过所述密封剂；和第一导电连接器，电连接至所述第一再分布结构的第二侧，所述第一导电连接器的子集与所述密封剂和所述管芯的界面重叠。
在上述半导体器件中，所述密封剂包括模塑料和亲核试剂。
在上述半导体器件中，所述亲核试剂是乙二醇，2-乙氧基乙醇或盐酸乙醇胺。
在上述半导体器件中，还包括：粘合剂，将所述管芯粘附至所述第一介电层，所述粘合剂通过第二共价键接合至所述第一介电层。
在上述半导体器件中，所述粘合剂包括环氧树脂和亲核试剂。
在上述半导体器件中，所述第一导电连接器的子集的每个相应导电连接器具有宽度，其中，每个相应导电连接器的宽度的至少四分之一设置在所述管芯上方，其中，每个相应导电连接器的宽度的至少四分之一设置在所述密封剂上方。
在上述半导体器件中，还包括：第二再分布结构，电连接至所述通孔和所述管芯，所述密封剂设置在所述第一再分布结构和所述第二再分布结构之间；和
第二导电连接器，电连接至所述第二再分布结构，所述第二导电连接器的子集与所述密封剂和所述管芯的界面重叠。
在上述半导体器件中，还包括：器件封装件，通过所述第一导电连接器连接至所述第一再分布结构；和封装衬底，通过所述第二导电连接器连接至所述第二再分布结构。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：在第一金属化图案上方形成第一介电层；形成延伸穿过所述第一介电层的通孔，所述通孔电连接至所述第一金属化图案；将管芯粘附至所述第一介电层的第一表面；利用第一共价键将密封剂接合至所述第一介电层的第一表面，所述密封剂横向密封所述管芯和所述通孔；在所述密封剂上方形成第二介电层；和形成延伸通过所述第二介电层的第二金属化图案，所述第二金属化图案电连接至所述管芯和所述通孔。
在上述方法中，还包括：形成电连接至所述第一金属化图案的第一导电连接器，所述第一导电连接器的子集与所述管芯的边缘或拐角重叠；和利用所述第一导电连接器将器件封装件连接至所述第一金属化图案。
在上述方法中，还包括：形成电连接至所述第二金属化图案的第二导电连接器，所述第二导电连接器的子集与所述管芯的边缘或拐角重叠；和利用所述第二导电连接器将封装衬底连接到所述第二金属化图案。
在上述方法中，还包括：处理所述第一介电层的第一表面以在所述第一介电层的第一表面上形成悬空羟基。
在上述方法中，将所述密封剂接合至所述第一介电层的第一表面包括：将所述密封剂分配在所述第一介电层的第一表面上，所述密封剂包括模塑料和亲核试剂；和固化所述密封剂以在所述悬空羟基和所述亲核试剂之间形成第一共价键。
在上述方法中，将所述管芯粘附至所述第一介电层的第一表面包括：在所述管芯上分配粘合剂，所述粘合剂包括环氧树脂和亲核试剂；和固化所述粘合剂以使所述悬空羟基与所述亲核试剂反应并形成第二共价键。
在上述方法中，处理所述第一介电层的第一表面包括：执行第一表面处理工艺以同时蚀刻和羟基化所述第一介电层的第一表面；和执行第二表面处理工艺以去除通过蚀刻所述第一介电层的第一表面而暴露的残余金属。
在上述方法中，所述第一表面处理工艺是等离子体处理工艺，并且所述第二表面处理工艺是湿蚀刻工艺，其中，所述等离子体处理工艺的前体包括O2和H2。
根据本发明的另一些实施例，还提供了一种形成半导体器件的方法，包括：穿过第一介电层利用晶种层镀通孔；蚀刻所述晶种层的暴露部分，蚀刻所述晶种层后保留晶种层的残余金属；处理所述第一介电层的第一表面以使所述第一表面羟基化并且从所述第一表面去除所述晶种层的残余金属；将管芯粘附至羟基化的第一表面；和利用第一共价键将密封剂接合至所述羟基化的第一表面，所述密封剂横向密封所述管芯和所述通孔；和在所述密封剂和所述管芯上方形成第二介电层。
在上述方法中，将所述管芯粘附至所述羟基化的第一表面包括：利用第二共价键将粘合剂接合至所述羟基化的第一表面，所述粘合剂将所述管芯粘合至所述羟基化的第一表面。
在上述方法中，处理所述第一介电层的第一表面包括：实施第一表面处理工艺以使所述第一介电层的第一表面羟基化；和实施第二表面处理工艺以从羟基化的第一表面去除所述晶种层的残余金属。
在上述方法中，将所述密封剂接合至所述羟基化的第一表面包括：将所述密封剂分配在所述羟基化的第一表面上，所述密封剂包括模塑料和亲核试剂；和固化所述密封剂以在所述羟基化的第一表面和所述亲核试剂之间形成所述第一共价键。
上面概述了若干实施例或实例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一再分布结构，包括第一介电层；
管芯，粘附至所述第一再分布结构的第一侧；
密封剂，横向密封所述管芯，所述密封剂通过第一共价键接合至所述第一介电层；
通孔，延伸穿过所述密封剂；和
第一导电连接器，电连接至所述第一再分布结构的第二侧，所述第一导电连接器的子集与所述密封剂和所述管芯的界面重叠。
2.根据权利要求1所述的半导体器件，其中，所述密封剂包括模塑料和亲核试剂。
3.根据权利要求2所述的半导体器件，其中，所述亲核试剂是乙二醇，2-乙氧基乙醇或盐酸乙醇胺。
4.根据权利要求2所述的半导体器件，还包括：
粘合剂，将所述管芯粘附至所述第一介电层，所述粘合剂通过第二共价键接合至所述第一介电层。
5.根据权利要求4所述的半导体器件，其中，所述粘合剂包括环氧树脂和亲核试剂。
6.根据权利要求1所述的半导体器件，其中，所述第一导电连接器的子集的每个相应导电连接器具有宽度，其中，每个相应导电连接器的宽度的至少四分之一设置在所述管芯上方，其中，每个相应导电连接器的宽度的至少四分之一设置在所述密封剂上方。
7.根据权利要求1所述的半导体器件，还包括：
第二再分布结构，电连接至所述通孔和所述管芯，所述密封剂设置在所述第一再分布结构和所述第二再分布结构之间；和
第二导电连接器，电连接至所述第二再分布结构，所述第二导电连接器的子集与所述密封剂和所述管芯的界面重叠。
8.根据权利要求7所述的半导体器件，还包括：
器件封装件，通过所述第一导电连接器连接至所述第一再分布结构；和
封装衬底，通过所述第二导电连接器连接至所述第二再分布结构。
9.一种形成半导体器件的方法，包括：
在第一金属化图案上方形成第一介电层；
形成延伸穿过所述第一介电层的通孔，所述通孔电连接至所述第一金属化图案；
将管芯粘附至所述第一介电层的第一表面；
利用第一共价键将密封剂接合至所述第一介电层的第一表面，所述密封剂横向密封所述管芯和所述通孔；
在所述密封剂上方形成第二介电层；和
形成延伸通过所述第二介电层的第二金属化图案，所述第二金属化图案电连接至所述管芯和所述通孔。
10.一种形成半导体器件的方法，包括：
穿过第一介电层利用晶种层镀通孔；
蚀刻所述晶种层的暴露部分，蚀刻所述晶种层后保留晶种层的残余金属；
处理所述第一介电层的第一表面以使所述第一表面羟基化并且从所述第一表面去除所述晶种层的残余金属；
将管芯粘附至羟基化的第一表面；和
利用第一共价键将密封剂接合至所述羟基化的第一表面，所述密封剂横向密封所述管芯和所述通孔；和
在所述密封剂和所述管芯上方形成第二介电层。
CN201910454554.1A 2018-06-29 2019-05-29 半导体封装件和方法 Active CN110660753B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862692136P 2018-06-29 2018-06-29
US62/692,136 2018-06-29
US16/266,446 US11049805B2 (en) 2018-06-29 2019-02-04 Semiconductor package and method
US16/266,446 2019-02-04

Publications (2)

Publication Number Publication Date
CN110660753A true CN110660753A (zh) 2020-01-07
CN110660753B CN110660753B (zh) 2022-09-16

Family

ID=68886168

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910454554.1A Active CN110660753B (zh) 2018-06-29 2019-05-29 半导体封装件和方法

Country Status (5)

Country Link
US (3) US11049805B2 (zh)
KR (1) KR102259707B1 (zh)
CN (1) CN110660753B (zh)
DE (1) DE102019103729B4 (zh)
TW (1) TWI695438B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113140516A (zh) * 2020-01-17 2021-07-20 台湾积体电路制造股份有限公司 封装件及其形成方法
CN113140535A (zh) * 2020-05-04 2021-07-20 台湾积体电路制造股份有限公司 传感器器件、传感器封装件及其形成方法
CN113178392A (zh) * 2020-03-30 2021-07-27 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN113540049A (zh) * 2020-04-16 2021-10-22 台湾积体电路制造股份有限公司 半导体封装件和制造半导体封装件的方法
CN113808960A (zh) * 2020-08-26 2021-12-17 台湾积体电路制造股份有限公司 集成电路封装件和方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11088057B2 (en) * 2019-05-10 2021-08-10 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10879221B2 (en) * 2019-05-16 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure
US11521958B2 (en) * 2019-11-05 2022-12-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package with conductive pillars and reinforcing and encapsulating layers
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11508633B2 (en) * 2020-05-28 2022-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having taper-shaped conductive pillar and method of forming thereof
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345231A (zh) * 2007-07-12 2009-01-14 东部高科股份有限公司 半导体芯片器件及其制造方法和包括其的堆叠封装
CN103681367A (zh) * 2012-09-12 2014-03-26 台湾积体电路制造股份有限公司 封装方法和封装器件
CN105073760A (zh) * 2013-02-25 2015-11-18 韩国生产技术研究院 具有烷氧基甲硅烷基基团的环氧化合物，其制造方法，包含其的组合物和固化产物，及其用途
CN105679718A (zh) * 2014-12-03 2016-06-15 台湾积体电路制造股份有限公司 半导体封装件及其形成方法
CN105789062A (zh) * 2014-09-05 2016-07-20 台湾积体电路制造股份有限公司 封装件结构及其形成方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6746954B2 (en) * 2002-07-02 2004-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of reworking tungsten particle contaminated semiconductor wafers
US8541532B2 (en) 2007-02-09 2013-09-24 Nippon Shokubai Co., Ltd. Silane compound, production method thereof, and resin composition containing silane compound
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
WO2011058999A1 (ja) 2009-11-13 2011-05-19 日立化成工業株式会社 フィルム状接着剤の製造方法、接着シート並びに半導体装置及びその製造方法
US9985150B2 (en) 2010-04-07 2018-05-29 Shimadzu Corporation Radiation detector and method of manufacturing the same
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
CN103094325B (zh) * 2011-11-02 2016-08-10 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US10739673B2 (en) * 2014-06-20 2020-08-11 Taiwan Semiconductor Manufacturing Company Limited Preparing patterned neutral layers and structures prepared using the same
US9425178B2 (en) 2014-07-08 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. RDL-first packaging process
CN108137786A (zh) 2015-08-19 2018-06-08 汉高知识产权控股有限责任公司 助熔底部填充组合物
DE102015121344B4 (de) 2015-12-08 2023-11-02 Infineon Technologies Austria Ag Halbleitervorrichtung und verfahren zu ihrer herstellung
JP6780259B2 (ja) 2016-02-22 2020-11-04 富士ゼロックス株式会社 ポリイミド前駆体組成物、及びポリイミド前駆体組成物の製造方法
US10090194B2 (en) 2016-03-18 2018-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345231A (zh) * 2007-07-12 2009-01-14 东部高科股份有限公司 半导体芯片器件及其制造方法和包括其的堆叠封装
CN103681367A (zh) * 2012-09-12 2014-03-26 台湾积体电路制造股份有限公司 封装方法和封装器件
CN105073760A (zh) * 2013-02-25 2015-11-18 韩国生产技术研究院 具有烷氧基甲硅烷基基团的环氧化合物，其制造方法，包含其的组合物和固化产物，及其用途
CN105789062A (zh) * 2014-09-05 2016-07-20 台湾积体电路制造股份有限公司 封装件结构及其形成方法
CN105679718A (zh) * 2014-12-03 2016-06-15 台湾积体电路制造股份有限公司 半导体封装件及其形成方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
金玉丰等: "《微米纳米器件封装技术》", 31 October 2012, 北京：国防工业出版社 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113140516A (zh) * 2020-01-17 2021-07-20 台湾积体电路制造股份有限公司 封装件及其形成方法
CN113140516B (zh) * 2020-01-17 2024-03-12 台湾积体电路制造股份有限公司 封装件及其形成方法
CN113178392A (zh) * 2020-03-30 2021-07-27 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN113178392B (zh) * 2020-03-30 2024-03-29 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN113540049A (zh) * 2020-04-16 2021-10-22 台湾积体电路制造股份有限公司 半导体封装件和制造半导体封装件的方法
CN113140535A (zh) * 2020-05-04 2021-07-20 台湾积体电路制造股份有限公司 传感器器件、传感器封装件及其形成方法
US11942417B2 (en) 2020-05-04 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor package and method
CN113808960A (zh) * 2020-08-26 2021-12-17 台湾积体电路制造股份有限公司 集成电路封装件和方法

Also Published As

Publication number Publication date
TW202002110A (zh) 2020-01-01
DE102019103729A1 (de) 2020-01-02
US20210327806A1 (en) 2021-10-21
US11508656B2 (en) 2022-11-22
US20200006220A1 (en) 2020-01-02
KR102259707B1 (ko) 2021-06-03
TWI695438B (zh) 2020-06-01
DE102019103729B4 (de) 2022-01-13
US11049805B2 (en) 2021-06-29
CN110660753B (zh) 2022-09-16
KR20200002591A (ko) 2020-01-08
US20230090895A1 (en) 2023-03-23

Similar Documents

Publication Publication Date Title
CN110660753B (zh) 半导体封装件和方法
US10971477B2 (en) Semiconductor packages and methods of forming the same
CN109786266B (zh) 半导体封装件及其形成方法
CN107808870B (zh) 半导体封装件中的再分布层及其形成方法
CN109786267B (zh) 半导体封装件和方法
US10037963B2 (en) Package structure and method of forming the same
CN107833864B (zh) 封装结构及其形成方法
US11728249B2 (en) Semiconductor package and method
CN109786360B (zh) 半导体封装件和方法
CN110957281A (zh) 集成电路封装件和方法
TWI749088B (zh) 半導體裝置的製造方法
CN110797270B (zh) 半导体封装件和方法
KR102295360B1 (ko) 집적형 팬아웃 패키지 및 그를 형성하는 방법
CN111106020B (zh) 集成电路封装件和方法
US20230335471A1 (en) Semiconductor packages
US20230335536A1 (en) Semiconductor Packages and Methods of Forming the Same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant