CN105679718A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN105679718A
CN105679718A CN201510760391.1A CN201510760391A CN105679718A CN 105679718 A CN105679718 A CN 105679718A CN 201510760391 A CN201510760391 A CN 201510760391A CN 105679718 A CN105679718 A CN 105679718A
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China
Prior art keywords
hole
layer
crystal seed
integrated circuit
dielectric layer
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CN201510760391.1A
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CN105679718B (zh
Inventor
余振华
刘重希
林志伟
郭宏瑞
郑明达
胡毓祥
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了一种半导体器件和用于形成半导体器件的方法。该半导体器件包括具有邻近集成电路管芯的通孔的集成电路，其中，模塑料插入在集成电路管芯和通孔之间。通孔具有延伸穿过图案化层并且从图案化层突出以暴露出锥形的侧壁的突出件。本发明实施例涉及半导体封装件及其形成方法。

Description

半导体封装件及其形成方法
优先权声明和交叉引用
本申请是于2015年4月24日提交的名称为“SemiconductorPackagesandMethodsofFormingtheSame”的共同拥有的美国专利申请第14/696,198号的部分连续申请。本申请也要求于2014年12月3日提交的名称为“SemiconductorPackagesandMethodsofFormingtheSame”的美国临时专利申请第62/087,167号的优先权，其全部内容结合于此作为参考。
技术领域
本发明实施例涉及半导体封装件及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人计算机、手机、数码相机和其他电子设备。通常通过以下步骤来制造半导体器件：在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体材料层；以及使用光刻来图案化各个材料层，以在各个材料层上形成电路组件和元件。通常，在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单个的管芯。然后，以多芯片模式或以其他封装类型来单独地封装单独的管芯。
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度不断提高，半导体产业已经经历了快速的发展。在很大程度上，集成度的这种提高源自于最小部件尺寸的不断减小(例如，将半导体工艺节点向着亚20nm节点减小)，这允许更多的组件集成在给定区域内。由于近来对小型化、更高的速度和更大的带宽以及较低的功耗和延迟的需求的产生，产生了对用于半导体管芯的更小和更富创造性的封装技术。
随着半导体技术的进一步发展，已经出现了堆叠式半导体器件(例如，三维集成电路(3DIC))，以作为进一步减小半导体器件的物理尺寸的有效可选方式。在堆叠式半导体器件中，在不同的半导体晶圆上制造诸如逻辑电路、存储器电路、处理器电路等的有源电路。两个或更多的半导体晶圆可安装或堆叠在另一个的顶部上以进一步降低半导体器件的形状因数。叠层封装(POP)器件是一种3DIC，其中，封装管芯并且然后将管芯与其他封装的管芯或多个管芯封装在一起。
发明内容
根据本发明的一些实施例，提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上形成第一层；在所述第一层中形成第一开口；沿着所述第一层的顶面、所述第一开口的侧壁和所述第一开口的底部形成一个或多个晶种层；在所述一个或多个晶种层上形成通孔，所述通孔延伸至所述第一开口内；在所述第一层上方放置半导体管芯；邻近所述通孔和所述半导体管芯的侧壁形成模塑料；去除所述载体衬底；去除所述一个或多个晶种层的至少部分以暴露出所述通孔的顶部；以及去除所述第一层的部分以暴露出所述通孔的侧壁的部分。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成第一介电层；在所述第一介电层上方形成一个或多个晶种层；在所述一个或多个晶种层上方形成通孔，所述一个或多个晶种层和所述通孔延伸穿过所述第一介电层；在所述第一介电层上方放置集成电路管芯；在所述集成电路管芯和所述通孔之间形成密封剂；去除所述衬底；以及去除所述一个或多个晶种层的部分和所述第一介电层的部分以暴露出所述通孔的侧壁的部分。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：第一介电层；集成电路，位于所述第一介电层上；通孔，围绕所述集成电路；以及密封剂，位于所述第一介电层上并且插入在所述集成电路和所述通孔之间；其中，所述通孔的部分从所述第一介电层突出。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图16是根据一些实施例的用于形成半导体器件的各个中间步骤的截面图。
图17A至图17C示出了根据一些实施例的用于通孔的开口轮廓的截面图。
图18至图31是根据一些实施例的用于形成半导体器件的各个中间步骤的截面图。
图32至图34是根据一些实施例的形成半导体器件的各个中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且本文使用的空间相对描述符可以同样地作相应的解释。
将结合具体的环境中的实施例进行描述实施例，即，三维(3D)集成扇出(InFO)叠层封装(PoP)器件。然而，其他实施例也可以应用于其他电连接部件，包括，但不限于，叠层封装组件、管芯至管芯组件、晶圆至晶圆组件、管芯至衬底组件、组装中封装、处理中衬底、中介板、衬底等或者安装输入部件、板、芯片或其他部件，或用于连接封装或安装的任何类型的集成电路或电子部件的组合。
图1至图16示出了根据一些实施例的在形成半导体封装件中的中间步骤的截面图。图1是载体衬底40的截面图。例如，载体衬底40包括基于硅的材料(诸如硅晶圆、玻璃或氧化硅)或其他材料(诸如氧化铝)、陶瓷材料、这些材料的任意组合等。在一些实施例中，载体衬底40是平坦的以适应进一步的处理。在一些实施例中，载体衬底40可以是晶圆，在晶圆上形成多个封装件结构。载体衬底40可以是为载体衬底40上方的层提供(在制造工艺的中间操作期间)机械支撑的任何合适的衬底。
图2是根据一些实施例的载体衬底40上的释放层42的截面图。释放层42可以由聚合物基材料形成，释放层42可以与载体衬底40一起从在随后步骤中将形成的上面的结构。在一些实施例中，释放层42是诸如光热转换(LTHC)释放涂层的环氧化物基热释放材料，该材料在被加热时失去其粘性。在其他实施例中，释放层42可以是紫外(UV)胶，当紫外(UV)胶暴露于UV光时，失去其粘性。释放层42可以作为液体进行分配并且被固化，释放层42可以是层压在载体衬底40上的层压膜等。
图3是根据一些实施例的释放层42上的第一图案化层44的截面图。如将在下文进行详细的讨论，第一图案化层44被图案化为具有开口，在后续工艺中形成的通孔将在开口中延伸。第一图案化层44可以是聚合物(诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等)、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)或它们的组合等)等并且可以通过例如旋涂、层压、化学汽相沉积(CVD)等形成。在一些实施例中，第一图案化层44是光刻胶材料并且通过暴露于穿过图案化掩模的光而被图案化，从而在光刻胶材料中产生第一开口47。
图4是根据一些实施例的随后在释放层42的部分和第一图案化层44上方形成的通孔的晶种层46的截面图。可以在第一图案化层44上方和在第一图案化层44中形成的第一开口47中形成晶种层46。在一些实施例中，晶种层46是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。晶种层46可由铜、钛、镍、金或它们的组合等制成。在一些实施例中，晶种层46包括钛层和位于钛层上方的铜层。例如，可以使用物理汽相沉积(PVD)、化学汽相沉积(CVD)、原子层沉积(ALD)、它们的组合等形成晶种层46。晶种层46可以包括一层或多层。
如将在下面详细地讨论，利用晶种层46形成通孔，在形成通孔之后，可以去除晶种层46的部分以形成凹槽。晶种层46的厚度，或者如果利用复合晶种层，复合晶种层的一层或多层，可以用于控制从第一图案化层44的底面至通孔50的凹槽深度(见图6)。相应地，可以选择晶种层46的厚度和材料以帮助控制凹槽。例如，在一些实施例中，晶种层46可以包括钛层和上面的铜层。在该实施例中，可以选择性地去除钛层，从而产生凹槽并且暴露出铜层。在一些实施例中，第一晶种层(例如，钛层)的厚度为约0.01μm至约5μm，并且第二晶种层(例如，铜层)的厚度为约0.01μm至约5μm。在其他实施例中，可以利用其他材料。
图5是根据一些实施例的位于晶种层46上方的第二图案化层48的截面图，第二图案化层48具有第二开口49以暴露出第一开口47的至少部分。可以通过诸如旋涂工艺的湿工艺，或者通过干工艺或施加干膜形成第二图案化层48，并且第二图案化层48可以暴露于光以图案化。图案化形成穿过第二图案化层48的第二开口49以暴露出晶种层46的部分和第一开口47，并且第二开口49的宽度可以宽于第一开口47的宽度。在一些实施例中，第二图案化层48包括光刻胶层并且使用光刻技术被图案化。在另一实施例中，诸如氧化硅或氮化硅的其他材料可以用作第二图案化层48。
图6是根据一些实施例的导电材料的截面图，导电材料填充第一开口47(见图3)和位于晶种层46的暴露部分上的第二图案化层48的第二开口49(见图5)以形成通孔50。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝或它们的组合的金属，并且可以具有包括多层的复合结构。如图6所示，通孔50包括主体部分和当通孔50延伸穿过第一图案化层44时的窄突出件，主体部分具有第一宽度w1，窄突出件具有第二宽度w2。通孔50包括具有介于第一宽度w1和第二宽度w2之间的宽度w3的凸耳或凹槽。通孔50的第一宽度w1可以在从约20μm至约500μm的范围内，第二宽度w2可以在从约20μm至约500μm的范围内，并且第三宽度w3可以在从约0μm至约100μm的范围内。通孔50的主体部分的第一高度h1可以在从约20μm至约1000μm的范围内，并且通孔50的窄突出件的第二高度h2可以在从约0.01μm至约50μm的范围内。
图7是根据一些实施例的去除第二图案化层48(见图6)之后的通孔50的截面图。在一些实施例中，其中，第二图案化层48包括光刻胶材料，可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除第二图案化层48，并且也可以通过在丙酮、异丙醇和去离子水等中冲洗去除第二图案化层48。一旦去除第二图案化层48，暴露出晶种层46的未被通孔50覆盖的部分。
图8示出了根据一些实施例的暴露的晶种层46的去除。可以通过，例如，使用可接受的蚀刻工艺(诸如通过湿或干蚀刻)去除暴露的晶种层46以暴露出第一图案化层44的至少部分。
图9示出了根据一些实施例的将集成电路管芯52附接至第一图案化层44。在一些实施例中，集成电路管芯52可以通过粘合剂54(诸如管芯附接膜(DAF))附接至第一图案化层44。粘合剂54的厚度可以在从约0.01μm至约100μm的范围内。集成电路管芯52可以是如图9所示的单个管芯，或在一些实施例中，可以附接两个或两个以上的管芯，以及可以包括适合特定方法的任何管芯。例如，集成电路管芯52可以包括静态随机存取存储器(SRAM)芯片或动态随机存取存储器(DRAM)芯片、处理器、存储芯片、逻辑芯片、模拟芯片、数字芯片、中央处理单元(CPU)，图形处理单元(GPU)或它们的组合等。集成电路管芯52可以附接至适合的位置以用于特定的设计或应用。例如，图9示出了一实施例，其中，集成电路管芯52安装在中心区域，其中，通孔50被设置在周界周围。在其他实施例中，集成电路管芯52可以从中心偏移。在附接至第一图案化层44之前，可以根据适用的制造工艺处理集成电路管芯52以在集成电路管芯52中形成集成电路。
在一些实施例中，集成电路管芯52安装至第一图案化层44，从而使得管芯连接件56面向为远离第一图案化层44或位于第一图案化层44的远端。管芯连接件56提供至形成在集成电路管芯52上的电路的电连接。管芯连接件56可以形成在集成电路管芯52的有源侧上，或者可以形成在背侧上并且包括通孔。管芯连接件56可以进一步包括在集成电路管芯52的第一侧和第二侧之间提供电连接的通孔。在实施例中，管芯连接件56的导电材料是铜、钨、铝、银、金、锡、它们的组合等。
根据一些实施例，图10示出了通过密封剂58封装集成电路管芯52以及通孔50。密封剂58放置在集成电路管芯52和周围的通孔50之间的间隙中。例如，可以使用压缩模制将密封剂58模制在集成电路管芯52和通孔50上。在一些实施例中，密封剂58由模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合制成。可以实施固化步骤以固化密封剂58，其中，固化可以是热固化、UV固化、类似物或它们的组合。可以使用其他封装工艺，诸如层压、压缩模制等。
在一些实施例中，模制材料完全地覆盖集成电路管芯52的上表面。在这些实施例中，可以在模制材料58上实施诸如研磨的平坦化步骤以暴露出集成电路管芯52和管芯连接件56。在一些实施例中，管芯连接件56的表面和通孔50的表面与模制材料58的表面共平面。通孔50可以称为模制通孔(TMV)、封装件通孔(TPV)和/或InFO(集成的扇出)通孔(TIV)。
图11示出了根据一些实施例的再分布结构60的形成。再分布结构60可以包括任意数量的介电层、金属化图案和通孔。例如，图11示出了一个实施例，在该实施例中，再分布结构60包括三个具有各自金属化图案和通孔的介电层62、64、66，如将在下文进行讨论，尽管其他实施例可以具有更少或更多的介电层。
在密封剂58和管芯连接件56上形成第一介电层62。在一些实施例中，第一介电层62由聚合物形成，聚合物可以是使用光刻可以图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。在其他实施例中，第一介电层62由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等形成。可以通过旋涂、层压、化学汽相沉积(CVD)等或它们的组合形成第一介电层62。然后图案化第一介电层62以形成开口，从而暴露出管芯连接件56和通孔50的部分。可以通过可接受的工艺进行图案化，诸如当介电层是光敏材料时，通过将第一介电层62暴露于光或者例如通过使用图案化掩模和各向异性蚀刻的蚀刻。
在第一介电层62上形成具有通孔72的第一金属化图案70。作为形成第一金属化图案70和通孔72的实例，在第一介电层62上方和在第一介电层62中形成的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理汽相沉积(PVD)等形成晶种层。根据期望的再分布图案，然后在晶种层上形成掩模并且图案化掩模。在一些实施例中，掩模是通过旋涂等形成并且暴露于光以用于图案化的光刻胶。掩模的图案对应于具有通孔72的第一金属化图案72。图案化形成了穿过掩模的开口以暴露出晶种层。在掩模的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成第一金属化图案70和通孔72。第二介电层64形成在第一介电层62上方以为随后的层提供更平坦的表面。在一些实施例中，第二介电层64由聚合物、氮化物、氧化物等形成。在一些实施例中，第二介电层64是通过旋涂工艺形成的PBO。
第三介电层66、第二金属化图案68和通孔74形成在第二介电层64和第一金属化图案70上。可以使用如上讨论的用于形成第一介电层62、第一金属化图案70和通孔72的类似工艺和类似材料来形成第三介电层66、第二金属化图案68和通孔74。通孔74互连金属化图案68和70。在第三介电层66和周围的第二金属化图案68上形成第四介电层67。在一些实施例中，第四介电层67由聚合物形成，聚合物可以是使用光刻掩模可以图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中，第四介电层67由诸如氮化硅、氧化硅的氮化物或氧化物、PSG、BSG、BPSG等形成。可以通过旋涂、层压、CVD、类似物或它们的组合形成第四介电层67。然后图案化第四介电层67以产生第三开口71。可以通过可接受的工艺进行图案化，诸如当介电层是光敏材料时，通过将第四介电层67暴露于光或者例如通过使用各向异性蚀刻的蚀刻。
再分布层60可以称为在集成电路管芯52上的前侧再分布层。通过电连接至一个或多个其他封装件、封装件衬底、组件等或它们的组合，可以利用前侧再分布层60提供至集成电路管芯52外部电连接和/或将集成电路管芯52电连接至通孔50。示出的再分布层60中的金属化层的数量仅用于说明的目的并不限制。可以具有不同于图11中示出的那些的任意的数量的介电层和金属化图案。
图12示出了根据一些实施例的第三开口71(见图11)中的凸块下金属(UBM)75的形成。UBM75可以包括多个层，诸如钛层、随后的铜层和第三Ni层。在一些实施例中，UBM75可以包括钛(Ti)层、钽(Ta)层和氮化钽(TaN)层中的一层。可以通过电镀或化学镀的方法图案化UBM焊盘。
图13示出了在UBM75上方形成一组导电连接件76并且导电连接件76电连接至再分布层60。导电连接件76可以是焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块、它们的组合(例如，附接有焊球的金属柱)等。导电连接件76可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在导电连接件76是焊料凸块的实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转印、球植等常用的方法形成焊料层来形成导电连接件76。一旦已经在结构上形成焊料层，可以实施回流以将材料成形为期望的凸块形状。在另一个实施例中，导电连接件76是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以没有焊料并且具有基本上垂直的侧壁。
图14根据一些实施例示出了去除载体衬底40和释放层42以暴露出第一图案化层44，并且示出了去除通孔50上的晶种层46的一层或多层。根据一些实施例，脱粘包括将诸如激光或UV光的光投射在释放层42上(见图13)，从而使得释放层在光的热量下分解，并且载体衬底40可以被去除。可以实施清洗和/或研磨工艺以去除释放层的残余部分。在另一实施例中，可以使用热工艺、化学剥离工艺、激光去除、UV处理等或它们的组合。在使载体衬底40和释放层42脱粘之后，暴露出晶种层46的一层或多层。通过可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层46的一层或多层。在去除暴露的晶种层之后，然后暴露出通孔50。在一些实施例中，晶种层46的一层或多层可以保留在通孔50上方。晶种层46的去除的层的厚度将控制凹槽的深度，凹槽的深度为在第一图案化层44的密封剂58远端的表面与晶种层46和/或通孔50的暴露表面之间。下面将参照图17A至图17C详细的讨论凹槽。
图15示出了在通孔50上方并且电连接至通孔50的一组导电连接件78的形成。导电连接件78可以是焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件78可以包括诸如焊料、铜、铝、金、镍、银、钯、锡、它们的组合等的导电材料。在导电连接件78是焊料凸块的实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转印、球植等常用的方法形成焊料层来形成导电连接件78。一旦已经在结构上形成焊料层，可以实施回流以将材料成形为期望的凸块形状。在另一个实施例中，导电连接件78是通过溅射、印刷、电子电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以没有焊料并且具有基本上垂直的侧壁。导电连接件78的直径可以在从约20μm至约500μm的范围内。
图16示出了根据一些实施例的通过粘合材料82的额外粘合支撑将导电连接件78电连接至衬底80。衬底80可以是任何衬底，诸如集成电路管芯、封装件、印刷电路板、中介板等。在一些实施例中，粘合材料82可以是环氧树脂或胶水，并且可以将其施加至导电连接件78。在一些实施例中，导电连接件78可以直接地附接至通孔50。光或UV光可以用于固化介于晶圆80和导电连接件78之间的粘合材料82。
在一些实施例中，也可以在导电连接件78和通孔50之间利用UBM结构。UBM结构可以类似于UBM75。
图17A至图17C示出了根据各个实施例的如图14中示出的凹槽79的各个配置。多层晶种层的使用允许利用晶种层以控制凹槽79的深度。例如，在诸如图17A至图17C中示出的那些的实施例中，利用具有第一晶种层83(诸如钛层)和第二晶种层84(诸如铜层)的多层晶种层46。在诸如这些实施例中，通过依赖第一晶种层83和第二晶种层84的材料之间的蚀刻选择性，从而第二晶种层84用作蚀刻停止层以用于去除第一晶种层83，第一晶种层83的厚度限定了凹槽79的深度。在一些实施例中，第一晶种层83的厚度和凹槽79的深度R为约0.01μm至约5μm。在其他实施例中，第一晶种层83和第二晶种层84可以从通孔50的端部去除，从而完全地去除晶种层46并且暴露出通孔50。
图17A至图17C进一步示出用于开口47(见图3)的各个侧壁轮廓。例如，图17A示出了一个实施例，在该实施例中，通孔50的突出件具有延伸穿过第一图案化层44的基本上垂直的侧壁。图17B示出了一个实施例，在该实施例中，通孔50的突出件具有延伸穿过第一图案化层44的正锥形，从而突出件的宽度随着突出件远离通孔50的中心体向外延伸而增加。在一个实施例中，突出件的侧壁的正锥角(α)为从约5度至约85度。在光刻工艺期间，可以通过从约500mJ/cm2至约1000mJ/cm2的剂量，和从约5μm至约10μm的聚焦深度来调整正锥角(α)。
图17C示出了一个实施例，在该实施例中，通孔50的突出件具有延伸穿过第一图案化层44的负锥形，从而突出件的宽度随着突出件远离通孔50的中心体向外延伸而减小。在一个实施例中，突出件的侧壁的负锥角(β)为从约5度至约85度。在光刻工艺期间，可以通过从约100mJ/cm2至约500mJ/cm2的剂量，和从约15μm至约20μm的聚焦深度来调整负锥角(β)。可以调整通孔50的突出件的锥形以减小在特定设计中的应力。
诸如在本文中公开的那些实施例在不使用可能造成更多损坏或提供更少控制的工艺的情况下允许与通孔50接触。例如，诸如本文中的那些实施例利用在第一图案化层44和晶种层结构中的开口以形成至通孔50的凹槽，这依靠良好控制的选择性蚀刻工艺，而不是穿过介电层的激光钻孔开口以提供至通孔的电接触。诸如激光钻孔的技术对轮廓和临界尺寸造成损坏并且提供较小的控制。
图18至图31示出了根据一些实施例的制造封装件结构的各个中间阶段的截面图。图18至图31中示出的实施例可以利用如上参照图1至图16以及图17A至图17C所讨论的一些类似的结构和工艺，其中，相同的参考标号代表使用类似工艺由类似的材料形成的相同的元件。但是，可以利用其他材料和工艺。现在参考图18，牺牲层94形成在释放层42和载体衬底40上，其中，一些实施例可以利用如上参考图1和图2所讨论的载体衬底40和释放层42。如将在下面讨论，结构将形成在载体衬底40上，并且然后载体衬底40将随后被去除。在随后去除载体衬底40和释放层42期间(见，例如，图29)，牺牲层94提供保护层以保护随后形成的聚合物层44(见图19)。在去除工艺之后，聚合物层44保持平坦。
在一些实施例中，牺牲层94可以是聚合物层或金属层。例如，聚合物层可以是六甲基二硅氮烷(HMDS)层等，并且例如金属层可以是钛(Ti)层等。可以通过旋涂沉积聚合物层，并且可以通过化学汽相沉积(CVD)、物理汽相沉积(PVD)、溅射等形成金属层。在一些实施例中，HMDS层的厚度在从约0.01μm至约5μm的范围内。在另一实施例中，牺牲层94是通过，例如，溅射、CVD、PVD等形成的Ti层。Ti层的厚度在从约0.01μm至约5μm的范围内。
图19至图30示出了分别类似于图3至图14中示出的那些的随后的各个中间步骤的截面图。可以使用类似的工艺和材料并且将不在此重复，其中，相同的参考标号表示相同的元件。
现在参考图31，根据一些实施例，示出了牺牲层94(见图30)和晶种层46的一层或多层的去除。可以通过，例如，使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除牺牲层94和晶种层46的一层或多层以暴露出至少部分的第一图案化层44和通孔50。如上参照图17A至图17C所讨论的，去除牺牲层94和去除晶种层46的一层或多层以暴露出通孔50并且产生凹槽79。通孔50可以进一步电连接至另一个半导体结构。例如，可以通过等离子体灰化、在丙酮、异丙醇等中冲洗去除HMDS层。可以通过湿蚀刻或干蚀刻去除Ti层。其后，可以实施随后的处理。例如，诸如上参照图15至图16所讨论的处理以形成导电连接件78(见图15)并且使用导电连接件78和粘合材料82连接衬底80(见图16)。可以使用如图15至图16中的类似的工艺和材料，并且在此将不再重复。
图32至图34示出了根据一些实施例的制造封装件结构的各个中间阶段的截面图。首先参考图32，根据一些实施例，图32示出了另一个结构。图32示出的实施例假设已经实施了那些类似于用于形成图31中示出的结构的工艺，其中，相同的参考标号指的是相同的元件。为了简洁，那些工艺将不再此重复。但是，可以利用其他材料和工艺。
如图32中所示，凹进第一图案化层44从而使得通孔50的部分从第一图案化层44突出。在一些实施例中，可以通过使用例如干蚀刻、湿蚀刻、它们的组合等的蚀刻凹进第一图案化层44。干蚀刻工艺可以包括诸如使用氩气、氧气、它们的组合等的灰化工艺，并且可以使用的蚀刻时间从约30秒至50秒，诸如40秒，从而精确地控制第一图案化层44的厚度。如图32所示，减薄第一图案化层44，从而暴露出通孔50的侧壁。在一些实施例中，通孔50的突出部分具有沿着通孔50的侧壁的第三高度h3，第三高度h3可以为约1μm至约5μm，诸如μm，第三高度h3成反比地取决于第一图案化44的厚度。通孔50的突出部分可以提供更大的工艺窗口以用于晶圆上封装(POW)工艺，并且它可以减小在通孔50和焊球75之间界面处的焊料润湿性问题。在另一实施例中，如上在图17A至图17C中所讨论的，取决于开口47的侧壁轮廓，突出部分可以包括正形、负形和垂直形。通过在光刻工艺期间调整剂量和聚焦深度，可以控制开口的侧壁的角度。
图33至图34示出了分别类似于图15至图16中示出的那些的将第二封装件附接至通孔50的步骤的截面图。可以使用类似的工艺和材料并且将不在此重复，其中，相同的参考标号表示相同的元件。
在一些实施例中，提供了一种制造半导体器件的方法。该方法包括：在载体衬底上方形成第一层和在第一层中形成第一开口。在第一层上方形成通孔，从而使得通孔延伸至第一开口内。在第一层上方放置集成电路，并且在第一层上方形成模塑料，模塑料沿着集成电路和通孔的侧壁延伸。可以在集成电路和通孔上形成再分布层。去除载体衬底。
在另一实施例中，提供了一种制造半导体器件的方法。该方法包括：在载体衬底上形成第一层和在第一层中形成第一开口。沿着第一开口的侧壁和底部形成一个或多个晶种层，在晶种层上方形成通孔，从而通孔延伸至开口内。在第一层上放置集成电路，并且在第一层上形成模塑料，模塑料被插入在集成电路和通孔之间。可以去除载体衬底。
在又另一实施例中，提供了一种半导体器件。半导体器件包括第一层和集成电路，第一层具有开口，集成电路位于第一层上。将密封剂设置在邻近集成电路的第一层上，密封剂具有在其中延伸的通孔，该通孔延伸至开口内。通孔的延伸穿过密封剂的部分的宽度大于通孔的延伸至开口内的部分的宽度。
在一些实施例中，提供了一种制造半导体器件的方法。该方法包括：在载体衬底上方形成第一层和在第一层中形成第一开口。沿着第一层的顶面、第一开口的侧壁和第一开口的底部形成一个或多个晶种层。在一个或多个晶种层上形成通孔，从而使得通孔延伸至第一开口内。将半导体管芯放置在第一层上方，并且邻近通孔和半导体管芯的侧壁形成模塑料。去除载体衬底。去除一个或多个晶种层的至少部分以暴露出通孔的顶部并且去除第一层的部分以暴露出通孔的侧壁的部分。
在另一实施例中，提供了一种制造半导体器件的方法。该方法包括在载体衬底上形成第一介电层。在第一介电层上方形成一个或多个晶种层。在一个或多个晶种层上方形成通孔，一个或多个晶种层和通孔延伸穿过第一介电层。将集成电路管芯放置在第一介电层上方，并且在集成电路管芯和通孔之间形成密封剂。去除载体衬底，并且然后去除一个或多个晶种层的部分和第一介电层的部分以暴露出通孔的侧壁的部分。
在又另一实施例中，提供了一种半导体器件。半导体器件包括第一介电层和位于第一介电层上的集成电路。将集成电路放置在第一介电层上。放置通孔以围绕集成电路管芯并且在第一介电层之上。位于第一介电层上的密封剂插入在集成电路和通孔之间。通孔的部分从第一介电层突出并且具有暴露侧壁。
根据本发明的一些实施例，提供了一种制造半导体器件的方法，所述方法包括：在载体衬底上形成第一层；在所述第一层中形成第一开口；沿着所述第一层的顶面、所述第一开口的侧壁和所述第一开口的底部形成一个或多个晶种层；在所述一个或多个晶种层上形成通孔，所述通孔延伸至所述第一开口内；在所述第一层上方放置半导体管芯；邻近所述通孔和所述半导体管芯的侧壁形成模塑料；去除所述载体衬底；去除所述一个或多个晶种层的至少部分以暴露出所述通孔的顶部；以及去除所述第一层的部分以暴露出所述通孔的侧壁的部分。
在上述方法中，所述第一开口具有正锥形。
在上述方法中，所述第一开口具有负锥形。
在上述方法中，还包括：在所述半导体管芯和所述通孔上形成再分布层。
在上述方法中，所述通孔的侧壁的部分的高度为1μm至5μm。
在上述方法中，还包括：在所述载体衬底上形成牺牲层，并且其中，所述第一层形成在所述牺牲层上。
在上述方法中，还包括：在去除所述一个或多个晶种层的至少部分之前去除所述牺牲层。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，所述方法包括：在衬底上方形成第一介电层；在所述第一介电层上方形成一个或多个晶种层；在所述一个或多个晶种层上方形成通孔，所述一个或多个晶种层和所述通孔延伸穿过所述第一介电层；在所述第一介电层上方放置集成电路管芯；在所述集成电路管芯和所述通孔之间形成密封剂；去除所述衬底；以及去除所述一个或多个晶种层的部分和所述第一介电层的部分以暴露出所述通孔的侧壁的部分。
在上述方法中，还包括：在所述通孔和所述集成电路管芯上方形成再分布层。
在上述方法中，所述通孔包括具有第一宽度的第一主体部分和具有第二宽度的第二主体部分，所述第一主体部分延伸穿过所述密封剂和所述第二主体部分延伸穿过所述第一介电层，所述第二宽度不同于所述第一宽度。
在上述方法中，所述第二宽度小于所述第一宽度。
在上述方法中，所述第二主体部分是锥形的。
在上述方法中，去除所述一个或多个晶种层的部分和所述第一介电层的部分形成具有1μm至5μm的高度的所述通孔的突出部分。
在上述方法中，还包括：在形成所述第一介电层之前形成牺牲层。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：第一介电层；集成电路，位于所述第一介电层上；通孔，围绕所述集成电路；以及密封剂，位于所述第一介电层上并且插入在所述集成电路和所述通孔之间；其中，所述通孔的部分从所述第一介电层突出。
在上述半导体器件中，所述通孔的暴露侧壁是锥形的。
在上述半导体器件中，还包括：再分布层，位于所述集成电路和所述通孔上
在上述半导体器件中，还包括：焊球，位于所述再分布层上。
在上述半导体器件中，还包括：一个或多个晶种层，位于所述通孔和所述第一介电层之间。
在上述半导体器件中，所述通孔的部分突出1μm至5μm的距离。
以上论述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
在载体衬底上形成第一层；
在所述第一层中形成第一开口；
沿着所述第一层的顶面、所述第一开口的侧壁和所述第一开口的底部形成一个或多个晶种层；
在所述一个或多个晶种层上形成通孔，所述通孔延伸至所述第一开口内；
在所述第一层上方放置半导体管芯；
邻近所述通孔和所述半导体管芯的侧壁形成模塑料；
去除所述载体衬底；
去除所述一个或多个晶种层的至少部分以暴露出所述通孔的顶部；以及
去除所述第一层的部分以暴露出所述通孔的侧壁的部分。
2.根据权利要求1所述的方法，其中，所述第一开口具有正锥形。
3.根据权利要求1所述的方法，其中，所述第一开口具有负锥形。
4.根据权利要求1所述的方法，还包括：在所述半导体管芯和所述通孔上形成再分布层。
5.根据权利要求1所述的方法，其中，所述通孔的侧壁的部分的高度为1μm至5μm。
6.根据权利要求1所述的方法，还包括：在所述载体衬底上形成牺牲层，并且其中，所述第一层形成在所述牺牲层上。
7.根据权利要求6所述的方法，还包括：在去除所述一个或多个晶种层的至少部分之前去除所述牺牲层。
8.一种制造半导体器件的方法，所述方法包括：
在衬底上方形成第一介电层；
在所述第一介电层上方形成一个或多个晶种层；
在所述一个或多个晶种层上方形成通孔，所述一个或多个晶种层和所述通孔延伸穿过所述第一介电层；
在所述第一介电层上方放置集成电路管芯；
在所述集成电路管芯和所述通孔之间形成密封剂；
去除所述衬底；以及
去除所述一个或多个晶种层的部分和所述第一介电层的部分以暴露出所述通孔的侧壁的部分。
9.根据权利要求8所述的方法，还包括：在所述通孔和所述集成电路管芯上方形成再分布层。
10.一种半导体器件，包括：
第一介电层；
集成电路，位于所述第一介电层上；
通孔，围绕所述集成电路；以及
密封剂，位于所述第一介电层上并且插入在所述集成电路和所述通孔之间；
其中，所述通孔的部分从所述第一介电层突出。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511426A (zh) * 2017-02-24 2018-09-07 台湾积体电路制造股份有限公司 封装
CN109216315A (zh) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 半导体封装及其制造方法
CN110660753A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 半导体封装件和方法
US10586763B2 (en) 2017-11-15 2020-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11205615B2 (en) 2017-11-15 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9443797B2 (en) * 2012-09-14 2016-09-13 STATS ChipPAC Pte. Ltd. Semiconductor device having wire studs as vertical interconnect in FO-WLP
US10177115B2 (en) * 2014-09-05 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US9837359B1 (en) * 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
CN108022897A (zh) * 2016-11-01 2018-05-11 财团法人工业技术研究院 封装结构及其制作方法
TW202404049A (zh) 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
DE102017127920A1 (de) 2017-01-26 2018-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Erhöhte Durchkontaktierung für Anschlüsse auf unterschiedlichen Ebenen
US10157824B2 (en) 2017-05-05 2018-12-18 Qualcomm Incorporated Integrated circuit (IC) package and package substrate comprising stacked vias
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
CN107507816A (zh) * 2017-08-08 2017-12-22 中国电子科技集团公司第五十八研究所 扇出型晶圆级多层布线封装结构
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US11004779B2 (en) * 2018-02-09 2021-05-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10622302B2 (en) 2018-02-14 2020-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Via for semiconductor device connection and methods of forming the same
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10700008B2 (en) * 2018-05-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having redistribution layer structures
DE102018126130B4 (de) 2018-06-08 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und -verfahren
US11158775B2 (en) 2018-06-08 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10992100B2 (en) 2018-07-06 2021-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR102530754B1 (ko) * 2018-08-24 2023-05-10 삼성전자주식회사 재배선층을 갖는 반도체 패키지 제조 방법
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10867929B2 (en) * 2018-12-05 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods of forming the same
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US11088079B2 (en) * 2019-06-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having line connected via portions
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
KR102609302B1 (ko) 2019-08-14 2023-12-01 삼성전자주식회사 반도체 패키지의 제조 방법
US11569159B2 (en) * 2019-08-30 2023-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of chip package with through vias
KR20210026546A (ko) * 2019-08-30 2021-03-10 삼성전자주식회사 반도체 패키지 제조 방법
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11450641B2 (en) * 2019-09-27 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structure
KR20210083830A (ko) * 2019-12-27 2021-07-07 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
KR20210099244A (ko) * 2020-02-03 2021-08-12 삼성전자주식회사 반도체 장치 및 그의 제조 방법
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100263923A1 (en) * 2009-04-16 2010-10-21 Shinko Electric Industries Co., Ltd. Wiring substrate having columnar protruding part
CN102246299A (zh) * 2008-10-15 2011-11-16 Aac微技术有限公司 用于制作通路互连的方法
US20120007234A1 (en) * 2010-07-12 2012-01-12 Siliconware Precision Industries Co., Ltd. Semiconductor package without chip carrier and fabrication method thereof
US8176628B1 (en) * 2008-12-23 2012-05-15 Amkor Technology, Inc. Protruding post substrate package structure and method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173371A (ja) * 2005-12-20 2007-07-05 Shinko Electric Ind Co Ltd フレキシブル配線基板の製造方法及び電子部品実装構造体の製造方法
JP5203108B2 (ja) * 2008-09-12 2013-06-05 新光電気工業株式会社 配線基板及びその製造方法
US8399987B2 (en) * 2009-12-04 2013-03-19 Samsung Electronics Co., Ltd. Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers
US8791009B2 (en) * 2011-06-07 2014-07-29 International Business Machines Corporation Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
JP6081693B2 (ja) * 2011-09-12 2017-02-15 新光電気工業株式会社 配線基板及び配線基板の製造方法
US9059107B2 (en) 2012-09-12 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged devices
KR20140063271A (ko) * 2012-11-16 2014-05-27 삼성전자주식회사 관통 전극을 갖는 반도체 장치 및 그 제조 방법
US9378982B2 (en) * 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102246299A (zh) * 2008-10-15 2011-11-16 Aac微技术有限公司 用于制作通路互连的方法
US8176628B1 (en) * 2008-12-23 2012-05-15 Amkor Technology, Inc. Protruding post substrate package structure and method
US20100263923A1 (en) * 2009-04-16 2010-10-21 Shinko Electric Industries Co., Ltd. Wiring substrate having columnar protruding part
US20120007234A1 (en) * 2010-07-12 2012-01-12 Siliconware Precision Industries Co., Ltd. Semiconductor package without chip carrier and fabrication method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511426A (zh) * 2017-02-24 2018-09-07 台湾积体电路制造股份有限公司 封装
CN108511426B (zh) * 2017-02-24 2022-11-11 台湾积体电路制造股份有限公司 封装、半导体封装及封装结构的形成方法
CN109216315A (zh) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 半导体封装及其制造方法
CN109216315B (zh) * 2017-06-30 2022-03-15 台湾积体电路制造股份有限公司 半导体封装及其制造方法
US11355474B2 (en) 2017-06-30 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
US10586763B2 (en) 2017-11-15 2020-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
TWI688074B (zh) * 2017-11-15 2020-03-11 台灣積體電路製造股份有限公司 半導體元件及其製造方法
US11205615B2 (en) 2017-11-15 2021-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN110660753A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 半导体封装件和方法
US11049805B2 (en) 2018-06-29 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11508656B2 (en) 2018-06-29 2022-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method

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