KR102530754B1 - 재배선층을 갖는 반도체 패키지 제조 방법 - Google Patents

재배선층을 갖는 반도체 패키지 제조 방법 Download PDF

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KR102530754B1
KR102530754B1 KR1020180099284A KR20180099284A KR102530754B1 KR 102530754 B1 KR102530754 B1 KR 102530754B1 KR 1020180099284 A KR1020180099284 A KR 1020180099284A KR 20180099284 A KR20180099284 A KR 20180099284A KR 102530754 B1 KR102530754 B1 KR 102530754B1
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South Korea
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conductive pad
forming
silicon substrate
semiconductor chip
layer
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KR1020180099284A
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KR20200022982A (ko
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김일환
강운병
이충선
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삼성전자주식회사
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Priority to KR1020180099284A priority Critical patent/KR102530754B1/ko
Priority to US16/293,697 priority patent/US11315802B2/en
Priority to CN201910345056.3A priority patent/CN110858549A/zh
Publication of KR20200022982A publication Critical patent/KR20200022982A/ko
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Abstract

반도체 패키지 제조 방법은 실리콘 기판의 일면에 복수의 트렌치를 형성하는 단계, 상기 복수의 트렌치의 내부에 도전성 패드를 형성하는 단계, 상기 실리콘 기판의 일면 상에 재배선층을 형성하는 단계, 상기 재배선층의 제1 면 상에 외부 연결 부재를 형성하는 단계, 상기 도전성 패드가 노출되도록 상기 실리콘 기판을 제거하는 단계, 상기 도전성 패드에 연결되는 반도체 칩을 실장하는 단계, 및 상기 반도체 칩의 적어도 일면을 감싸는 봉지재를 형성하는 단계를 포함할 수 있다.

Description

재배선층을 갖는 반도체 패키지 제조 방법{Method for manufacturing semiconductor package having redistribution layer}
본 개시의 기술적 사상은 재배선층을 갖는 반도체 패키지의 제조 방법에 관한 것이다.
전자기기의 소형화 및 경량화 요구에 따라 반도체 패키지 기술에서는 관통 실리콘 전극(Through Silicon Via; TSV) 또는 재배선층 기술이 시도되고 있다. 관통 실리콘 전극 및 재배선층의 제조에는 캐리어를 부착하고 제거하는 공정이 추가되므로 반도체 패키지 제조 공정의 단순화가 필요하다.
본 개시의 기술적 사상의 실시예들에 따른 과제는, 제조 공정이 단순화된 반도체 패키지 제조 방법을 제공하는 데 있다.
본 개시의 실시예들에 따른 반도체 패키지 제조 방법은 실리콘 기판의 일면에 복수의 트렌치를 형성하는 단계, 상기 복수의 트렌치의 내부에 도전성 패드를 형성하는 단계, 상기 실리콘 기판의 일면 상에 재배선층을 형성하는 단계, 상기 재배선층의 제1 면 상에 외부 연결 부재를 형성하는 단계, 상기 도전성 패드가 노출되도록 상기 실리콘 기판을 제거하는 단계, 상기 도전성 패드에 연결되는 반도체 칩을 실장하는 단계, 및 상기 반도체 칩의 적어도 일면을 감싸는 봉지재를 형성하는 단계를 포함할 수 있다.
본 개시의 실시예들에 따른 반도체 패키지 제조 방법은 실리콘 기판의 일면에 복수의 제1 트렌치 및 상기 제1 트렌치보다 깊게 형성되는 복수의 제2 트렌치를 형성하는 단계, 상기 복수의 제1 트렌치 내부에 제1 도전성 패드를 형성하고, 상기 복수의 제2 트렌치의 내부에 제2 도전성 패드를 형성하는 단계, 상기 실리콘 기판의 일면 상에 재배선층을 형성하는 단계, 상기 재배선층의 제1 면 상에 외부 연결 부재를 형성하는 단계, 상기 제1 도전성 패드 및 제2 도전성 패드가 노출되도록 실리콘 기판을 제거하는 단계, 상기 제1 도전성 패드에 연결되는 제1 반도체 칩을 실장하는 단계, 및 상기 제1 반도체 칩의 적어도 일면을 감싸는 봉지재를 형성하는 단계를 포함할 수 있다.
본 개시의 실시예들에 따른 반도체 패키지 제조 방법은 실리콘 기판의 일면에 복수의 트렌치를 형성하는 단계, 상기 복수의 트렌치의 내부에 도전성 패드를 형성하는 단계, 상기 실리콘 기판의 일면 상에 재배선층을 형성하는 단계, 상기 재배선층의 제1 면 상에 외부 연결 부재를 형성하는 단계, 상기 도전성 패드가 노출되도록 실리콘 기판을 제거하는 단계, 상기 도전성 패드에 연결되는 반도체 칩을 실장하는 단계, 및 상기 반도체 칩의 적어도 일면을 감싸는 봉지재를 형성하는 단계를 포함할 수 있다. 상기 복수의 트렌치의 측면은 스캘럽 형상을 가질 수 있다.
본 개시의 실시예들에 따르면, 실리콘 기판에 도전성 패드를 형성하고, 도전성 패드 상에 재배선층 및 외부 연결 부재를 순차적으로 형성함으로써, 제조 공정을 단순화 할 수 있다.
도 1은 본 개시의 실시예에 따른 반도체 패키지의 제조 방법을 나타내는 순서도이다.
도 2 내지 도 11은 본 개시의 실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위해 공정 순서에 따라 도시된 단면도들이다.
도 12는 본 개시의 다른 실시예에 따른 반도체 패키지의 단면도이다.
도 13 및 도 14는 본 개시의 다른 실시예에 따른 도전성 패드의 단면도이다.
도 15a 내지 도 15b는 본 개시의 다른 실시예에 따른 반도체 패키지의 일부 확대도이다.
도 16은 본 개시의 다른 실시예에 따른 트렌치를 설명하기 위한 단면도이다.
도 17은 본 개시의 다른 실시예에 따른 반도체 패키지의 단면도이다.
도 18은 본 개시의 다른 실시예에 따른 트렌치를 설명하기 위한 단면도이다.
도 19는 본 개시의 다른 실시예에 따른 반도체 패키지의 단면도이다.
도 20은 본 개시의 다른 실시예에 따른 트렌치를 설명하기 위한 단면도이다.
도 21은 본 개시의 다른 실시예에 따른 도전성 패드를 설명하기 위한 단면도이다.
도 22는 본 개시의 다른 실시예에 따른 반도체 패키지의 단면도이다.
도 23은 본 개시의 다른 실시예에 따른 도전성 패드 및 인터커넥터를 설명하기 위한 단면도이다.
도 24 및 도 25는 본 개시의 다른 실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위한 단면도이다.
도 1은 본 개시의 실시예에 따른 반도체 패키지의 제조 방법을 나타내는 순서도이다.
도 1을 참조하면, 반도체 패키지의 제조 방법은 실리콘 기판을 준비하는 단계(S10), 실리콘 기판에 복수의 트렌치를 형성하는 단계(S11), 트렌치의 내부에 도전성 패드를 형성하는 단계(S12), 실리콘 기판의 일면 상에 재배선층을 형성하는 단계(S13), 재배선층의 제1 면에 외부 연결 부재를 형성하는 단계(S14), 외부 연결 부재 상에 캐리어를 부착하는 단계(S15), 도전성 패드가 노출되도록 실리콘 기판을 제거하는 단계(S16), 도전성 패드에 연결되는 반도체 칩을 실장하는 단계(S17), 반도체 칩의 적어도 일면을 감싸는 봉지재를 형성하는 단계(S18) 및 캐리어를 제거하는 단계(S19)를 포함할 수 있다.
이하에서는, 상기와 같이 구성되는 본 개시의 실시예에 따른 반도체 패키지의 제조 방법을 도 2 내지 도 12를 참조하여 설명한다.
도 2를 참조하면, 실리콘 기판(110)을 준비하는 단계(S10) 및 실리콘 기판(110)에 복수의 트렌치를 형성하는 단계(S11)가 이루어진다. 기판(110)은 제1 면(110a)과 상기 제1 면(110a)의 반대면인 제2 면(110b)을 가질 수 있다. 트렌치(112)는 기판(110)의 제1 면(110a)에 형성될 수 있다. 상기 트렌치(112)는 복수 형성될 수 있으며, 소정의 간격으로 이격되어 배치될 수 있다. 예를 들어, 복수의 트렌치(112)는 0.5 ~ 100μm의 간격으로 이격될 수 있다.
복수의 트렌치(112)는 기판(110)을 식각하여 형성될 수 있으며, 상기 식각 공정은 리소그래피, 레이저 드릴링, 반응성 이온 식각(reactive ion etching; RIE) 또는 습식 식각을 포함할 수 있다. 복수의 트렌치(112)는 기판(110)의 제1 면(110a)에서 수직 방향으로 연장되어 형성될 수 있으며, 깊이(D)는 50 ~ 300nm일 수 있다. 일 실시예에서, 복수의 트렌치(112)는 동일한 깊이를 갖도록 형성될 수 있으며, 다른 실시예에서 복수의 트렌치(112) 중 일부는 다른 깊이를 가질 수 있다. 또한, 일 실시예에서, 복수의 트렌치(112)는 동일한 폭을 갖도록 형성될 수 있으며, 다른 실시예에서 복수의 트렌치(112) 중 일부는 다른 폭을 가질 수 있다.
도 3을 참조하면, 트렌치(112) 내부에 도전성 패드(114)가 형성되는 단계(S12)가 이루어진다. 도전성 패드(114)와 트렌치(112)의 내벽 사이에는 제1 배리어층(120)이 및 제1 시드층(122)이 더 형성될 수 있다. 제1 배리어층(120)은 복수의 트렌치(112)의 내벽에 배치될 수 있다. 제1 시드층(122)은 각 제1 배리어층(120) 상에 배치될 수 있으며, 도전성 패드(114)는 제1 시드층(122) 상에 배치될 수 있다.
제1 배리어층(120)은 Ta, Ti, W, Ru, V, Co 및 Nb 중에서 선택된 적어도 하나를 포함할 수 있다. 예를 들어, 제1 배리어층(120)은 탄탈럼 질화물, 탄탈럼 규화물, 탄탈럼 탄화물, 티타늄 질화물, 티타늄 규화물, 티타늄 탄화물, 텅스텐 질화물, 텅스텐 규화물, 텅스텐 탄화물, 루테늄 및 루테늄 산화물, 바나듐 산화물, 코발트 산화물 또는 니오븀 산화물 등으로 구성될 수 있다. 일 실시예에서, 상기 제1 배리어층(120)은 복수의 층으로 구성될 수 있다. 제1 시드층(122)은 Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au 및 Ag 중에서 선택된 적어도 하나를 포함할 수 있다. 상기 제1 배리어층(120) 및 제1 시드층(122)은 물리 기상 증착(Physical Vapor Deposition; PVD) 공정, 화학 기상 증착(Chemical Vapor Deposition; CVD) 공정 또는 원자층 증착(Atomic Layer Deposition; ALD) 공정 등에 의해 기판(110)의 제1 면(110a)에 증착될 수 있다.
도전성 패드(114)는 상기 제1 시드층(122) 상에 도전성 물질을 도금하여 형성될 수 있다. 도금 공정은, 예를 들어, 전기 화학 도금(electro-chemical plating; ECP) 공정 또는 다른 타입의 도금 공정을 포함할 수 있다. 도전성 패드(114)는 Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au 및 Ag와 같은 금속을 포함할 수 있으며, 일 실시예에서 도전성 패드(114)는 구리를 포함할 수 있다. 도전성 패드(114)는 실리콘 기판(110)을 식각하여 형성된 트렌치(112)의 내부에 배치되므로, 도전성 패드(114)들은 미세한 간격으로 배치될 수 있다.
상기 제1 배리어층(120), 제1 시드층(122) 및 도전성 패드(114)는 기판(110)의 제1 면(110a) 상에도 형성될 수 있다. 트렌치(112) 내부에 도전성 패드(114)를 형성하는 단계(S11) 이후에, 제1 배리어층(120), 제1 시드층(122) 및 도전성 패드(114)는 화학 기계적 연마(chemical mechanical polishing; CMP) 공정에 의해 평탄화 될 수 있다. 상기 CMP 공정에 의해 도전성 패드(114), 제1 배리어층(120) 및 제1 시드층(122)의 상단은 기판(110)의 제1 면(110a)과 동일한 레벨에 위치할 수 있다.
도 4를 참조하면, 도전성 패드(114)의 제1 면(114a) 상에 제2 배리어층(130) 및 제2 시드층(132)이 배치될 수 있다. 여기에서, 도전성 패드(114)의 제1 면(114a)은 도 4에 도시된 도전성 패드(114)의 상면으로 제2 배리어층(130)과 접하는 면을 의미할 수 있다. 도전성 패드(114)의 제2 면(114b)은 제1 면(114a)의 반대 방향에 위치하는 도전성 패드(114)의 하면을 의미할 수 있다.
제2 배리어층(130)은 Ta, Ti, W, Ru, V, Co 및 Nb 중에서 선택된 적어도 하나를 포함할 수 있다. 일 실시예에서, 상기 제2 배리어층(130)은 복수의 층으로 구성될 수 있다. 제2 시드층(132)은 상기 제2 배리어층(130) 상에 배치될 수 있다. 제2 시드층(132)은 Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au 및 Ag 중에서 선택된 적어도 하나를 포함할 수 있다. 상기 제2 배리어층(130) 및 제2 시드층(132)은 물리 기상 증착 공정, 화학 기상 증착 공정 또는 원자층 증착 공정 등에 의해 기판(110)의 제1 면(110a)에 증착될 수 있다.
도 5를 참조하면, 실리콘 기판(110)의 제1 면(110a) 상에 재배선층(140)을 형성하는 단계(S13)가 이루어진다. 예를 들어, 도전성 패드(114) 상에 위치한 제2 시드층(132) 상에 재배선층이 형성될 수 있다. 재배선층(140)은 제1 면(140a) 및 상기 제1 면(140a)의 반대되는 제2 면(140b)을 가질 수 있다. 재배선층(140)의 제1 면(140a)은 도 5에 도시된 재배선층(140)의 상면을 의미할 수 있다. 재배선층(140)의 제2 면(140b)은 도 5에 도시된 재배선층(140)의 하면으로, 제2 시드층(132)과 접하는 면을 의미할 수 있다.
재배선층(140)은 내부에 배선 패턴(142), 비아(144) 및 절연층(146)을 포함할 수 있다. 재배선층(140)의 형성은 복수의 층으로 구성되는 배선 패턴(142) 및 절연층(146)이 적층되어 이루어질 수 있다. 제2 시드층(132) 상에 절연층(146)이 형성된 후, 절연층(146)을 일부 식각하여 생긴 개구부에 배선 패턴(142) 및 비아(144)를 형성한다. 상기 배선 패턴(142) 및 비아(144)를 덮는 절연층(146)이 다시 형성될 수 있다. 절연층(146)의 상면에 형성된 개구부(148)에 의해 배선 패턴(142)이 노출될 수 있다. 도시되지는 않았으나, 노출된 배선 패턴(142)의 상부에는 언더범프메탈이 형성될 수 있다.
배선 패턴(142)은 재배선층(140)의 내부에 여러 층에 배치될 수 있으며, 신호 전달 경로를 제공할 수 있다. 비아(144)는 서로 다른 층에 배치된 배선 패턴(142)을 전기적으로 연결시킬 수 있다. 비아(144)는 도전성 물질로 이루어질 수 있으며, 도전성 물질로 완전히 충전될 수 있다. 비아(144)는 비아 홀의 벽면을 따라 배치될 수 있으며, 또한 테이퍼 형상뿐만 아니라, 원통형상이 적용될 수 있다. 비아(144)는 재배선층(140)의 배선 패턴(142)과 일체화되도록 배치될 수 있다. 상기 배선 패턴(142) 및 비아(144)는 반도체 패키지 내에서 다양한 신호 경로를 제공할 수 있다. 절연층(146)은 배선 패턴(142) 및 비아(144)를 외부로부터 전기적으로 절연시킬 수 있다.
배선 패턴(142) 및 비아(144)는 구리(Cu), 알루미늄(Al), 은(Ag), 주석(Sn), 금(Au), 니켈(Ni), 납(Pb), 티타늄(Ti), 또는 이들의 합금 등의 도전성 물질을 포함할 수 있다. 절연층(146)은 SiO2, Si3N4, SiON, Ta2O5, HfO2, PI(PolyImide), PBO(Poly Benz Oxazole), BCB(Benzi Cyclo Butene), BT(BismaleimideTriazine) 및 감광성 수지 중 선택되는 어느 하나를 포함할 수 있다. 도전성 패드(114), 제2 시드층(132) 및 배선 패턴(142)은 동일한 금속을 포함할 수 있으며, 서로 전기적으로 연결될 수 있다. 예를 들어, 도전성 패드(114), 제2 시드층(132) 및 배선 패턴(142)은 구리를 포함할 수 있다.
도 6을 참조하면, 재배선층(140)의 제1 면(140a)에 외부 연결 부재(150)를 형성하는 단계(S14)가 이루어진다. 외부 연결 부재(150)는 재배선층(140)의 배선 패턴(142)과 전기적으로 연결될 수 있다. 예를 들어, 외부 연결 부재(150)는 개구부(148)에 의해 노출된 배선 패턴(142)과 전기적으로 연결될 수 있으며, 상기 배선 패턴(142) 상에 배치된 언더범프메탈 상에 위치할 수 있다. 외부 연결 부재(150)를 통하여 재배선층(140)은 외부와 전기적으로 연결될 수 있다. 외부 연결 부재(150)는 솔더 볼 또는 C4 범프일 수 있다.
도 7을 참조하면, 외부 연결 부재(150) 상에 캐리어(160)를 부착하는 단계(S15)가 이루어진다. 캐리어(160)는 접착제(162)에 의해 외부 연결 부재(150) 상에 형성될 수 있다. 캐리어(160)는 반도체 패키지 제조 단계에서 재배선층(140) 및 외부 연결 부재(150)를 외부의 충격 또는 휨(warpage)으로부터 보호할 수 있다. 접착제(162)는 캐리어(160)를 외부 연결 부재(150)에 고정시킬 수 있다. 접착제(162)의 두께는 외부 연결 부재(150)의 직경보다 크게 형성될 수 있다.
상기 캐리어(160)는 실리콘, 게르마늄, 실리콘-게르마늄, 갈륨-비소(GaAs), 유리, 플라스틱, 세라믹 등을 포함할 수 있으나, 이에 제한되지 않는다. 상기 접착제(162)는 에폭시 접착제, 접착 필름 또는 접착 테이프를 포함할 수 있으나, 이에 제한되지 않는다.
도 8을 참조하면, 도전성 패드(114)가 노출되도록 실리콘 기판(110)을 제거하는 단계(S16)가 이루어진다. 실리콘 기판(110)을 제거하기 위해, 기판(110)의 제2 면(110b)이 상방을 향하도록 플리핑(flipping)이 이루어질 수 있다. 기판(110)은 제2 면(110b)에서부터 백그라인딩에 의해 일부 제거될 수 있다. 예를 들어, 백그라인딩에 의해 식각된 기판(110)의 상단은 도전성 패드(114) 또는 제1 배리어층(120)의 상단과 동일한 레벨에 위치할 수 있다. 도전성 패드(114)는 백그라인딩 공정에 의해 제거되지 않고 남을 수 있다. 도전성 패드(114)의 제2 면(114b) 상에 배치된 제1 배리어층(120) 및 제1 시드층(122)은 제거되지 않을 수 있다. 일 실시예에서, 제1 배리어층(120) 및 제1 시드층(122)은 일부 제거될 수 있다. 백그라인딩된 기판(110) 중 일부는 제거되지 않고 도전성 패드(114) 사이에 남을 수 있다. 도전성 패드(114)들 사이에 남아 있는 기판(110)은 건식 식각에 의해 제거될 수 있다. 실리콘 기판(110)을 제거하는 단계(S16)에서 제1 배리어층(120) 및 제1 시드층(122)은 도전성 패드(114)가 제거되지 않도록 보호할 수 있다. 제2 배리어층(130) 및 제2 시드층(132)은 재배선층(140)이 제거되지 않도록 보호할 수 있다.
도 9를 참조하면, 도전성 패드(114)의 제2 면(114b) 및 측면을 덮는 제1 배리어층(120) 및 제1 시드층(122)이 제거될 수 있다. 상기 제1 배리어층(120) 및 제1 시드층(122)이 제거됨으로써 반도체 칩이 실장될 수 있도록 도전성 패드(114)가 노출될 수 있다. 제2 배리어층(130) 또는 제2 시드층(132)을 통하여 도전성 패드(114)들이 서로 전기적으로 연결되는 것을 방지하기 위해, 상기 제2 배리어층(130) 및 제2 시드층(132)은 제거될 수 있다. 재배선층(140)의 제2 면(140b) 상에 배치된 제2 배리어층(130) 및 제2 시드층(132)의 일부는 제거되지 않을 수 있다. 예를 들어, 도전성 패드(114)의 제1 면(114a)과 재배선층(140)의 제2 면(140b) 사이에 제2 배리어층(131) 및 제2 시드층(133)이 남을 수 있다. 상기 제2 배리어층(131)은 제2 시드층(133)상에 위치할 수 있다.
도 10을 참조하면, 반도체 칩(170)을 실장하는 단계(S17) 및 반도체 칩(170)의 적어도 일면을 감싸는 봉지재를 형성하는 단계(S18)가 이루어진다. 적어도 하나의 반도체 칩(170)이 재배선층(140)의 제 2면(140b) 상에 실장될 수 있다. 반도체 칩(170)은 하면에 내부 연결 부재(172)를 포함할 수 있으며, 상기 내부 연결 부재(172)는 도전성 패드(114)에 부착될 수 있다. 내부 연결 부재(172)는 구리 또는 솔더를 포함할 수 있다.
봉지재(180)는 재배선층(140)의 제2 면(140b) 및 반도체 칩(170)들 사이에 형성될 수 있다. 상기 봉지재(180)는 반도체 칩(170)들이 손상되지 않게 보호할 수 있다. 일 실시예에서, 봉지재(180)는 반도체 칩(170) 상에 형성된 후, 평탄화 공정에 의해 상부가 일부 식각될 수 있다. 상기 봉지재(180)의 상단은 반도체 칩(170)의 상단과 동일한 레벨에 위치할 수 있다.
상기 봉지재(180)는 에폭시(epoxy) 또는 폴리이미드 등을 포함하는 수지일 수 있다. 예를 들면, 비스페놀계 에폭시 수지(Bisphenol-group Epoxy Resin), 다방향족 에폭시 수지(Polycyclic Aromatic Epoxy Resin), 올소크레졸 노블락계 에폭시 수지(o-Cresol Novolac Epoxy Resin), 바이페닐계 에폭시 수지(Biphenyl-group Epoxy Resin) 또는 나프탈렌계 에폭시 수지(Naphthalene-group Epoxy Resin) 등일 수 있다.
도 11을 참조하면, 캐리어(160)가 제거되는 단계(S19)가 이루어진다. 재배선층(140) 및 외부 연결 부재(150)에 부착된 접착제(162)를 디본딩함으로써 캐리어(160)가 제거될 수 있다. 반도체 패키지(100)는 다이싱됨으로써 완성될 수 있다. 이와 같이 완성된 반도체 패키지(100)는 외부 연결 부재(150)를 통하여 인쇄 회로 기판(110)에 전기적으로 연결되도록 실장될 수 있다. 본 개시의 일 실시예에 따른 반도체 패키지(100) 상에는 다른 패키지 또는 부품이 더 탑재될 수 있다.
도 3 내지 도 11에 도시된 바와 같이, 반도체 칩(170)에 연결되는 도전성 패드(114)를 재배선층(140) 형성 전에 배치함으로써, 도전성 패드(114), 재배선층(140) 및 외부 연결 부재(150)를 형성하는 단계들 (S12, S13, S14)이 일련의 공정으로 수행될 수 있다. 본 개시의 일 실시예에 따른 반도체 패키지 제조 방법은 TSV(through silicon via)가 사용되지 않으며, WSS(wafer support system)가 한번만 사용되어 간소화된 공정을 제공할 수 있다. 도전성 패드(114)는 실리콘 기판(110)을 식각하여 형성되는 트렌치(112)의 내부에 배치되므로, 도전성 패드(114)의 간격이 미세하게 형성될 수 있다.
도 12는 본 개시의 다른 실시예에 따른 반도체 패키지(200)의 단면도이다.
도 12를 참조하면, 도전성 패드(114)의 상면에는 솔더캡(274)이 더 배치될 수 있다. 여기에서 상면은 도전성 패드(114)의 제2 면(114b)을 의미할 수 있다. 솔더캡(274)은 도전성 패드(114)와 내부 연결 부재(272)의 접속을 용이하게 할 수 있다. 상기 솔더캡(274)은 반도체 칩(170)이 실장되기 전에 도전성 패드(114) 상면에 준비될 수 있다.
도 13 및 도 14는 본 개시의 다른 실시예에 따른 도전성 패드를 설명하기 위한 단면도이다. 상술한 바와 같이, 트렌치 내부에 도전성 패드를 형성하는 단계는 도전성 물질을 제1 시드층 상에 형성한 후 CMP 공정이 이루어질 수 있다. 물질의 표면을 평탄화하기 위해 CMP공정이 사용되나, 과연마되어 디싱(dishing) 또는 부식(erosion) 등의 현상이 발생될 수 있다.
도 13은 CMP 공정 후 디싱 현상이 발생된 것을 도시한다. 도 13에 도시된 바와 같이, 도전성 패드(314)는 과연마될 수 있으며, 도전성 패드(314)의 제1 면(314a)이 기판(110)의 제1 면(110a)보다 낮은 레벨에 위치하도록 형성될 수 있다. 예를 들어, 도전성 패드(314)의 제1 면(314a)은 제2 면(314b)을 향해 오목하게 형성될 수 있다. 제1 배리어층(120) 및 제1 시드층(122)은 과연마되지 않은 것으로 도시되어 있으나, 이에 제한되지 않는다.
도 14는 CMP 공정 후 부식 현상이 발생된 것을 도시한다. 도 14에 도시된 바와 같이, 기판(410) 및 도전성 패드(414)는 과연마될 수 있다. 기판(410)의 제1 면(410a)은 제 2면(410b)을 향해 오목하게 형성될 수 있으며, 도전성 패드(414)의 제1 면(414a)은 제2 면(414b)을 향해 오목하게 형성될 수 있다.
도 15a 내지 도 15b는 본 개시의 다른 실시예에 따른 반도체 패키지의 일부 확대도이다.
도 15a은 도 13에 도시된 도전성 패드(314)를 이용하여 도 4 내지 도 11에 도시된 제조 방법에 따라 제조된 반도체 패키지(400)의 일부 확대도이다. 도 15a는 도 11의 다른 실시예로서, 반도체 패키지(100)의 영역 R에 대응할 수 있다. 도 15a를 참조하면, 도전성 패드(314)의 제1 면(314a)은 재배선층(140)의 제2 면(140b)보다 높은 레벨에 위치할 수 있으며, 예를 들어 도전성 패드(314)의 제1 면(314a)은 제2 면(314b)을 향해 오목하게 형성될 수 있다. 제2 배리어층(331)은 도전성 패드(314)의 제1 면(314a)을 따라 오목하게 배치될 수 있다. 제2 시드층(333)은 제2 배리어층(331)의 하부에 표면을 따라 형성되며 제2 시드층(333)의 하부면은 재배선층(140)의 제2 면(140b)과 동일한 레벨에 위치할 수 있다.
도 15b은 도 14에 도시된 도전성 패드(414)를 이용하여 도 4 내지 도 11에 도시된 제조 방법에 따라 제조된 반도체 패키지(400)의 일부 확대도이다. 도 15b는 도 11의 다른 실시예로서, 반도체 패키지(100)의 영역 R에 대응할 수 있다. 도 15b를 참조하면, 도전성 패드(414)의 제1 면(414a)은 재배선층(140)의 제2 면(140b)보다 높은 레벨에 위치할 수 있다. 예를 들어, 도전성 패드(414)의 제1 면(414a)은 재배선층(140)의 제 2면(140b)에 대해 기울어진 모양을 가지며, 도전성 패드(414)의 제1 면(414a)의 하단은 재배선층(140)의 제2 면(140b)보다 높은 레벨에 위치할 수 있다. 제2 배리어층(431)은 도전성 패드(414)의 제1 면(414a)을 따라 비스듬히 형성될 수 있다. 제2 시드층(433)은 제2 배리어층(431)의 하부에 표면을 따라 형성되며 제2 시드층(433)의 하부면은 재배선층(140)의 제2 면(140b)과 동일한 레벨에 위치할 수 있다.
도 16은 본 개시의 다른 실시예에 따른 반도체 패키지(500)의 트렌치를 설명하기 위한 단면도이다. 도 17은 본 개시의 다른 실시예에 따른 반도체 패키지(500)의 단면도이다.
도 16을 참조하면, 트렌치(512)의 측면(512a)은 스캘럽 형상을 가질 수 있다. 트렌치(512)는 실리콘 기판(110)을 식각하여 형성될 수 있으며, 식각 공정은 보쉬 에칭 공정이 사용될 수 있다. 보쉬 에칭 공정은 실리콘 기판(110)에 제1 리세스를 형성하는 과정, 제1 리세스에 보호막을 증착하는 과정 및 보호막이 증착된 제1 리세스를 식각하여 제2 리세스를 형성하는 과정을 포함할 수 있다. 상기 공정이 반복되어 트렌치(512)가 형성될 수 있다. 보호막은 트렌치(512) 형성 후 제거될 수 있다. 이와 같이 보쉬 에칭 공정에 의해 형성된 트렌치(512)의 측면(512a)은 스캘럽 형상을 가질 수 있다.
도 17은 도 16에 도시된 트렌치(512)에 대해 도 3 내지 도 11에 도시된 제조 방법을 이용하여 제조된 반도체 패키지를 도시한다. 트렌치(512)의 내부에서 형성된 도전성 패드(514)의 측면(515)은 스캘럽 형상을 가질 수 있다.
도 18은 본 개시의 다른 실시예에 따른 반도체 패키지(600)의 트렌치를 설명하기 위한 단면도이다. 도 19는 본 개시의 다른 실시예에 따른 반도체 패키지(600)의 단면도이다.
도 18을 참조하면, 트렌치(612)의 측면(612a)은 기울어진 형상을 가질 수 있다. 예를 들어, 트렌치(612)의 폭은 기판(110)의 제1 면(110a)으로부터 제2 면(110b) 방향으로 갈수록 좁아 지도록 형성될 수 있다.
도 19는 도 18에 도시된 트렌치(612)에 대해 도 3 내지 도 11에 도시된 제조 방법을 이용하여 제조된 반도체 패키지를 도시한다. 도 18에 도시된 트렌치(612)의 내부에서 형성된 도전성 패드(614)는 제1 면(614a)이 제 2면(614b)보다 넓은 형상을 가질 수 있다. 또한, 도전성 패드(614)의 측면(615)은 기울어진 형상을 가질 수 있다.
도 20은 본 개시의 다른 실시예에 따른 반도체 패키지(700)의 트렌치를 설명하기 위한 단면도이다. 도 21은 본 개시의 다른 실시예에 따른 반도체 패키지(700)의 도전성 패드를 설명하기 위한 단면도이다. 도 22는 본 개시의 다른 실시예에 따른 반도체 패키지(700)의 단면도이다.
일반적으로 트렌치를 형성하는 단계는 일반적으로 실리콘 기판 전체에 균일 두께의 감광제를 입히는 도포(Coating)- 과정, 마르지 않은 감광제 용제를 열처리하는 소프트 베이크(Soft Bake) 과정, 포토 마스크 패턴을 실리콘 기판의 표면으로 옮기는 노광(Exposure) 작업, 식각 시킬 부위의 감광막을 제거하는 현상(Develope) 과정, 및 잔류 용제를 증발시켜 밀착력 향상, 막의 정밀도를 높여 식각 등 후속 공정을 위한 하드 베이크(Hard Bake) 과정을 포함할 수 있다.
도 20 및 도 2를 참조하면, 실리콘 기판(110)에 복수의 트렌치를 형성하는 단계(S11)에 있어서, 높이가 다양한 트렌치(712, 713)가 형성될 수 있다. 우선, 제1 개구부(792) 및 제2 개구부(793)를 갖는 마스크(790)가 실리콘 기판(110) 상에 배치될 수 있다. 제2 개구부(793)의 폭은 제1 개구부(792)의 폭보다 넓게 형성될 수 있다. 상기 마스크(790)가 덮인 실리콘 기판(110)은 DRIE(deep reactive ion etching) 공정 등을 통해 소정의 깊이로 식각될 수 있다. 제1 트렌치(712)는 기판(110)이 제1 개구부(792)에 의해 노출된 부분에 형성되며, 제2 트렌치(713)는 기판(110)이 제2 개구부(793)에 의해 노출된 부분에 형성될 수 있다. 제2 트렌치(713)는 제1 트렌치(712)보다 넓은 폭을 가질 수 있다. 일 실시예에서, 제2 트렌치(713)의 깊이는 제1 트렌치(712)의 깊이보다 깊게 형성될 수 있다.
도 21을 참조하면, 상기 제1 트렌치(712) 및 제2 트렌치(713)에는 각각 제1 도전성 패드(714) 및 제2 도전성 패드(715)가 배치될 수 있다. 제1 도전성 패드(714) 및 제2 도전성 패드(715)는 동일한 물질을 포함할 수 있다. 예를 들어, 제1 도전성 패드(714) 및 제2 도전성 패드(715)는 구리를 포함할 수 있다. 제2 도전성 패드(715)는 제1 도전성 패드(714) 보다 넓은 폭을 가질 수 있으며, 일 실시예에서 제2 도전성 패드(715)의 높이는 제1 도전성 패드(714)의 높이보다 클 수 있다. 도 3에서 설명된 바와 같이, 제1 트렌치(712)의 내벽에는 제1 배리어층(720)이 배치될 수 있으며, 제1 시드층(721)이 제1 배리어층(720) 상에 배치될 수 있다. 제1 도전성 패드(714)는 제1 트렌치(712)의 내부에, 제1 시드층(721) 상에 배치될 수 있다. 마찬가지로, 제2 트렌치(712)의 내벽에는 제1 배리어층(722)이 배치될 수 있으며, 제1 시드층(723)이 제1 배리어층(722) 상에 배치될 수 있다. 제2 도전성 패드(715)는 제2 트렌치(713)의 내부에, 제1 시드층(723) 상에 배치될 수 있다.
도 22는 제1 도전성 패드(714) 및 제2 도전성 패드(715)가 배치된 후, 도4 내지 도 11에 도시된 방법에 의해 제조된 반도체 패키지(700)를 도시한다. 제1 도전성 패드(714) 상에는 제1 반도체 칩(770)이 실장되고, 제2 도전성 패드(715) 상에는 제2 반도체 칩(775)이 실장될 수 있다. 예를 들어, 제1 반도체 칩(770)은 DRAM, SRAM, HBM(high bandwidth memory), HMC(hybrid memory cube) 등과 같은 메모리 소자를 포함할 수 있으며, 제2 반도체 칩(775)은 애플리케이션 프로세서 또는 그래픽 처리 장치(graphics processing unit, GPU) 등과 같은 로직 칩을 포함할 수 있다. 시스템 인 패키지(system in package; SiP)에서는 이종의 칩이 단일 패키지에 실장될 수 있다. 제2 도전성 패드(715)의 하부에는 제2 배리어층(731)이 배치되며, 제2 배리어층(731)의 하부에는 제2 시드층(733)이 배치될 수 있다.
도 20 및 도 21에 도시된 바와 같이, 기판(110)에 트렌치를 형성하는 방법을 통해 서로 다른 크기를 갖는 제1 도전성 패드(714) 및 제2 도전성 패드(715)를 하나의 공정에서 형성함으로써, 패키지 제조 공정이 간소화 될 수 있다.
도 23은 본 개시의 다른 실시예에 따른 반도체 패키지(800)의 도전성 패드 및 인터커넥터를 설명하기 위한 단면도이다. 도 24 및 도 25는 본 개시의 다른 실시예에 따른 반도체 패키지(800)의 제조 방법을 설명하기 위한 단면도이다.
도 23을 참조하면, 도 20에 도시된 방법에 의해 서로 다른 높이를 갖는 트렌치가 형성될 수 있다. 상기 트렌치들의 내부에는 도전성 패드(814) 및 인터커넥터(815)가 배치될 수 있다. 도전성 패드(814) 및 인터커넥터(815)는 동일한 물질을 포함할 수 있다. 예를 들어, 도전성 패드(814) 및 인터커넥터(815)는 구리를 포함할 수 있다. 인터커넥터(815)의 폭은 도전성 패드(814)의 폭보다 넓게 형성될 수 있으며, 인터커넥터(815)의 높이는 도전성 패드(814)의 높이보다 높게 형성될 수 있다. 도 3에서 설명된 바와 같이, 트렌치의 내벽에는 제1 배리어층(820)이 배치될 수 있으며, 제1 시드층(821)이 제1 배리어층(820) 상에 배치될 수 있다. 도전성 패드(814)는 트렌치의 내부에서, 제1 시드층(821) 상에 배치될 수 있다. 마찬가지로, 트렌치의 내벽에는 제1 배리어층(822)이 배치될 수 있으며, 제1 시드층(823)이 제1 배리어층(822) 상에 배치될 수 있다. 인터커넥터(815)는 트렌치의 내부에서, 제1 시드층(823) 상에 배치될 수 있다.
도 24는 도전성 패드(814) 및 인터커넥터(815)가 배치된 후, 도 4 내지 도 11에 도시된 방법에 의해 제조된 하부 패키지(802)를 도시한다. 하부 패키지(802)는 인터커넥터(815), 재배선층(140), 반도체 칩(870) 및 봉지재(180)를 포함할 수 있다. 인터커넥터(815)의 상단은 봉지재(180)의 상단과 실질적으로 동일한 레벨에 위치할 수 있으며, 일 실시예에서 인터커넥터(815)의 상면은 반도체 칩(870)의 상면과 실질적으로 동일한 레벨에 위치할 수 있다. 예를 들어, 인터커넥터(815) 및 반도체 칩(870)의 적어도 일면을 감싸는 봉지재(180)가 형성된 후, 상기 인터커넥터(815), 반도체 칩(870) 및 봉지재(180)가 평탄화 되도록 평탄화 공정이 진행될 수 있다. 인터커넥터(815)의 상단은 외부로 노출될 수 있다. 다른 실시예에서, 인터커넥터(815)의 상면은 반도체 칩(870)의 상면보다 높은 레벨에 위치할 수 있다. 인터커넥터(815)의 하부에는 제2 배리어층(831)이 배치되며, 제2 배리어층(831)의 하부에는 제2 시드층(833)이 배치될 수 있다.
도 25를 참조하면, 하부 패키지(802) 상에 상부 패키지(804)가 적층된 반도체 패키지(800)가 도시되어 있다. 상부 패키지(804)는 상부 기판(840), 상부 반도체 칩(875), 상부 연결 부재(874) 및 봉지재(876)를 포함할 수 있다. 상부 패키지(804)는 하부 패키지(802)와는 다른 기능을 가질 수 있다. 예를 들어, 하부 패키지(802)는 로직 연산을 수행할 수 있으며, 상부 패키지(804)는 메모리 소자로서 기능할 수 있다.
상부 기판(840)은 인쇄 회로 기판, 실리콘 기판 또는 재배선층으로 형성될 수 있다. 상부 반도체 칩(875)은 반도체 칩(870)과는 다른 종류의 동작을 수행할 수 있다. 예를 들어, 상부 반도체 칩(875)은 DRAM, SRAM 등과 같은 메모리 칩일 수 있으며, 반도체 칩(870)은 어플리케이션 프로세서와 같은 로직 칩일 수 있다. 도 25에는 상부 반도체 칩(875)이 상부 기판에 와이어 본딩된 것이 도시되어 있으나, 이에 제한되지 않는다. 일 실시예에서 상부 반도체 칩(875)은 상부 기판(840)에 플립 칩 방식으로 실장될 수 있다. 상부 연결 부재(874)는 인터커넥터(815)와 전기적으로 연결될 수 있다. 상부 반도체 칩(875)은 인터커넥터(815)를 통해 재배선층(140), 반도체 칩(870) 및 외부 연결 부재(150)와 전기적으로 연결될 수 있다. 봉지재(876)는 상부 기판(840), 상부 반도체 칩(875)의 적어도 일면을 감싸도록 형성되어 상부 기판(840) 및 상부 반도체 칩(875)을 외부의 충격으로부터 보호할 수 있다. 봉지재(876)는 상술한 하부 패키지(802)의 봉지재(180)와 동일한 물질을 포함할 수 있다. 봉지재(876)는 상부 패키지(804)의 적층시에 미리 형성되어 있을 수 있다.
도 23 내지 도 25에 도시된 바와 같이, 실리콘 기판(110)에 트렌치를 형성하여 전기 도금을 수행하는 일련의 공정으로 도전성 패드(814) 및 인터커넥터(815)가 형성됨으로써, 공정이 간소화될 수 있다. 트렌치는 실리콘 기판(110)을 식각하여 형성되므로, 도전성 패드(814) 및 인터커넥터(815)가 미세한 간격으로 배치될 수 있다.
이상, 첨부된 도면을 참조하여 본 개시에 따른 실시예들을 설명하였지만, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 이상에서 기술한 실시예는 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해하여야 한다.
100, 200, 300, 400, 500, 600, 700 ,800 : 반도체 패키지
110 : 기판 112 : 트렌치
114 : 도전성 패드 120 : 제1 배리어층
122 : 제1 시드층 130 : 제2 배리어층
132 : 게이트 절연층 140 : 재배선층
150 : 외부 연결 부재 160 : 캐리어
170 : 반도체 칩 180 : 봉지재
802 : 하부 패키지 804 : 상부 패키지

Claims (10)

  1. 실리콘 기판의 일면에 복수의 트렌치를 형성하는 단계;
    상기 복수의 트렌치의 내부에 상기 실리콘 기판과 공면을 이루는 제1 면 및 상기 제1 면과 반대되는 제2 면을 갖는 도전성 패드를 형성하는 단계;
    상기 실리콘 기판의 일면 및 상기 도전성 패드의 상기 제1 면 상에 재배선층을 형성하는 단계;
    상기 재배선층의 제1 면 상에 외부 연결 부재를 형성하는 단계;
    상기 도전성 패드의 상기 제2 면 및 측면이 노출되도록 상기 실리콘 기판을 제거하는 단계;
    상기 도전성 패드의 상기 제2 면에 연결되는 반도체 칩을 실장하는 단계; 및
    상기 도전성 패드의 상기 측면 및 상기 반도체 칩의 적어도 일면을 감싸는 봉지재를 형성하는 단계를 포함하는 반도체 패키지 제조 방법.
  2. 제1항에 있어서,
    상기 도전성 패드를 형성하는 단계 후에, 상기 실리콘 기판의 일면 상에 배리어층 및 시드층을 순차적으로 증착하는 단계를 더 포함하고, 상기 재배선층은 상기 시드층 상에 배치되는 반도체 패키지 제조 방법.
  3. 제2항에 있어서,
    상기 배리어층은 티타늄을 포함하고, 상기 시드층은 구리를 포함하는 반도체 패키지 제조 방법.
  4. 제2항에 있어서,
    상기 실리콘 기판을 제거하는 단계 후에, 상기 배리어층 및 상기 시드층의 일부를 제거하는 단계를 더 포함하는 반도체 패키지 제조 방법.
  5. 제4항에 있어서,
    상기 도전성 패드와 상기 재배선층 사이에 배치되는 상기 배리어층 및 시드층은 제거되지 않는 반도체 패키지 제조 방법.
  6. 실리콘 기판의 일면에 복수의 제1 트렌치 및 상기 제1 트렌치보다 깊게 형성되는 복수의 제2 트렌치를 형성하는 단계;
    상기 복수의 제1 트렌치 내부에 상기 실리콘 기판과 공면을 이루는 제1 면 및 상기 제1 면과 반대되는 제2 면을 갖는 제1 도전성 패드를 형성하고, 상기 복수의 제2 트렌치의 내부에 제2 도전성 패드를 형성하는 단계;
    상기 실리콘 기판의 일면 상에 재배선층을 형성하는 단계;
    상기 재배선층의 제1 면 상에 외부 연결 부재를 형성하는 단계;
    상기 제1 도전성 패드의 상기 제2 면, 측면 및 제2 도전성 패드가 노출되도록 실리콘 기판을 제거하는 단계;
    상기 제1 도전성 패드의 상기 제2 면에 연결되는 제1 반도체 칩을 실장하는 단계; 및
    상기 제1 도전성 패드의 상기 측면 및 상기 제1 반도체 칩의 적어도 일면을 감싸는 봉지재를 형성하는 단계를 포함하는 반도체 패키지 제조 방법.
  7. 제6항에 있어서,
    상기 제2 도전성 패드에 연결되는 제2 반도체 칩을 실장하는 단계를 더 포함하는 반도체 패키지 제조 방법.
  8. 제7항에 있어서,
    상기 제2 도전성 패드는 제1 도전성 패드보다 높게 형성되는 반도체 패키지 제조 방법.
  9. 제6항에 있어서,
    상기 제2 도전성 패드는 인터커넥터이며, 상기 인터커넥터의 상면은 상기 제1 반도체 칩의 상면과 동일한 레벨 또는 상기 제1 반도체 칩의 상면보다 높은 레벨에 위치하는 반도체 패키지 제조 방법.
  10. 제9항에 있어서,
    상기 인터커넥터와 전기적으로 연결되며 내부에 제2 반도체 칩을 포함하는 상부 패키지를 상기 제1 반도체 칩의 상부에 적층하는 단계를 더 포함하는 반도체 패키지 제조 방법.
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US16/293,697 US11315802B2 (en) 2018-08-24 2019-03-06 Method for manufacturing semiconductor package having redistribution layer
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