CN108511426A - 封装 - Google Patents

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Publication number
CN108511426A
CN108511426A CN201711289180.XA CN201711289180A CN108511426A CN 108511426 A CN108511426 A CN 108511426A CN 201711289180 A CN201711289180 A CN 201711289180A CN 108511426 A CN108511426 A CN 108511426A
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China
Prior art keywords
dielectric
layer
integrated circuit
sheet type
dielectric layer
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Granted
Application number
CN201711289180.XA
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English (en)
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CN108511426B (zh
Inventor
余振华
刘重希
史朝文
吴凯强
张守仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN108511426A publication Critical patent/CN108511426A/zh
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Abstract

一种实施例封装包括：集成电路管芯，包封在包封体中；贴片式天线，位于所述集成电路管芯之上；以及介电特征，设置在所述集成电路管芯与所述贴片式天线之间。所述贴片式天线在俯视图中与所述集成电路管芯交叠。所述介电特征的厚度是根据所述贴片式天线的工作带宽。

Description

封装
技术领域
本发明实施例涉及一种封装。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度持续增大，半导体行业已经历快速增长。在很大程度上，集成密度的增大来自于最小特征大小(feature size)的不断缩减，这使得能够将更多的组件集成到给定区域中。随着对缩减电子装置大小的需求的增长，需要更小且更具创造性的半导体管芯封装技术。这种封装系统的一个实例是叠层封装(Package-on-Package，PoP)技术。在叠层封装装置中，将顶部半导体封装堆叠在底部半导体封装的顶上，以提供高集成水平及高组件密度。叠层封装技术一般来说能够生产功能性得到增强且在印刷电路板(printed circuit board，PCB)上的占用面积小的半导体装置。
发明内容
本发明实施例的一种封装包括：集成电路管芯，包封在包封体中；装置，位于所述集成电路管芯之上；以及介电特征，设置在所述集成电路管芯与所述装置之间。所述装置在俯视图中与所述集成电路管芯交叠。所述装置包括信号线及接地元件。所述介电特征的厚度是根据所述装置的工作带宽。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A、图1B、及图1C示出根据一些实施例的半导体封装的各种图；
图2A、图2B、图2C、图2D及图2E示出根据一些实施例的半导体封装的一部分的剖视图；
图3A、图3B、及图3C示出根据一些替代实施例的半导体封装的各种图；
图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19、图20、图21、图22、图23、图24、及图25示出根据一些实施例的制造半导体封装的各个中间阶段的剖视图；
图26A及图26B示出根据一些替代实施例的半导体封装的各种图。
具体实施方式
以下公开内容提供用于实作本发明的不同特征的许多不同的实施例或实例。以下阐述组件及配置的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、以使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...之下(beneath)”、“在...下面(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性用语可同样相应地进行解释。
本文所论述的实施例可在具体上下文中论述，即在具有一个或多个集成天线及一个或多个半导体芯片(例如，射频(radio frequency，RF)芯片、基带(baseband)芯片等)的封装结构的上下文中论述。然而，也可对具有集成有一或多个半导体芯片的嵌置功能元件(例如，波导线)的其他封装应用各种实施例。
在具有集成天线的实施例中，集成天线包括贴片式天线，所述贴片式天线具有一或多条信号线(在本文中也被称为馈电线(feed line))、接地元件、以及一或多个辐射元件。在运行期间，射频芯片通过馈电线从贴片式天线的辐射元件接收信号或将信号传送到贴片式天线的辐射元件。接地元件包括接地线及/或为所述一个或多个辐射元件提供电接地的接地平面。通过将天线与半导体芯片集成在单个封装中，可实现大小的减小。
为有利地实现小的封装占用面积，在俯视图中，贴片式天线的一些部分与至少一个半导体芯片交叠。然而，已观察到，这种交叠可因由半导体芯片造成的干扰而引起贴片式天线的效率降低。各种实施例旨在通过在半导体芯片与贴片式天线(例如，贴片式天线的馈电线及接地元件)之间设置介电特征来提高贴片式天线的效率及减小来自半导体芯片的干扰。在一些实施例中，介电特征包括管芯贴合膜(die attach film)，所述管芯贴合膜用于在制造期间将半导体芯片贴合到封装。对介电特征的厚度加以选择来实现贴片式天线的期望效率。所述厚度可进一步对应于贴片式天线与半导体芯片之间的距离。举例来说，已观察到，相对厚的介电特征可在贴片式天线与半导体芯片之间提供改善的隔离。在一些实施例中，介电特征的厚度是基于天线的工作带宽(operating bandwidth)、介电特征的k值、贴片式天线的各种特征的面积、贴片式天线的期望效率、其组合等来加以选择。
图1A示出根据一些实施例的半导体封装250的剖视图。图1B及图1C示出根据一些实施例的半导体封装250的俯视图。图1A所示剖视图是沿图1B及图1C所示线1A-1A截取。
首先参照图1A，半导体封装250包括包封在包封体130中的集成电路管芯114。集成电路管芯114可为射频(RF)芯片，所述射频芯片可包括或可不包括集成在集成电路管芯114内的基带处理器。尽管在半导体封装250中仅示出一个集成电路管芯，然而根据封装设计而定，在其他实施例中在单个半导体封装中可集成有多个集成电路管芯114(例如，单独的基带芯片、处理器、存储器等)。在这些实施例中，所述多个集成电路管芯114中的每一者可被包封在包封体130中。
在运行期间，集成电路管芯114通过集成在半导体封装250中的一个或多个天线来传送及接收无线信号。举例来说，半导体封装250包括贴片式天线210，贴片式天线210包括接地元件106A、馈电线106B、介电层200的一部分、以及辐射元件204。在封装250中，接地元件106A与馈电线106B设置在同一层中。举例来说，馈电线106B可设置在延伸穿过接地元件106A的开口中，如图1A及图1C所示。在图1A、图1B、及图1C所示的实施例中，接地元件106A可进一步为馈电线106B提供屏蔽(电磁辐射屏蔽)。接地元件106A的顶表面及底表面与馈电线106B的顶表面及底表面可实质上共面。在图1C中由虚线标记辐射元件204的位置以供参考。在其他实施例中可使用实施例贴片式天线的其他配置(例如，具有更大或更小数目的馈电线)。
集成电路管芯114通过重布线结构170中的重布线以及导通孔110而电连接到接地元件106A及馈电线106B。举例来说，重布线结构170可包括设置在一个或多个介电层中的多条导电重布线。导通孔110设置在包封体130(可为模塑化合物)中且将接地元件106A及馈电线106B电连接到重布线结构170中的重布线。因此，导通孔110将接地元件106A及馈电线106B电连接到集成电路管芯114。重布线结构170中的重布线进一步将集成电路管芯114电连接到外部连接件166，外部连接件166可用于将封装250结合到另一封装组件，例如封装衬底(参见图25)。
在一些实施例中，辐射元件204通过介电层200及可选介电层104而与接地元件106A及馈电线106B隔开。举例来说，辐射元件204可粘着至介电层200的与接地元件106A/馈电线106B相对的表面。辐射元件204可使用粘合剂202而粘着到介电层200，或者可省略粘合剂202。辐射元件204电耦合到接地元件106A及馈电线106B。在一些实施例中，可对介电层200的材料加以选择以促进这种电耦合且介电层200的材料可具有相对低的耗散因数(dissipation factor，Df)。举例来说，介电层200的耗散因数可小于约0.01或者在一些实施例中甚至小于约0.001。接地元件106A可为辐射元件204提供接地平面，且馈电线106B在辐射元件204与集成电路管芯114之间中继信号206。辐射元件204继而从半导体封装250外部的其他装置接收无线信号208以及将无线信号208传送到半导体封装250外部的其他装置。
如由图1B所提供的封装250的俯视图所示，集成电路管芯114(在图1B中以虚像(ghost)示出)与接地元件106A/馈电线106B(在图1B中以虚像示出)交叠。特征的这种交叠可导致贴片式天线210(参见图1A)效率降低。举例来说，贴片式天线210的效率可能会因由集成电路管芯114造成的干扰而降低。
为减弱这种干扰并提高贴片式天线210的效率，将介电特征116并置在集成电路管芯114与贴片式天线210(例如，贴片式天线210的一些部分(接地元件106A/馈电线106B))之间。介电特征116会增强集成电路管芯114与贴片式天线210的一些部分(例如，接地元件106A/馈电线106B)之间的隔离。介电特征116具有厚度d，厚度d是从贴片式天线210的面对集成电路管芯114的表面到集成电路管芯114测得。在各种实施例中，厚度d相对厚以在集成电路管芯114与贴片式天线210之间提供合适的隔离。尽管不受限于任何特定理论，然而据信贴片式天线210的效率可由集成电路管芯与接地元件106A/馈电线106B之间的寄生电容(parasitic capacitance)来近似表示。举例来说，这些特征的较低的寄生电容与贴片式天线210的提高的效率相关。另外，集成电路管芯114与接地元件106A/馈电线106B之间的寄生电容可满足以下方程式：
其中C是集成电路管芯114与接地元件106A/馈电线106B之间的寄生电容；k是介电特征116的k值；d是介电特征116的厚度d；A是接地元件106A/馈电线106B的面积(例如，通过将接地元件106A/馈电线106B的长度L乘以接地元件106A/馈电线106B的宽度W而获得，参见图1B)；且λ是贴片式天线210的工作波长。各种实施例操纵以上参数中的一个或多个以减小寄生电容C并提高封装250中的贴片式天线210的效率。
在各种实施例中，介电特征116的厚度d是根据贴片式天线210的工作带宽(频率)、介电特征116的k值、贴片式天线210的各种特征(例如，接地元件106A及/或馈电线106B)的面积、贴片式天线210的期望效率、其组合等来加以选择。举例来说，当介电特征116的k值为约3或大于3且贴片式天线210具有为约60GHz的工作带宽时，介电特征116的厚度d可为至少100μm。作为另一实例，当介电特征116的k值小于3(例如，约1)且贴片式天线210具有为约60GHz的工作带宽时，介电特征116的厚度d可为至少30μm。作为另一实例，当介电特征116的k值为约3或大于3且贴片式天线210具有为约77GHz的工作带宽时，介电特征116的厚度d可为至少约50μm。作为另一实例，当介电特征116的k值小于3(例如，约1)且贴片式天线210具有为约77GHz的工作带宽时，介电特征116的厚度d可为至少约15μm。作为另一实例，当介电特征116的k值为约3或大于3且贴片式天线210具有为约38GHz的工作带宽时，介电特征116的厚度d可为至少约120μm。作为另一实例，当介电特征116的k值小于3(例如，约1)且贴片式天线210具有为约38GHz的工作带宽时，介电特征116的厚度d可为至少约40μm。
已观察到，当集成电路管芯114的厚度d处于以上值以内时，贴片式天线210的效率处于基线贴片式天线的效率的95％以内，而不具有来自集成电路管芯的干扰。举例来说，已对具有为约77GHz至约81GHz的工作带宽的贴片式天线以及具有为约57GHz至约64GHz的工作带宽的贴片式天线进行了实验。已在分别集成在介电特征具有约0μm、20μm、40μm、50μm、60μm、80μm、及100μm的不同厚度d的封装中的各贴片式天线之间进行了比较。也在不具有来自集成电路管芯的干扰的基线贴片式天线之间进行了比较。当厚度d为0μm且贴片式天线的工作带宽为约77GHz至约81GHz时，贴片式天线的增益为7.1dBi且贴片式天线的效率为41％。当厚度d为20μm且贴片式天线的工作带宽为约77GHz至约81GHz时，贴片式天线的增益为9.7dBi且贴片式天线的效率为70％。当厚度d为40μm且贴片式天线的工作带宽为约77GHz至约81GHz时，贴片式天线的增益为10.2dBi且贴片式天线的效率为82％。当厚度d为50μm且贴片式天线的工作带宽为约77GHz至约81GHz时，贴片式天线的增益为10.3dBi且贴片式天线的效率为84％。当厚度d为60μm且贴片式天线的工作带宽为约77GHz至约81GHz时，贴片式天线的增益为10.3dBi且贴片式天线的效率为86％。当厚度d为80μm且贴片式天线的工作带宽为约77GHz至约81GHz时，贴片式天线的增益为10.4dBi且贴片式天线的效率为88％。当厚度d为100μm且贴片式天线的工作带宽为约77GHz至约81GHz时，贴片式天线的增益为10.5dBi且贴片式天线的效率为89％。具有为约77GHz至约81GHz的工作带宽的基线贴片式天线提供为10.5dBi的增益，且所述基线贴片式天线的效率为90％。当厚度d为20μm且贴片式天线的工作带宽为约57GHz至约64GHz时，贴片式天线的带宽规格无效，贴片式天线的增益为3.95dBi，且贴片式天线的效率为42.4％。当厚度d为40μm且贴片式天线的工作带宽为约57GHz至约64GHz时，贴片式天线的增益为5.3dBi且贴片式天线的效率为66.3％。当厚度d为50μm且贴片式天线的工作带宽为约57GHz至约64GHz时，贴片式天线的增益为5.48dBi且贴片式天线的效率为70.6％。当厚度d为60μm且贴片式天线的工作带宽为约57GHz至约64GHz时，贴片式天线的增益为5.62dBi且贴片式天线的效率为73.3％。当厚度d为100μm且贴片式天线的工作带宽为约57GHz至约64GHz时，贴片式天线的增益为5.88dBi且贴片式天线的效率为78.3％。具有为约57GHz至约64GHz的工作带宽的基线贴片式天线提供为6.12dBi的增益，且所述基线贴片式天线的效率为82％。
所有以上值均假设接地元件106A/馈电线106B具有恒定的面积A。一般来说，还观察到，减小接地元件106A/馈电线106B的面积A也可使得能够在仍实现期望效率的同时具有较小的厚度d。
在图1A中，将介电特征116示出为单个介电层。在其他实施例中，介电特征116可具有任何数目的包含不同材料的介电层。举例来说，介电特征116可具有两个介电层116A及116B(例如，如由图2A所示)或三个介电层116A、116B及116C(例如，如由图2B所示)。介电特征116内的介电层中的每一者可包含管芯贴合膜、背侧涂布胶带(LC)、预浸体(prepreg，PP)材料、低介电常数材料、或类似材料。介电特征116可具有与集成电路管芯114相同的宽度(例如，在介电特征116的相对的侧壁之间测得)(例如，如由图1A所示)，具有比集成电路管芯114大的宽度(例如，如由图2C所示)，或者具有比集成电路管芯114小的宽度(例如，如由图2D所示)。另外，介电层中的每一者(例如，介电层116A、116B、及/或116C)可具有相同的宽度(例如，如由图2A、图2B、图2C、及图2D所示)或者不同的宽度(例如，如由图2E所示)。当介电特征116包括多个介电层时，可使用主要介电层116A的厚度及/或k值作为近似值来计算厚度d以减小寄生电容。主要介电层116A可为占据整个介电特征116的大部分体积(例如，大于50％(例如，大于约80％))的介电层。在其他实施例中，可使用k值及/或厚度的权重平均值来计算厚度d以减小寄生电容。
半导体封装250可还包括附加天线，例如辐射天线108。在一些实施例中，辐射天线108包括延伸穿过包封体130的导电特征。辐射天线108通过重布线结构170中的重布线电连接到集成电路管芯114。对辐射天线108的形状及配置加以选择以使得能够向位于封装250外部的其他装置(图中未示出)发送无线信号以及从位于封装250外部的其他装置(图中未示出)接收无线信号。在其他实施例中，可省略辐射天线108。
图3A、图3B、及图3C示出根据一些实施例的半导体封装280的各种图。图3A示出半导体封装280的剖视图；图3B示出接地元件106A的俯视图，且图3C示出馈电线106B及可选接地元件106C的俯视图。封装280实质上相似于封装250，其中相同的参考编号表示相同的元件。在封装280中，接地元件106A与馈电线106B设置在不同的层中。举例来说，接地元件106A可沿与半导体封装280的侧表面垂直的线设置在馈电线106B与集成电路管芯之间。在一些实施例中，可选附加接地元件106C(参见图3C)可与馈电线106B设置在同一层中。
图4至图26B示出根据一些实施例的在用于形成半导体封装250的工艺期间的中间步骤的剖视图。图4示出载体衬底100以及形成在载体衬底100上的释放层102。分别示出用于形成第一封装及第二封装的第一封装区600及第二封装区602。
载体衬底100可为玻璃载体衬底、陶瓷载体衬底或类似衬底。载体衬底100可为晶片，使得可在载体衬底100上同时形成多个封装。释放层102可由聚合物系材料形成，所述聚合物系材料可与载体衬底100一起从将在后续步骤中形成的上覆结构被移除。在一些实施例中，释放层102是在受热时会丧失其粘着性质的环氧树脂系热释放材料，例如光热转换(light-to-heat-conversion，LTHC)释放涂层。在其他实施例中，释放层102可为在暴露至紫外光时会丧失其粘着性质的紫外光(ultra-violet，UV)胶。释放层102可作为液体进行分配并进行固化，可为被叠层到载体衬底100上的叠层膜(laminate film)，或可为类似形式。释放层102的顶表面可为齐平(leveled)且可具有高的共面度(degree of coplanarity)。
在图5中，形成介电层104及金属化图案(例如，接地元件106A及馈电线106B)。如图2所示，在释放层102上形成介电层104。介电层104的底表面可接触释放层102的顶表面。在一些实施例中，介电层104是由例如以下聚合物形成：聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene，BCB)。在其他实施例中，介电层104是由氮化物(例如，氮化硅)、氧化物(例如，氧化硅)、磷硅酸盐玻璃(phosphosilicateglass，PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、掺杂有硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)等形成。可通过例如以下任何可接受的沉积工艺来形成介电层104：旋转涂布(spin coating)、化学气相沉积(chemical vapor deposition，CVD)、叠层、类似工艺、或其组合。可将介电层104形成为提供实质上平坦的顶表面以形成后续特征。
金属化图案可包括接地元件106A及馈电线106B，例如，如图1A、图1B、及图1C所示。作为形成接地元件106A及馈电线106B的实例，在介电层104之上形成晶种层(图中未示出)。在一些实施例中，晶种层是金属层，所述金属层可为单个层或为包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积(physical vapor deposition，PVD)等来形成晶种层。接着在晶种层上形成光刻胶(photo resist)并将所述光刻胶图案化。可通过旋转涂布或类似工艺来形成光刻胶且可将光刻胶暴露至光以进行图案化。光刻胶的图案对应于接地元件106A及馈电线106B。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。导电材料可通过镀覆(例如，电镀或无电镀覆等)来形成。导电材料可包括金属，如铜、钛、钨、铝等。接着，移除光刻胶以及晶种层的上面未形成导电材料的部分。光刻胶可通过可接受的灰化工艺(ashing process)或剥除工艺(strippingprocess)来移除，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，便例如使用可接受的刻蚀工艺(例如，通过湿刻蚀(wet etching)或干刻蚀(dry etching))来移除晶种层的暴露部分。晶种层的剩余部分与导电材料形成接地元件106A及馈电线106B。
介电层104及介电层104上形成的金属化图案(例如，接地元件106A及馈电线106B)可被称为背侧金属化结构。如图中所示，背侧金属化结构包括一个介电层104及一个金属化图案(接地元件106A及馈电线106B)。在其他实施例中，背侧重布线结构可包括任何数目的介电层、金属化图案、及通孔。举例来说，当馈电线106B及接地元件106A设置在不同的层中时(例如，如由图3A、图3B、及图3C所示)，背侧重布线结构可包括形成在两个介电层中的两个金属化图案。在这些实施例中，可将接地元件106A形成在馈电线106B之上或下方。可通过重复进行所述形成介电层104、馈电线106B、及接地元件106A的工艺而在背侧金属化结构中形成一个或多个额外的金属化图案及介电层。可在所述形成金属化图案期间通过在下伏介电层的开口中形成金属化图案的晶种层及导电材料来形成通孔。通孔因此可对各个金属化图案(例如，图3A中的馈电线106B及接地元件106A)进行互连及电耦合。
接下来在图6中，形成穿孔(导通孔110)及(可选地)形成辐射天线108。作为形成穿孔(导通孔110)及辐射天线108的实例，在背侧重布线结构(例如，所示介电层104、接地元件106A、及馈电线106B)之上形成晶种层。在一些实施例中，晶种层是金属层，所述金属层可为单个层或为包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积等来形成晶种层。在晶种层上形成光刻胶并将所述光刻胶图案化。可通过旋转涂布或类似工艺来形成光刻胶且可将光刻胶暴露至光以进行图案化。光刻胶的图案对应于穿孔。所述图案化会形成穿过光刻胶以暴露出晶种层的开口。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。导电材料可通过镀覆(例如，电镀或无电镀覆等)来形成。导电材料可包括金属，如铜、钛、钨、铝等。移除光刻胶以及晶种层的上面未形成导电材料的部分。光刻胶可通过可接受的灰化工艺或剥除工艺来移除，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，便例如使用可接受的刻蚀工艺(例如，通过湿刻蚀或干刻蚀)来移除晶种层的暴露部分。所述晶种层的剩余部分与所述导电材料形成穿孔(导通孔110)及(可选地)形成辐射天线108。如图中所示，可将穿孔(导通孔110)直接形成在接地元件106A的一些部分上。在一些实施例中，穿孔(导通孔110)及辐射天线108同时形成。在其他实施例中，穿孔(导通孔110)可在辐射天线108之前或之后形成。
在图7中，通过介电特征116将集成电路管芯114粘着到背侧重布线结构(例如，接地元件106A/馈电线106B)。如图7所示，将一个集成电路管芯114粘着到第一封装区600及第二封装区602中的每一者中，且在其他实施例中，可在每一区中粘着更多或更少的集成电路管芯114。集成电路管芯114可为射频管芯、基带管芯、逻辑管芯(例如，中央处理器(centralprocessing unit)、微控制器等)、存储器管芯(例如，动态随机存取存储器(dynamicrandom access memory，DRAM)管芯、静态随机存取存储器(static random accessmemory，SRAM)管芯等)、电力管理管芯(例如，电力管理集成电路(power managementintegrated circuit，PMIC)管芯)、传感器管芯、微机电系统(micro-electro-mechanical-system，MEMS)管芯、信号处理管芯(例如，数字信号处理(digital signal processing，DSP)管芯)、前端管芯(例如，模拟前端(analog front-end，AFE)管芯)、类似管芯、或其组合。另外，在一些实施例中，集成电路管芯114可为不同大小(例如，不同的高度及/或表面积)，且在其他实施例中，集成电路管芯114可为相同大小(例如，相同的高度及/或表面积)。
在粘着到介电层104之前，可根据适用于在集成电路管芯114中形成集成电路的制造工艺来加工集成电路管芯114。举例来说，集成电路管芯114各自分别包括半导体衬底118，例如经掺杂的或未经掺杂的硅、或绝缘体上半导体(semiconductor-on-insulator，SOI)衬底的有源层。半导体衬底可包含：其他半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或其组合。也可使用例如多层式衬底(multi-layered substrate)或梯度衬底(gradient substrate)等其他衬底。可在半导体衬底118中及/或半导体衬底118上形成例如晶体管、二极管、电容器、电阻器等装置且所述装置可通过由例如位于半导体衬底118上的一个或多个介电层中的金属化图案形成的内连线结构120进行互连以形成集成电路。
集成电路管芯114还包括进行外部连接的接垫122，例如铝接垫。接垫122位于可被称为集成电路管芯114的相应有源侧的位置上。保护膜(passivation film)124位于集成电路管芯114上且位于接垫122的部分上。开口穿过保护膜124到达接垫122。例如导电柱(例如，包含例如铜等金属)等可选管芯连接件126位于穿过保护膜124的开口中，并且机械地耦合到且电耦合到相应的接垫122。管芯连接件126可通过例如镀覆等来形成。管芯连接件126对集成电路管芯114的相应的集成电路进行电耦合。
可选介电材料128位于集成电路管芯114的有源侧上，例如位于保护膜124及管芯连接件126上。介电材料128在横向上包封管芯连接件126，且介电材料128在横向上与相应的集成电路管芯114相接。介电材料128可为：聚合物，例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等；氮化物，例如，氮化硅等；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂有硼的磷硅酸盐玻璃等；类似材料、或其组合，且介电材料128可例如通过旋转涂布、层叠、化学气相沉积或类似方法形成。
在其他实施例中，可不包括管芯连接件126及介电材料128，且可将后续形成的重布线结构直接形成在保护膜124及接垫122上。举例来说，在这些实施例中，可直接将已完成的重布线结构170(参见图21)形成在保护膜124及接垫122上以使得重布线结构170中的金属化图案(有时称为重布线)138(参见图21)接触接垫122。
介电特征116位于集成电路管芯114的背侧上并将集成电路管芯114粘着到背侧重布线结构(例如，图式中的介电层104)。介电特征116可包括由例如以下任何合适的材料形成的一个或多个层：管芯贴合膜、低介电常数材料、预浸体材料、背侧涂布胶带、或类似材料。如以上参照图1A、图1B、及图1C所论述，可对介电特征116的厚度加以选择以改善集成电路管芯114与包括接地元件106A及馈电线106B的贴片式天线(例如，图1A及图1C所示贴片式天线210)之间的隔离。与将半导体封装的各个层制作成尽可能薄的传统期望相反，可增大介电特征116的厚度以改善接地元件106A/馈电线106B与集成电路管芯114之间的隔离。在各种实施例中，介电特征116的厚度可根据贴片式天线的工作带宽(例如，频率)、贴片式天线的期望效率、介电特征116的k值、以及接地元件106A在俯视图中的面积、其组合等来加以选择。举例来说，介电特征116可具有以上参照图1A、图1B、及图1C所论述的与k值及/或工作带宽对应的厚度d中的任意者。厚度d也可对应于集成电路管芯114与接地元件106A/馈电线106B之间的距离。
另外，尽管介电特征116被示出为具有与相应的集成电路管芯114相同宽度的单个层，然而介电特征116也可包括由不同的介电材料形成的多个层及/或可比集成电路管芯114(例如，如以上参照图2A、图2B、图2C、图2D、及图2E所阐述)宽或窄。可将介电特征116施加到集成电路管芯114的背侧，例如施加到相应的半导体晶片的背侧或者可施加到载体衬底100的表面之上。可例如通过锯切或切割来将集成电路管芯114单体化，且使用例如拾取及放置工具(pick-and-place tool)通过介电特征116将集成电路管芯114粘着到接地元件106A/馈电线106B。因此，在对集成电路管芯114进行贴合之后，介电特征116可填充接地元件106A与馈电线106B之间的空间。举例来说，介电特征116可延伸穿过接地元件106A中的开口到达介电层104。
在图8中，在各种组件上形成包封体130。包封体130可为模塑化合物、环氧树脂等，且可通过压缩模塑(compression molding)、转移模塑(transfer molding)等来施加。在固化之后，包封体130可经历研磨工艺(grinding process)以暴露出穿孔(导通孔110)、辐射天线108、及管芯连接件126。在研磨工艺之后，穿孔(导通孔110)的顶表面、辐射天线108的顶表面、管芯连接件126的顶表面、及包封体130的顶表面是共面的。在一些实施例中，例如如果已暴露出穿孔(导通孔110)、辐射天线108、及管芯连接件126，则可省略所述研磨。
在图9至图18中，形成前侧重布线结构170(参见图18)。如将在图18中示出，前侧重布线结构170包括介电层132、140、148、及156以及金属化图案(有时称为重布线层或重布线)138、146、及154。
在图9中，在包封体130、穿孔(导通孔110)、辐射天线108及管芯连接件126上沉积介电层132。在一些实施例中，介电层132是由可使用光刻掩模(lithography mask)进行图案化的聚合物形成，所述聚合物可为例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等感光性材料。在其他实施例中，介电层132由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂有硼的磷硅酸盐玻璃；或类似材料。介电层132可通过旋转涂布、层叠、化学气相沉积、类似方法、或其组合来形成。
在图10中，接着对介电层132进行图案化。所述图案化会形成开口以暴露出穿孔(导通孔110)的一些部分、辐射天线108的一些部分、以及管芯连接件126的一些部分。可通过例如以下可接受的工艺来进行图案化：当介电层132是感光性材料时将介电层132暴露至光；或者使用例如各向异性刻蚀(anisotropic etch)进行刻蚀。如果介电层132是感光性材料，则可在曝光之后对介电层132进行显影。
在图11中，在介电层132上形成具有通孔的金属化图案138。作为形成金属化图案138的实例，在介电层132之上以及在穿过介电层132的开口中形成晶种层(图中未示出)。在一些实施例中，晶种层是金属层，所述金属层可为单个层或为包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可例如利用物理气相沉积等来形成所述晶种层。接着在晶种层上形成光刻胶并将所述光刻胶图案化。可通过旋转涂布或类似工艺来形成光刻胶且可将光刻胶暴露至光以进行图案化。光刻胶的图案对应于金属化图案138。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。导电材料可通过镀覆(例如，电镀或无电镀覆等)来形成。导电材料可包括金属，如铜、钛、钨、铝等。接着，移除光刻胶以及晶种层的上面未形成导电材料的部分。光刻胶可通过可接受的灰化工艺或剥除工艺来移除，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，便例如使用可接受的刻蚀工艺(例如，通过湿刻蚀或干刻蚀)来移除晶种层的暴露部分。晶种层的剩余部分与导电材料形成金属化图案138及通孔。通孔形成在穿过介电层132而到达例如穿孔(导通孔110)、辐射天线108、及/或管芯连接件126的开口中。
在图12中，在金属化图案138及介电层132上沉积介电层140。在一些实施例中，介电层140是由可使用光刻掩模进行图案化的聚合物形成，所述聚合物可为例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等感光性材料。在其他实施例中，介电层140由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂有硼的磷硅酸盐玻璃；或类似材料。介电层140可通过旋转涂布、层叠、化学气相沉积、类似方法或其组合来形成。
在图13中，接着对介电层140进行图案化。所述图案化会形成开口以暴露出金属化图案138的一些部分。可通过例如以下可接受的工艺来进行所述图案化：当介电层是感光性材料时将介电层140暴露至光，或者使用例如各向异性刻蚀进行刻蚀。如果介电层140是感光性材料，则可在曝光之后对介电层140进行显影。
在图14中，在介电层140上形成具有通孔的金属化图案146。作为形成金属化图案146的实例，在介电层140之上以及在穿过介电层140的开口中形成晶种层(图中未示出)。在一些实施例中，晶种层是金属层，所述金属层可为单个层或为包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积等来形成晶种层。接着在晶种层上形成光刻胶并将所述光刻胶图案化。可通过旋转涂布或类似工艺来形成光刻胶且可将光刻胶暴露至光以进行图案化。光刻胶的图案对应于金属化图案146。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。导电材料可通过镀覆(例如，电镀或无电镀覆等)来形成。导电材料可包括金属，如铜、钛、钨、铝等。接着，移除光刻胶以及晶种层的上面未形成导电材料的部分。光刻胶可通过可接受的灰化工艺或剥除工艺来移除，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，便例如使用可接受的刻蚀工艺(例如，通过湿刻蚀或干刻蚀)来移除晶种层的暴露部分。晶种层的剩余部分与导电材料形成金属化图案146及通孔。通孔形成在穿过介电层140而到达例如金属化图案138的一些部分的开口中。
在图15中，在金属化图案146及介电层140上沉积介电层148。在一些实施例中，介电层148是由可使用光刻掩模进行图案化的聚合物形成，所述聚合物可为例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等感光性材料。在其他实施例中，介电层148由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂有硼的磷硅酸盐玻璃；或类似材料。介电层148可通过旋转涂布、层叠、化学气相沉积、类似方法、或其组合来形成。
在图16中，接着对介电层148进行图案化。所述图案化会形成开口以暴露出金属化图案146的部分。可通过例如以下可接受的工艺来进行所述图案化：当介电层是感光性材料时将介电层148暴露至光，或者使用例如各向异性刻蚀进行刻蚀。如果介电层148是感光性材料，则可在曝光之后对介电层148进行显影。
在图17中，在介电层148上形成具有通孔的金属化图案154。作为形成金属化图案154的实例，在介电层148之上以及在穿过介电层148的开口中形成晶种层(图中未示出)。在一些实施例中，晶种层是金属层，所述金属层可为单个层或为包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积等来形成晶种层。接着在晶种层上形成光刻胶并将所述光刻胶图案化。可通过旋转涂布或类似工艺来形成光刻胶且可将光刻胶暴露至光以进行图案化。光刻胶的图案对应于金属化图案154。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。导电材料可通过镀覆(例如，电镀或无电镀覆等)来形成。导电材料可包括金属，如铜、钛、钨、铝等。接着，移除光刻胶以及晶种层的上面未形成导电材料的部分。光刻胶可通过可接受的灰化工艺或剥除工艺来移除，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，便例如使用可接受的刻蚀工艺(例如，通过湿刻蚀或干刻蚀)来移除晶种层的暴露部分。晶种层的剩余部分与导电材料形成金属化图案154及通孔。通孔形成在穿过介电层148而到达例如金属化图案146的一些部分的开口中。
在图18中，在金属化图案154及介电层148上沉积介电层156。在一些实施例中，介电层156是由可使用光刻掩模进行图案化的聚合物形成，所述聚合物可为例如聚苯并恶唑、聚酰亚胺、苯并环丁烯等感光性材料。在其他实施例中，介电层156由以下材料形成：氮化物，例如氮化硅；氧化物，例如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂有硼的磷硅酸盐玻璃；或类似材料。介电层156可通过旋转涂布、层叠、化学气相沉积、类似方法、或其组合来形成。
示出前侧重布线结构170作为实例。可在前侧重布线结构170中形成更多或更少的介电层及金属化图案。如果将形成更少的介电层及金属化图案，则可省略以上论述的步骤及工艺。如果将形成更多介电层及金属化图案，则可重复以上论述的步骤及工艺。所属领域中的普通技术人员将易于理解哪些步骤及工艺将被省略或重复进行。
在图19中，接着对介电层156进行图案化。所述图案化会形成开口以暴露出金属化图案154的一些部分。可通过例如以下可接受的工艺来进行所述图案化：当介电层是感光性材料时将介电层156暴露至光，或者使用例如各向异性刻蚀进行刻蚀。如果介电层156是感光性材料，则可在曝光之后对介电层156进行显影。
在图20中，在前侧重布线结构170的外侧上形成接垫162。接垫162用以耦合到导电连接件166(参见图21)，且可被称为凸块下金属(under bump metallurgy)。在所示实施例中，穿过开口形成接垫162，所述开口穿过介电层156而到达金属化图案154。作为形成接垫162的实例，在介电层156之上形成晶种层(图中未示出)。在一些实施例中，晶种层是金属层，所述金属层可为单一层或为包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积等来形成晶种层。接着在晶种层上形成光刻胶并将所述光刻胶图案化。可通过旋转涂布或类似工艺来形成光刻胶且可将光刻胶暴露至光以进行图案化。光刻胶的图案对应于接垫162。所述图案化会形成穿过光刻胶的开口以暴露出晶种层。在光刻胶的开口中以及在晶种层的暴露的部分上形成导电材料。导电材料可通过镀覆(例如，电镀或无电镀覆等)来形成。导电材料可包括金属，如铜、钛、钨、铝等。接着，移除光刻胶以及晶种层的上面未形成导电材料的部分。光刻胶可通过可接受的灰化工艺或剥除工艺来移除，例如使用氧等离子体或类似工艺等。一旦光刻胶被移除，便例如使用可接受的刻蚀工艺(例如，通过湿刻蚀或干刻蚀)来移除晶种层的暴露部分。晶种层的剩余部分及导电材料形成接垫162。在其中接垫162以不同的方式形成的实施例中，可使用更多的光刻胶及图案化步骤。
在图21中，在接垫(可被称为凸块下金属)162上形成导电连接件166。导电连接件166可为球栅阵列封装(ball grid array，BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlled collapse chip connection，C4)凸块、微凸块、无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块等。导电连接件166可包含导电材料，例如，焊料、铜、铝、金、镍、银、钯、锡、类似材料、或其组合。在一些实施例中，通过使用例如蒸镀(evaporation)、电镀、印刷、焊料转移(solder transfer)、植球(ball placement)或类似工艺等常用方法初始地形成焊料层来形成导电连接件166。一旦已在结构上形成焊料层，便可执行回焊(reflow)以将所述材料塑形成期望凸块形状。在另一实施例中，导电连接件166为通过溅镀、印刷、电镀、无电镀覆、化学气相沉积或类似工艺形成的金属柱(例如铜柱)。所述金属柱可不含有焊料且具有实质上垂直的侧壁。在一些实施例中，在金属柱连接件166的顶部上形成金属盖层(metal caplayer)(图中未示出)。金属盖层可包含镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金、类似材料、或其组合，且可通过镀覆工艺来形成。
在图22中，执行载体衬底剥离(carrier substrate de-bonding)以使载体衬底100从背侧重布线结构(例如，介电层104)分离(剥离)。根据一些实施例，所述剥离包括将例如激光或紫外光等光投射在释放层102上以使得释放层102在光的热量作用下分解，且可移除载体衬底100。接着将所述结构翻转并放置在胶带190上。
在图23中，在介电层104之上形成介电层200。在一些实施例中，介电层200包含耗散因数相对低的材料以实现具有适当效率的贴片式天线。举例来说，介电层200的耗散因数可小于约0.01或者在一些实施例中甚至小于约0.001。另外，介电层200的k值可为约3至约4。在实施例中，介电层200的厚度与贴片式天线210的工作频率相关。举例来说，介电层200的厚度可与贴片式天线210工作频率成反比。在实施例中，当贴片式天线210具有为至少60GHz的工作频率时，介电层200的厚度可处于约200μm至约300μm的范围中。介电层200可使用任何合适的工艺(例如，层叠)形成。在其他实施例中，也可使用其他沉积工艺(例如，物理气相沉积、化学气相沉积、旋涂技术等)。
在图24中，在介电层200之上形成贴片式天线的辐射元件204。在俯视图中(例如，参见图1C)，辐射元件204可具有矩形形状且与接地元件106A/馈电线106B交叠，但是在其他实施例中预期存在其他形状。辐射元件204可包含任意合适的导电材料(例如，铜)，但是在其他实施例中也可使用其他导电材料。辐射元件204可通过粘合剂202粘着在介电层200的表面上。在一些实施例中，粘合剂202可为环氧树脂，所述环氧树脂在粘着到介电层200上之前便被施加到辐射元件204。可接着将辐射元件204放置在介电层200上(例如，通过拾取及放置工具)，并将粘合剂202活化(例如，通过加热)以将辐射元件204粘合在介电层200上。在其他实施例中，不包含粘合剂202，且将辐射元件204直接粘着到介电层200。在其他实施例中，使用例如以下不同的方法在介电层200上形成辐射元件204：沉积晶种层；在晶种层之上形成图案化掩模以界定辐射元件204的图案；在图案化掩模的开口中对辐射元件进行镀覆；以及移除图案化掩模及晶种层的凹陷部分。也可对辐射元件204进行其他沉积工艺。在一实施例中，可于辐射元件204上方加上一层可见或不可见的介电层(此处，所述可见或不可见介电层根据其厚度与材料染色与否决定)，以防止辐射元件204的氧化。
辐射元件204电耦合到下伏的接地元件106A及馈电线106B以发射及接收无线信号。由此，形成贴片式天线210(包括接地元件106A、馈电线106B、介电层200的一些部分、及辐射元件204)。将贴片式天线210中的每一者集成在与集成电路管芯114及可选辐射天线108相同的半导体封装中。介电特征116将集成电路管芯114中的每一者从相应的贴片式天线210分离并有助于将集成电路管芯114中的每一者从相应的贴片式天线210隔离，以提高贴片式天线210的效率。
在形成辐射元件204之后，通过沿例如位于相邻的区600与区602之间的切割道区212进行锯切来执行单体化工艺。所述锯切将第一封装区600从第二封装区602单体化以形成半导体封装250。
图25示出在将半导体封装250安装到衬底400之后的半导体封装250。衬底400可被称为封装衬底400。使用导电连接件166将封装250安装到封装衬底400。
封装衬底400可由例如硅、锗、金刚石等半导体材料制成。作为另外一种选择，也可使用化合物材料，例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、其组合等。另外，封装衬底400可为绝缘体上半导体(semiconductor-on-insulator，SOI)衬底。一般来说，绝缘体上半导体衬底包括由例如以下半导体材料形成的层：外延硅、锗、硅锗、绝缘体上半导体、绝缘体上硅锗(silicon germanium-on-insulator，SGOI)、或其组合。在一个替代实施例中，封装衬底400是基于绝缘芯体，例如玻璃纤维加强型树脂芯体。一种示例性芯体材料是玻璃纤维树脂，例如FR4。芯体材料的替代形式包括双马来酰亚胺三嗪(BT)树脂，或作为另外一种选择，包括其他印刷电路板材料或膜。可对封装衬底400使用例如味之素构成膜(Ajinomoto build-up film，ABF)等构成膜或其他层叠体。
封装衬底400可包括有源装置及无源装置(图25中未示出)。所属领域中的普通技术人员应认识到，可使用各种各样的装置(例如，晶体管、电容器、电阻器、其组合等)来实现半导体封装500的设计的结构性及功能性要求。可利用任何适合的方法来形成所述装置。
封装衬底400也可包括金属化层及通孔(图中未示出)以及位于所述金属化层及通孔之上的结合接垫402。金属化层可形成在有源装置及无源装置之上且被设计成连接各种装置，以形成功能性电路系统。金属化层可利用对导电材料层进行内连的通孔而由交替的介电质(例如，低介电常数介电材料)层与导电材料(例如，铜)层形成，且可通过任何适合的工艺(例如，沉积、镶嵌(damascene)、双镶嵌(dual damascene)等)来形成。在一些实施例中，封装衬底400实质上不含有有源装置及无源装置。
在一些实施例中，可对导电连接件166进行回焊以将封装250贴合到结合接垫402。导电连接件166将衬底400(包括位于衬底400中的金属化层)电耦合及/或实体耦合至第一封装250。在一些实施例中，可在将无源装置(例如，表面安装装置(surface mountdevices，SMD)，图中未示出)安装到衬底400上之前，将无源装置贴合到封装250(例如，结合到接垫162)。在这些实施例中，可将无源装置结合到封装250的与导电连接件166所结合的表面相同的表面。
在导电连接件166被回焊之前，导电连接件166上可形成有环氧树脂焊剂(图中未示出)，在将封装250贴合到衬底400之后所述环氧树脂焊剂的至少一些环氧树脂部分会余留。这些余留的环氧树脂部分可充当底部填充剂，以减小由对导电连接件166进行回焊而引起的应力并保护因对导电连接件166进行回焊而产生的接缝。在一些实施例中，可在第一封装250与衬底400之间以及环绕导电连接件166来形成底部填充剂(图中未示出)。所述底部填充剂可在对封装250进行贴合之后通过毛细管流动工艺(capillary flow process)形成，或可在对封装250进行贴合之前通过合适的沉积方法形成。
已参照具体上下文，即在包括集成电路管芯114以及一个或多个集成天线(例如，贴片式天线210)的封装的上下文中，阐述了各种以上实施例。在集成电路管芯114与贴片式天线的接地特征及/或信号线(被称为馈电线)之间设置有介电特征116以减少干扰。然而，可对其他类型的封装应用各种实施例，所述其他类型的封装可包括或可不包括集成天线。
举例来说，图26A及图26B示出根据一些其他实施例的半导体封装500的各种图。图26A示出封装500的剖视图，而图26B示出封装500的俯视图。图26A/图26B所示封装500可实质上相似于图25所示封装500，其中相同的参考编号表示相同的元件。
然而，不同于图25所示的封装500，图26A/图26B所示的封装500不包括贴片式天线210。而是，图26A/图26B示出封装500包括共面波导(coplanar waveguide，CPW)510。共面波导510包括信号线502及接地线504。在一些实施例中，接地线504为信号线502提供屏蔽(例如，电磁屏蔽)。举例来说，在俯视图中，信号线502可设置在两条接地线504之间并被两条接地线504包夹(参见图26B)。接地线504可通过导通孔110而电连接到集成电路管芯114及重布线结构170的导电特征。在一些实施例中，信号线502是高频信号线，所述高频信号线电连接到集成电路管芯114以及重布线结构170的导电特征。在一些实施例中，信号线502通过导通孔110(图26A中未示出)而电连接到集成电路管芯114以及重布线结构170的导电特征，导通孔110可设置在与图26A不同的横截面中。
在俯视图中，共面波导510可与集成电路管芯114交叠。另外，共面波导510可通过介电特征116而从集成电路管芯114实体分离。介电特征116可有助于将共面波导510从由共面波导510与集成电路管芯114之间的交叠造成的干扰隔离。在一些实施例中，介电特征116的厚度是基于共面波导510的工作带宽、介电特征的k值、共面波导510的各种特征的面积、共面波导510的期望效率、其组合等来加以选择。
如图26A所示，封装500可还包括可选天线(例如，辐射天线108)。在其他实施例中，可不包含天线108。在一些实施例中，可将另一个封装组件600A结合到封装500的与衬底400相对的一侧。封装组件600A可为集成电路管芯或另一种封装(例如，包括经包封的集成电路管芯以及电路由(electrical routing))。举例来说，封装组件600A可为经封装存储器模块，例如，低功率双倍数据速率1(low-power double data rate 1，LPDDR1)存储器模块、低功率双倍数据速率2存储器模块、低功率双倍数据速率3存储器模块、低功率双倍数据速率4存储器模块等。预期也存在其他类型的封装组件600A。
可通过连接件602A(例如，与上述连接件166相似)将封装组件600A结合到封装500，连接件602A延伸穿过封装500的介电层512。介电层512可设置在封装500的与衬底400相对的外侧处。封装组件600A可通过导通孔110而电连接到共面波导510、集成电路管芯114、及重布线结构170的导电特征。在一些实施例中，封装组件600A也可电连接到可选天线108。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(threedimensional，3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫(test pad)，以允许对三维封装或三维集成电路进行测试、对探针及/或探针卡(probecard)进行使用等。可对中间结构以及最终结构执行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用，以提高良率并降低成本。
在各种实施例中，在俯视图中，装置(例如，贴片式天线或共面波导)的一些部分与至少一个半导体芯片交叠，且如果不能得到解决，则这种交叠可能会在装置中造成干扰并造成装置的效率降低。因此，各种实施例通过在半导体芯片与装置(例如，装置的信号线及接地元件)之间设置介电特征来提高装置的效率并减少来自半导体芯片的干扰。对介电特征的厚度加以选择以实现装置的期望效率。所述厚度可进一步对应于装置与半导体芯片之间的距离。举例来说，已观察到，相对厚的介电特征可在装置与半导体芯片之间提供改善的隔离。在一些实施例中，介电特征的厚度是基于装置的工作带宽、介电特征的k值、装置的各种特征的面积、装置的期望效率、其组合等来加以选择。
根据实施例，一种封装包括：集成电路管芯，包封在包封体中；装置，位于所述集成电路管芯之上；以及介电特征，设置在所述集成电路管芯与所述装置之间。所述装置在俯视图中与所述集成电路管芯交叠。所述装置包括信号线及接地元件。所述介电特征的厚度是根据所述装置的工作带宽。
在一些实施例中，所述介电特征的所述厚度进一步根据所述介电特征的k值、所述装置的面积、所述装置的效率、或其组合。
在一些实施例中，当所述装置的所述工作带宽为60gHz且所述介电特征的所述k值为至少3时，所述介电特征的所述厚度为至少100μm；当所述装置的所述工作带宽为60gHz且所述介电特征的所述k值小于3时，所述介电特征的所述厚度为至少30μm；当所述装置的所述工作带宽为77gHz且所述介电特征的所述k值为至少3时，所述介电特征的所述厚度为至少50μm；以及当所述装置的所述工作带宽为77gHz且所述介电特征的所述k值小于3时，所述介电特征的所述厚度为至少15μm
在一些实施例中，所述装置是贴片式天线，且其中所述贴片式天线包括辐射元件，所述辐射元件位于所述接地元件及所述信号线之上且电耦合到所述接地元件及所述信号线，其中在所述信号线与所述辐射元件之间设置有第一介电层。
在一些实施例中，所述介电特征将所述接地元件从所述集成电路管芯在实体上分离，且其中所述介电特征的所述厚度是作为所述接地元件与所述集成电路管芯之间的距离来测量。
在一些实施例中，所述接地元件及所述信号线设置在第二介电层中，且其中所述信号线设置在延伸穿过所述接地元件的开口中。
在一些实施例中，所述接地元件设置在第二介电层中，且其中所述信号线设置在位于所述第二介电层之上的第三介电层中。
在一些实施例中，所述装置是共面波导，且其中在俯视图中，所述信号线设置在所述接地元件与附加接地元件之间。
根据实施例，一种方法包括：将集成电路管芯包封在包封体中；以及在所述包封体中形成导通孔，并将所述集成电路管芯电连接到贴片式天线。所述贴片式天线包括：接地元件；馈电线；以及辐射元件，电耦合到所述接地元件及所述馈电线。所述方法还包括形成将所述接地元件从所述集成电路管芯在实体上分离的介电特征。所述介电特征的厚度是根据以下中的至少一者加以选择：所述贴片式天线的工作带宽，所述介电特征的k值，所述贴片式天线的面积，以及所述贴片式天线的效率。
在一些实施例中，所述介电特征包括第一介电层及第二介电层，其中所述第一介电层包含与所述第二介电层不同的材料。
在一些实施例中，所述介电特征还包括第三介电层，所述第三介电层包含与所述第一介电层及所述第二介电层中的至少一者不同的材料。
在一些实施例中，所述介电特征的侧壁与所述集成电路管芯的侧壁具有共同的末端。
在一些实施例中，所述介电特征具有与所述集成电路管芯不同的宽度。
在一些实施例中，还包括形成辐射天线，所述辐射天线延伸穿过所述包封体且电连接到所述集成电路管芯。
根据实施例，一种方法包括：在载体之上形成贴片式天线的接地元件及馈电线；以及使用介电特征将集成电路管芯贴合到所述贴片式天线的所述接地元件。所述介电特征的厚度是根据所述贴片式天线的工作带宽、所述介电特征的k值、所述贴片式天线的面积、所述贴片式天线的效率、或其组合来加以选择。所述方法还包括：形成电连接到所述接地元件及所述馈电线的导通孔；包封所述集成电路管芯及所述导通孔；使用重布线层将所述导通孔电连接到所述集成电路管芯。所述重布线层设置在所述集成电路管芯的与所述接地元件相对的侧上。所述方法还包括将所述贴片式天线的辐射元件电耦合到所述接地元件及所述馈电线。
在一些实施例中，还包括：移除所述载体；在移除所述载体后，在所述接地元件及所述馈电线之上形成介电层；以及在所述介电层之上形成所述辐射元件。
在一些实施例中，形成所述辐射元件包括将所述辐射元件粘着到所述介电层。
在一些实施例中，还包括：在形成所述导通孔的同时，形成邻近所述导通孔的辐射天线；将所述辐射天线与所述导电孔及所述集成电路管芯包封在一起；以及使用所述重布线层将所述辐射天线电连接到所述集成电路管芯。
在一些实施例中，形成所述接地元件及所述馈电线包括同时形成所述接地元件与所述馈电线。
在一些实施例中，形成所述接地元件及所述馈电线包括在不同的介电层中形成所述接地元件及所述馈电线。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，他们可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (1)

1.一种封装，其特征在于，包括：
集成电路管芯，包封在包封体中；
装置，位于所述集成电路管芯之上，其中所述装置在俯视图中与所述集成电路管芯交叠，且其中所述装置包括接地元件及信号线；以及
介电特征，设置在所述集成电路管芯与所述装置之间，其中所述介电特征的厚度是根据所述装置的工作带宽。
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