CN110010503B - 形成半导体器件的方法以及半导体器件 - Google Patents

形成半导体器件的方法以及半导体器件 Download PDF

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CN110010503B
CN110010503B CN201811487556.2A CN201811487556A CN110010503B CN 110010503 B CN110010503 B CN 110010503B CN 201811487556 A CN201811487556 A CN 201811487556A CN 110010503 B CN110010503 B CN 110010503B
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dielectric layer
antenna
device die
shielding structure
forming
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CN110010503A (zh
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吴凯强
余振华
杨青峰
陈孟泽
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

根据本发明的实施例，提供了一种形成半导体器件的方法，包括在第一介电层上方形成金属杆，在第一介电层上方附接第二介电层，将器件管芯、第二介电层、屏蔽结构和金属杆密封在密封材料中，平坦化密封材料以暴露器件管芯、屏蔽结构和金属杆，并且形成电连接至器件管芯的天线。天线具有与器件管芯的部分垂直对准的部分。根据本发明的实施例还提供了另一种形成半导体器件的方法以及一种半导体器件。

Description

形成半导体器件的方法以及半导体器件
技术领域
本发明涉及半导体领域，并且更具体地，涉及形成半导体器件的方法以及半导体器件。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，更多功能需要集成到半导体管芯中。因此，半导体管芯需要将越来越多的I/O焊盘封装至在较小的区域中，并且因此随着时间I/O焊盘的密度迅速提升。结果，半导体管芯的封装变得更加困难，这会对封装产量产生不利影响。
传统的封装技术可以划分为两类。在第一类中，在切割晶圆上的管芯之前将它们进行封装。这种封装技术具有诸如更大的生产量和更低的成本的一些有利特征。此外，需要较少的底部填充物或模塑料。然而，这种封装技术还具有缺陷。由于管芯的尺寸正变得越来越小，并且相应的封装件仅可以是扇入型封装件，其中，每个管芯的I/O焊盘限制于位于相应管芯的表面正上方的区域。由于管芯的有限面积，I/O焊盘的间距的限制，I/O焊盘的数量受到限制。如果焊盘的间距减小，则可能发生焊料桥接。此外，在固定的球尺寸的需求下，焊球必须具有特定的尺寸，这进而限制可以封装在管芯表面上的焊球的数量。
在另一类封装中，在封装管芯之前从晶圆上切割管芯。该封装技术的有利特征是形成扇出型封装件的可能性，这意味着管芯上的I/O焊盘可以分布至比管芯更大的区域，并且因此可以增加封装在管芯的表面上的I/O焊盘的数量。该封装技术的另一有利特征是封装“已知良好管芯”，以及丢弃缺陷管芯，并且因此不会在缺陷管芯上浪费成本和精力。
在扇出封装件中，将器件管芯封装在模塑料中，然后平坦化以暴露器件管芯。在器件管芯上方形成介电层。在介电层中形成再分布线以连接至器件管芯。扇出封装件还可以包括穿透模塑料的通孔。
发明内容
根据本发明的实施例，提供了一种形成半导体器件的方法，包括：在第一介电层上方形成金属杆；在所述第一介电层上方附接第二介电层；将器件管芯、所述第二介电层、屏蔽结构和所述金属杆密封在密封材料中；平坦化所述密封材料以暴露所述器件管芯、所述屏蔽结构和所述金属杆；以及形成电连接至所述器件管芯的第一天线，其中，所述第一天线具有与所述器件管芯的部分垂直对准的部分。
根据本发明的实施例，还提供了一种形成半导体器件的方法，包括：在所述载体上方形成第一介电层；将第二介电层附接至所述第一介电层；在所述第二介电层上方设置金属膜；在所述金属膜上方形成侧屏蔽结构；将器件管芯附接至所述金属膜，其中，所述器件管芯位于由所述侧屏蔽结构环绕的区域中；将所述器件管芯和所述侧屏蔽结构密封在密封材料中；以及形成第一天线，其中，所述第一天线和所述器件管芯位于所述第二介电层的相对侧上，并且所述第一天线电连接至所述器件管芯。
根据本发明的实施例，还提供了一种半导体器件，包括：器件管芯；屏蔽结构，密封在密封材料中，其中，所述器件管芯位于所述屏蔽结构中；贯通孔，穿过所述密封材料；以及天线，具有与所述屏蔽结构重叠的至少部分，其中，所述天线通过所述贯通孔电连接至所述器件管芯。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图14示出根据一些实施例的形成封装件的中间阶段的截面图。
图15至图18示出根据一些实施例的形成封装件的中间阶段的截面图。
图19和图20示出根据一些实施例的形成封装件的中间阶段的截面图。
图21和图22示出根据一些实施例的形成封装件的中间阶段的截面图。
图23示出根据一些实施例的封装件的顶视图。
图24A、图24B、图24C和图24D示出根据一些实施例的一些屏蔽结构的立体图。
图25至图28示出根据一些实施例的具有屏蔽结构的一些封装件的截面图。
图29示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例，提供了一种封装件及其形成方法。示出形成该封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图14示出根据一些实施例的形成封装件的中间阶段的截面图。图1至图14中示出的步骤还在图29所示的工艺流程200中示意性地示出。
图1示出载体20和设置在载体20上的释放膜22。载体20可以是玻璃载体、陶瓷载体等。载体20可具有圆形的顶视形状并且可具有硅晶圆的尺寸。释放膜22可以由聚合物基材料(诸如光热转换(LTHC)材料)形成，释放膜22可以与载体20一起从将在后续步骤中形成的上面的结构去除。根据本发明的一些实施例，释放膜22由环氧树脂基热释放材料形成。在其他实施例中，释放膜22由紫外(UV)胶形成。释放膜22可以以流动形式进行分配并且然后进行固化。释放膜22的顶面是平坦的并且具有高度共面性。
在释放膜22上形成介电缓冲层24。相应的工艺在图29所示的工艺流程中示出为工艺202。根据本发明的一些实施例，介电缓冲层24由诸如聚合物的有机材料形成，其还可以是诸如聚苯并恶唑(PBO)、聚酰亚胺等的光敏材料，其可以通过曝光并且显影进行图案化。根据本发明的一些可选实施例，介电缓冲层24由无机材料形成，其中，该无机材料可以是诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等。
参考图2，在介电缓冲层24上方形成导电部件26。相应的工艺在图29所示的工艺流程中示出为工艺204。导电部件26可以包括再分布线(RDL)26A和金属焊盘26B。一些金属焊盘26B可以用作贴片天线(patch antenna)。由于RDL 26A位于器件管芯52(图7)的背侧上，因此RDL 26A也称为背侧RDL。形成RDL 26A可以包括在介电缓冲层24上方形成金属晶种层(未示出)，在金属晶种层上方形成诸如光刻胶的图案化的掩模(未示出)，并且然后对暴露的晶种层实施金属镀。然后，去除图案化的掩模，接着去除先前被去除的图案化的掩模覆盖的晶种层，留下图2中的RDL26A。根据本发明的一些实施例，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理汽相沉积(PVD)形成晶种层。可以使用例如化学镀、电化学镀等来实施镀。
进一步参考图2，在导电部件26上形成介电层28。相应的工艺在图29所示的工艺流程中示出为工艺206。介电层28的底面与导电部件26和介电缓冲层24的顶面接触。根据本发明的一些实施例，介电层28由诸如聚合物的有机材料形成，其中，其可以是诸如PBO、聚酰亚胺等的光敏聚合物。根据本发明的可选实施例，介电层28由无机材料形成，其中，其可以是诸如氮化硅的氮化物，诸如氧化硅的氧化物、PSG、BSG、BPSG等。然后图案化介电层28以在介电层28中形成开口30。因此，通过介电层28中的开口30暴露导电部件26的一些部分。
图3示出放置用于隔离电磁干扰(EMI)的介电层32和34，这将在后续的段落中讨论。相应的工艺在图29所示的工艺流程中示出为工艺208。根据本发明的一些实施例，介电层32由粘合剂形成，其中，该粘合剂可以是也可用于粘附器件管芯的管芯附接膜(DAF)。在介电层32是粘合膜的情况下，介电层32能够粘附至介电层28。选择介电层32的厚度T1，从而使得后续形成的贴片天线与器件管芯之间的EMI降低到可接受的水平。厚度T1也可以与介电层32的介电常数(k值)相关，并且较大的k值，较大的厚度T2是优选的。例如，当介电层32的k值为约3或更大并且贴片天线具有约60GHz的操作频率时，介电层32的厚度T1可以大于约100μm。作为另一实例，当介电层32的k值小于3(例如，约1)并且贴片天线具有约60GHz的操作频率时，介电层32的厚度T1可以大于约30μm。
在介电层32上方可以存在介电缓冲层34。介电缓冲层34可以由聚酰亚胺、PBO等的有机材料(诸如聚合物)或诸如氧化物、氮化物等的无机材料形成。应当理解，介电缓冲层34也具有隔离EMI的功能。先前讨论的介电层32的厚度T1是基于介电层34更薄(例如，厚度T2小于厚度T1的约10％)的假设。
根据本发明的一些实施例，在介电层34(当其预先形成时)上放置导电膜(其也称为箔或板)36。相应的工艺还在图29所示的工艺流程中示出为工艺208。也可以在介电层34上沉积导电膜36。导电膜可以是由铜、钛、镍或它们的多层形成的金属膜。根据本发明的一些实施例，介电层32和34以及导电膜36预先形成为单元，并且在介电层28上放置该单元。根据可选实施例，预先形成介电层32和34并且然后将其放置在介电层28上方，接着例如，通过诸如物理汽相沉积(PVD)、化学汽相沉积(CVD)等的沉积工艺形成导电膜36，并且接着进行图案化步骤。在顶视图中，导电膜36可以是没有位于其中的开口的实心板、具有位于其中的开口的网格(栅格)以暴露下面的介电层34，或多个互连或离散的平行条。
图4至图7示出形成侧屏蔽结构38、导电杆40以及可选的天线42(图6)。在整个描述中，由于金属杆将穿过后续分配的密封材料，所以金属杆40可选地称为贯通孔40。参考图4，例如通过PVD将金属晶种层44形成为毯式层。金属晶种层44的部分与金属膜36重叠。根据一些实施例，金属晶种层44可以包括铜或可以包括钛层和位于钛层上方的铜层。在金属晶种层44上方形成光刻胶46。相应的工艺在图29所示的工艺流程中示出为工艺210。根据本发明的一些实施例，光刻胶46是层压在金属晶种层44上的干膜。根据本发明的可选实施例，通过旋涂分配光刻胶46。
然后使用光刻掩模(未示出)对光刻胶46实施曝光，该光刻掩模包括允许光穿过的透明部分和阻挡光的不透明部分。在显影曝光的光刻胶46之后，在光刻胶46中形成开口48。金属晶种层44因此具有暴露于开口48的一些部分。
接下来，如图5所示，通过诸如化学镀工艺或电化学镀工艺的镀工艺形成侧屏蔽结构38、导电杆40和天线42(图7)。相应的工艺在图29所示的工艺流程中示出为工艺212。在后续步骤中，去除光刻胶46，并且因此暴露下面的金属晶种层44的部分。然后，在蚀刻步骤中去除金属晶种层44的暴露部分。相应的工艺在图29所示的工艺流程中示出为工艺214。在
图6中示出所得到的侧屏蔽结构38、导电杆40和天线42。由于金属膜36(图3)比晶种层更厚，并且还因为金属膜36可以由与金属晶种层44的底层不同的材料形成，所以在去除金属晶种层44之后保留金属膜36。在整个描述中，金属晶种层44的剩余部分也认为是相应的侧屏蔽结构38、导电杆40和天线42的部分。上述工艺还形成延伸到介电层28中以将导电杆40电连接至导电部件26的通孔50。
当从图6所示结构的顶部观察时，侧屏蔽结构38可以具有从多个候选形状中选择的形状。例如，侧屏蔽结构38可以包括多个离散杆(类似于图24A和图24B中所示出的)，其底部接触导电膜36的顶面。多个离散杆紧密定位，其间的距离足够小以阻挡电磁信号，并且多个离散杆与环对准。离散杆可以具有圆形、矩形、六边形、椭圆形、细长条等的顶视形状。侧屏蔽结构38可以可选地具有完整环(其中没有中断)的顶视形状。可以形成天线42，并分配为一个或多个组。根据本发明的一些实施例，每个组包括两个L形部分，其中，两个L形部分的底腿位于两个L形部分的两个垂直部分之间。
图7示出放置器件管芯52。相应的工艺在图29所示的工艺流程中示出为工艺216。器件管芯52通过管芯附接膜(DAF)54粘附至介电层28，其中，DAF 54是粘合膜。为了形成DAF54和附接的器件管芯52，可以将DAF 54预先附接至器件管芯52所在的晶圆，并且然后从晶圆切割DAF 54和晶圆。因此，器件管芯52的边缘与DAF 54的相应边缘齐平。器件管芯52可以是配置为产生和/或接收RF信号的RF管芯。器件管芯52还可以是包括位于其中的逻辑晶体管的逻辑器件管芯。器件管芯52还可以是基带(BB)管芯。
根据本发明的一些实施例，预先形成金属柱56(诸如铜杆)或金属焊盘作为器件管芯52的顶部，以及金属柱56电连接至诸如器件管芯52中的晶体管的集成电路器件(未示出)。根据本发明的一些实施例，诸如聚合物的介电材料填充相邻的金属柱56之间的间隙以形成顶部介电层58。根据一些实施例，介电层58可以由聚酰亚胺或PBO形成。根据本发明的一些实施例，在放置器件管芯52时，介电层58的顶面高于或共面于金属柱56的顶面。
接下来，也如图7所示，密封材料(密封剂)60密封在器件管芯52、侧屏蔽结构38、导电杆40和天线42上。相应的工艺还在图29所示的工艺流程中示出为工艺216。密封材料60填充侧屏蔽结构38、贯通孔40、器件管芯52和天线42之间的间隙。密封材料60可以包括模塑料、模制底部填充物、环氧树脂或树脂。根据本发明的一些实施例，密封材料60包括基材和基材中的填料颗粒。基材可以是环氧树脂、树脂、聚合物等。填料颗粒可以是二氧化硅、氧化铝等的球形颗粒。密封材料60也可以是均质材料，这意味着密封材料60的每个部分的材料与其他部分相同。例如，密封材料60的整体可以是包括相同基材和相同填料颗粒的模塑料。此外，侧屏蔽结构38内部的密封材料60的部分与侧屏蔽结构38外部的密封材料60的部分相同。
还参考图7，实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以削薄密封材料60，直到暴露金属柱56、侧屏蔽结构38、导电杆40和天线42。相应的工艺还在图29所示的工艺流程中示出为工艺216。由于平坦化，金属柱56的顶端与侧屏蔽结构38、导电杆40和天线42的顶面大致齐平(共面)，并且与密封材料60的顶面大致共面。在整个描述中，由于导电杆40穿过密封材料60，所以导电杆40可选地称为贯通孔40。
图8至图12示出形成前侧RDL和导电连接件。相应的工艺在图29所示的工艺流程中示出为工艺218。参考图8，形成介电层62。根据本发明的一些实施例，介电层62由诸如PBO、聚酰亚胺等聚合物的有机材料形成。根据本发明的可选实施例，介电层62由诸如氮化硅、氧化硅等的无机材料形成。开口64形成在介电层62中以暴露侧屏蔽结构38、贯通孔40、天线42和金属柱56。形成开口64可以包括光刻工艺，其中，该光刻工艺包括曝光并且然后显影介电层62。
接下来，参考图9，RDL 66形成为连接(并且还可以互连)金属柱56、侧屏蔽结构38、贯通孔40、天线42。RDL 66包括位于介电层62上方的金属迹线(金属线)以及延伸到位于介电层62中的开口中的通孔。形成RDL66可以包括镀工艺，其中，每个RDL 66均包括晶种层(未示出)和位于晶种层上方的镀的金属材料。晶种层和镀的材料可以由相同材料或不同材料形成。RDL 66可以包括具有铝、铜、钨和它们的合金的金属或金属合金。
参考图10，在RDL 66和介电层62上方形成介电层68、RDL 70和介电层72。可以使用从与介电层62的材料相同的候选材料中选择的材料形成介电层68。例如，介电层68可以包括PBO、聚酰亚胺等。可选地，介电层68可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等的非有机介电材料。
RDL 70电连接至RDL 66。形成RDL 70可采用与形成RDL 66的方法和材料类似的方法和材料。由于RDL 70和66都位于器件管芯52的前侧上，所以RDL 70和66还称为前侧RDL。虚线71示出为表示位于侧屏蔽结构38的部分与RDL 70中的一个之间的电连接。虚线表示电连接不在所示的平面中。还如图10所示，形成额外的介电层72以覆盖RDL 70和介电层68。介电层72可以由从用于形成介电层62和68的相同候选材料中选择的材料形成。
图11和图12示出根据一些实施例的形成凸块下金属(UBM)74(图11)并且形成电连接件76(图12)。形成UBM 74可以包括图案化介电层72以形成开口，以及沉积并图案化诸如钛层和位于钛层上方的铜层的金属层。电连接件76的形成可以包括在UBM 74的暴露部分上放置焊球，并且然后回流该焊球。根据本发明的可选的实施例，形成电连接件76包括实施镀步骤以在RDL 70上方形成焊料区并且然后回流焊料区。电连接件76还可包括金属柱和位于金属柱上的可选的焊料帽，其还可以通过镀形成。在整个描述中，包括介电层24和上面的结构的组合结构将称为封装件100，其可以是具有圆形的顶视形状的复合晶圆。根据一些实施例，复合晶圆100包括彼此相同的多个组件，图12中示出每个组件。
接下来，从载体20卸下封装件100。相应的工艺在图29所示的工艺流程中示出为工艺220。在卸下时，带78(图13)可以粘附至电连接件76上。在后续的步骤中，诸如UV光或激光束的辐射投射在释放膜22上以分解释放膜22，并且从封装件100卸下载体20。
接下来，如图13所示，在介电缓冲层24上方形成介电层77。相应的工艺在图29所示的工艺流程中示出为工艺222。根据本发明的一些实施例，介电层77由模塑料形成，并且通过分配并且然后固化模塑料而形成。模塑料77还可以包括基材(诸如树脂或聚合物)以及基材中的球形颗粒。介电层77也可以由诸如氧化物、氮化物、碳化物等的无机材料的其他介电材料形成。可以实施平坦化工艺以平坦化介电层77的顶面。
在介电层77上方形成贴片天线79。相应的工艺还在图29所示的工艺流程中示出为工艺222。根据本发明的一些实施例，贴片天线79由铜、铝、钨、镍、银、金、它们的合金和/或它们的多层的金属形成。贴片天线79是电悬置的，并且与下面的贴片天线26B重叠。
实施切割(管芯锯切)步骤以将封装件100锯切成多个封装件，每个封装件与图13中所示的类似。相应的工艺在图29所示的工艺流程中示出为工艺224。所得的封装件中的一个示出为图14中的封装件80。
图14示出封装件80与封装组件82的接合。相应的工艺在图29所示的工艺流程中示出为工艺226。根据本发明的一些实施例，通过电连接件76实施接合，其中，电连接件76可以包括接合至封装组件82中的导电部件84的焊料区。根据本发明的一些实施例，封装组件82是封装衬底，其可以是无芯衬底或具有芯(诸如玻璃纤维增强芯)的衬底。根据本发明的其他实施例，封装组件82是印刷电路板或封装件。可以在封装件80和封装组件82之间设置底部填充物88。在下文中可以将图14中的封装件称为封装件86。
如图14所示，贴片天线26B和贴片天线79形成堆叠的贴片天线，其以信号的形式连接至器件管芯52。可以在位于器件管芯52下面的RDL中形成接地面板(未示出)。接地面板可以位于互连器件管芯52和堆叠的贴片天线的馈线下方。贴片天线79与贴片天线26B重叠并且通过电磁场连接至贴片天线26B。在整个描述中，将金属膜36和侧屏蔽结构38组合称为屏蔽结构90，其中，金属膜36形成屏蔽结构90的帽，并且侧屏蔽结构38形成屏蔽结构90的裙部。屏蔽结构90通过RDL 66、70和电结构76电接地，并且因此具有屏蔽器件管芯52以免受堆叠的贴片天线的EMI的作用。一些接地路径由虚线71表示。根据本发明的一些实施例，侧屏蔽结构38包括多个金属杆，并且多个金属杆中的每个可以单独电接地以实现更好的屏蔽效果。
在图14中，贴片天线26B和79具有与器件管芯52的一些部分重叠的部分。因此，封装件86占据的面积减小。该重叠可能导致器件管芯52和贴片天线26B和79之间的EMI恶化。根据本发明的一些实施例，通过形成屏蔽结构90并且在屏蔽结构90和贴片天线26B和79之间插入介电层32和34(具有足够的厚度)来减少EMI问题。
图23示出封装件86的部分的顶视图。屏蔽结构90包括裙部38，其形成环绕器件管芯52和介电层32和34的环。密封材料60将屏蔽结构90密封在其中。密封材料60包括环绕屏蔽结构90的外部部分和由屏蔽结构90的裙部38环绕的内部部分。
图15至图22示出根据本发明的一些实施例的形成封装件的中间阶段的截面图。除非另有声明，这些实施例中的组件的材料和形成方法与相同的组件大致相同，相同的组件由图1至图14中所示实施例中的相同的参考标号表示。因此，可以在图1至图14所示实施例的讨论中找到关于图15至图22中所示组件的形成工艺和材料的细节。
图15至图18示出根据本发明的一些实施例的形成封装件的中间阶段的截面图。除了不同地形成侧屏蔽结构38之外，这些实施例类似于图1至图14中所示的实施例。当侧屏蔽结构38和贯通孔40之间的高度差大于工艺裕度时，可以采用这些实施例，并且因此不能同时镀侧屏蔽结构38和贯通孔40。除了不在图15所示的结构中形成图7所示的侧屏蔽结构38之外，这些实施例的初始步骤与图1至图7所示的大致相同以形成图15所示的结构。接下来，如图16所示，在密封材料60中形成开口94以查看金属膜36的一些部分。例如，可以通过激光钻孔或蚀刻形成开口94。当通过激光钻孔形成时，开口94可具有比相应的底部宽度更大的顶部宽度。
接下来，如图17所示，将导电膏填充到开口94(图16)中，并且然后固化以形成侧屏蔽结构38。例如，可以通过模板印刷来实现填充。导电膏可以包括铜膏、银膏等。后续步骤与参考图8至图14示出和讨论的步骤大致相同，并且在此不再重复细节。图18示出所得到的封装件86。
图19和图20示出根据本发明的一些实施例的形成封装件的中间阶段的截面图。除了屏蔽结构90预先形成为集成单元之外，这些实施例类似于图1至图14所示的实施例。除了在形成贯通孔40和天线42时，不形成侧屏蔽结构(图7)之外，这些实施例的初始步骤与图1至图7所示的大致相同以形成图19所示的结构。
根据本发明的一些实施例，如图19所示，预先形成屏蔽结构90，并且然后附接至介电层32和34。然后将器件管芯52附接至屏蔽结构90。组件32、34、90和52因此组合形成离散单元。然后将离散单元放置在介电层28上。根据本发明的可选实施例，首先将介电层32和34放置在介电层28上，并且然后将器件管芯52放置在屏蔽结构90内并且附接至屏蔽结构90。根据这些实施例的屏蔽结构90可以具有盆的形状，其中，裙部38和帽36由相同的材料形成，并且作为在其之间没有可区分的界面的整体件。后续步骤可以与参考图8至图14示出和讨论的步骤大致相同，并且在此不再重复细节。图20示出所得到的封装件86。
图21和图22示出根据本发明的一些实施例的形成封装件的中间阶段的截面图。这些实施例类似于图1至图14所示的实施例，除了通过喷射导电膏(诸如铜膏或银膏)或者通过溅射工艺在器件管芯52上预先形成屏蔽结构90之外。DAF 54可以存在或可以省略，从而使得导电膏接触器件管芯52的底面。除了在形成贯通孔40和天线42时，不形成侧屏蔽结构38(图7)之外，这些实施例的初始步骤与图1至图7中所示的大致相同以形成图21所示的结构。
根据本发明的一些实施例，如图21所示，器件管芯52和预先形成的屏蔽结构90附接至介电层32和34以形成离散单元。然后将离散单元放置在介电层28上。后续步骤与参考图8至图14示出和讨论的步骤大致相同，并且在此不再重复细节。图22示出所得到的封装件86。
图24A、图24B、图24C和图24D示出根据本发明的一些实施例的一些屏蔽结构90的立体图。只要适用，这些实施例可用于图14、图18、图20和图22中所示的结构中。参考图24A，屏蔽结构90的帽36包括多个彼此分离的离散金属条。侧屏蔽结构38包括连接至离散条的多个金属杆。每个金属杆可以单独地电接地。相邻金属杆之间的距离D1很小以实现有效的EMI隔离，例如，其中，距离D1小于由贴片天线发射或接收的RF信号的波长的约5％。器件管芯52位于由侧屏蔽结构38中的金属杆形成的环中。
图24B示出与图24A所示的屏蔽结构90类似的屏蔽结构90，除了帽36是实心板之外。根据可选实施例(未示出)，帽36可以是网状物(网格)，其中，贯通孔穿过帽36。图24C示出帽36是实心板，并且侧屏蔽结构38是实心壁，其可以完全环绕器件管芯52。图24D示出帽38包括离散条，而侧屏蔽结构38是实心环。可以预先形成如图24B、图24C和图24D所示的屏蔽结构90，并且然后如图19所示附接。
图25至图28示出包括屏蔽结构的多个封装件92。应当理解，只要适用，图25至图28的实施例中的屏蔽可以采用如图1至图24A、图24B、图24C和图24D所示的结构和形成方法。图25示出根据本发明的一些实施例的封装件，其中，封装件包括两个屏蔽结构90，每个屏蔽结构都具有位于其中的器件管芯(52A和52B)。器件管芯52A和52B两者可以是RF管芯。封装件可以包括或可以不具有天线26B和79，并且侧屏蔽结构90用于减少/消除器件管芯52A和52B之间的干扰以及器件管芯52A和52B与天线26B和79(如果形成的话)之间的干扰。
图26示出根据本发明的一些实施例的封装件92，其中，侧屏蔽结构90环绕位于其中的器件管芯52，其中，器件管芯52可以是RF器件管芯或基带管芯。也在封装件中放置器件管芯53，其中，不通过任何屏蔽结构环绕或覆盖器件管芯53。器件管芯53可以是逻辑管芯。封装件可以包括或可以不具有天线，并且屏蔽结构90用于消除管芯之间以及管芯和天线(如果形成的话)之间的干扰。
图27示出根据本发明的一些实施例的封装件92，其中，封装件包括其中放置有逻辑器件管芯52的屏蔽结构90。该封装件没有内置天线。根据本发明的一些实施例，贯通孔40连接至背侧RDL 26。封装件98通过焊料区106接合至下面的封装件86。封装件98可以包括位于其中的器件管芯104，例如，器件管芯104可以是存储器管芯。图28类似于图26，除了将介电块108密封在密封材料60中。介电块128可以具有低的热膨胀系数(CTE)，并且因此可以减小封装件92的翘曲。例如，介电块128的CTE可以低于约5ppm/℃。
在上述实施例中，根据本发明的一些实施例讨论了一些工艺和部件。也可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的允许使用探针和/或探针卡等测试3D封装件或3DIC的测试焊盘。可以对中间结构以及最终结构实施验证测试。额外地，本文公开的结构和方法可以与测试方法结合使用，该测试方法结合了已知良好管芯的中间验证以增加产量并降低成本。
本发明的实施例具有一些有利特征。通过形成导电屏蔽结构来屏蔽器件管芯，并进一步通过添加介电层来隔离EMI，降低了器件管芯和天线之间的EMI。
根据本发明的一些实施例，一种方法包括：在第一介电层上方形成金属杆；在第一介电层上方附接第二介电层；将器件管芯、第二介电层、屏蔽结构和金属杆密封在密封材料中；平坦化密封材料以暴露器件管芯、屏蔽结构和金属杆；以及形成电连接至器件管芯的第一天线，其中，第一天线具有与器件管芯的部分垂直对准的部分。根据一些实施例，该方法还包括形成屏蔽结构包括：在第二介电层上方附接金属膜；以及在金属膜上方形成侧屏蔽结构，其中，侧屏蔽结构和金属膜结合形成屏蔽结构。根据一些实施例，该方法还包括形成屏蔽结构包括：在第二介电层上方附接金属膜；在密封之后，在密封材料中形成开口以暴露金属膜的部分；以及将导电膏填充到开口中以在金属膜上方形成侧屏蔽结构，其中，侧屏蔽结构与金属膜组合形成屏蔽结构。根据一些实施例，该方法还包括预先形成屏蔽结构；将器件管芯附接至屏蔽结构；以及将预先形成的屏蔽结构和器件管芯作为集成单元附接在第二介电层上方。根据一些实施例，该方法还包括将导电膏喷射到器件管芯的表面和侧壁上以形成屏蔽结构；以及将屏蔽结构和器件管芯作为集成单元附接在第二介电层上方。根据一些实施例，该方法还包括形成第三介电层，其中第三介电层和器件管芯位于第二介电层的相对侧上；以及在第三介电层上形成第二天线，其中，第二天线从第一天线电去耦，并且配置为通过电磁场以信号方式连接至第一天线，以及第一天线和第二天线组合形成堆叠的贴片天线。根据一些实施例，该方法还包括使屏蔽结构电接地。
根据本发明的一些实施例，一种方法包括：在载体上方形成第一介电层；将第二介电层附接至第一介电层；在第二介电层上方设置金属膜；在金属膜上方形成侧屏蔽结构；将器件管芯附接至金属膜，其中，器件管芯位于由侧屏蔽结构围绕的区域中；将器件管芯和侧屏蔽结构密封在密封材料中；以及形成第一天线，其中，第一天线和器件管芯位于第二介电层的相对侧上，并且第一天线电连接至器件管芯。根据一些实施例，该方法还包括形成多个再分布线，其中，通过多个再分布线进一步互连第一天线和器件管芯。根据一些实施例，该方法还包括形成金属杆，其中，密封材料密封金属杆，并且通过金属杆进一步互连第一天线和器件管芯。根据一些实施例，金属杆和侧屏蔽结构形成为共享共同的镀工艺。根据一些实施例，形成侧屏蔽结构包括：在第一介电层、第二介电层和金属膜上方沉积金属晶种层，其中，从金属晶种层开始形成侧屏蔽结构；以及去除金属晶种层的部分，其中，金属晶种层的剩余部分成为侧屏蔽结构的部分。根据一些实施例，第一天线的部分与器件管芯的部分垂直对准。根据一些实施例，该方法还包括形成第三介电层，其中，第三介电层和器件管芯位于第二介电层的相对侧上；以及在第三介电层上形成第二天线，其中，第二天线从第一天线电去耦，并且第一天线和第二天线组合形成堆叠的贴片天线。
根据本发明的一些实施例，一种器件包括器件管芯；密封在密封材料中的屏蔽结构，其中，器件管芯位于屏蔽结构中；穿过密封材料的贯通孔；以及具有与屏蔽结构重叠的至少部分的天线，其中，天线通过贯通孔电连接至器件管芯。根据一些实施例，屏蔽结构包括导电帽；以及连接至导电帽的侧屏蔽结构，其中，侧屏蔽结构形成环绕器件管芯的环。根据一些实施例，该器件还包括密封材料，其中，在密封材料中密封器件管芯和屏蔽结构两者，并且导电帽的边缘与密封材料接触以形成界面。根据一些实施例，该器件进一步包括管芯附接膜，其中，器件管芯通过管芯附接膜附接至导电帽的表面。根据一些实施例，导电帽和侧屏蔽结构之间具有可区分的界面。根据一些实施例，屏蔽结构是没有位于其中的可区分界面的集成单元。
根据本发明的实施例，提供了一种形成半导体器件的方法，包括：在第一介电层上方形成金属杆；在所述第一介电层上方附接第二介电层；将器件管芯、所述第二介电层、屏蔽结构和所述金属杆密封在密封材料中；平坦化所述密封材料以暴露所述器件管芯、所述屏蔽结构和所述金属杆；以及形成电连接至所述器件管芯的第一天线，其中，所述第一天线具有与所述器件管芯的部分垂直对准的部分。
根据本发明的实施例，还包括形成所述屏蔽结构，包括：在所述第二介电层上方附接金属膜；以及在所述金属膜上方形成侧屏蔽结构，其中，所述侧屏蔽结构和所述金属膜组合形成所述屏蔽结构。
根据本发明的实施例，还包括形成所述屏蔽结构，包括：在所述第二介电层上方附接金属膜；在所述密封之后，在所述密封材料中形成开口以暴露所述金属膜的部分；以及将导电膏填充到所述开口中以在所述金属膜上方形成侧屏蔽结构，其中，所述侧屏蔽结构与所述金属膜组合形成所述屏蔽结构。
根据本发明的实施例，还包括：预先形成所述屏蔽结构；将所述器件管芯附接至所述屏蔽结构；以及将预先形成的所述屏蔽结构和所述器件管芯作为集成单元附接在所述第二介电层上方。
根据本发明的实施例，还包括：将导电膏喷射到所述器件管芯的表面和侧壁上以形成所述屏蔽结构；以及将所述屏蔽结构和所述器件管芯作为集成单元附接在所述第二介电层上方。
根据本发明的实施例，还包括：形成第三介电层，其中，所述第三介电层和所述器件管芯位于所述第二介电层的相对侧上；以及在所述第三介电层上形成第二天线，其中，所述第二天线从所述第一天线电去耦，并且配置为通过电磁场以信号方式连接至所述第一天线，并且所述第一天线和所述第二天线组合形成堆叠的贴片天线。
根据本发明的实施例，还包括使所述屏蔽结构电接地。
根据本发明的实施例，还提供了一种形成半导体器件的方法，包括：在所述载体上方形成第一介电层；将第二介电层附接至所述第一介电层；在所述第二介电层上方设置金属膜；在所述金属膜上方形成侧屏蔽结构；将器件管芯附接至所述金属膜，其中，所述器件管芯位于由所述侧屏蔽结构环绕的区域中；将所述器件管芯和所述侧屏蔽结构密封在密封材料中；以及形成第一天线，其中，所述第一天线和所述器件管芯位于所述第二介电层的相对侧上，并且所述第一天线电连接至所述器件管芯。
根据本发明的实施例，还包括形成多条再分布线，其中，通过所述多条再分布线进一步互连所述第一天线和所述器件管芯。
根据本发明的实施例，还包括形成金属杆，其中，所述密封材料密封所述金属杆，并且通过所述金属杆进一步互连所述第一天线和所述器件管芯。
根据本发明的实施例，所述金属杆和所述侧屏蔽结构形成为共享共同的镀工艺。
根据本发明的实施例，形成所述侧屏蔽结构包括：在所述第一介电层、所述第二介电层和所述金属膜上方沉积金属晶种层，其中，从所述金属晶种层开始形成所述侧屏蔽结构；以及去除所述金属晶种层的部分，其中，所述金属晶种层的剩余部分成为所述侧屏蔽结构的部分。
根据本发明的实施例，所述第一天线的部分与所述器件管芯的部分垂直对准。
根据本发明的实施例，还包括：形成第三介电层，其中，所述第三介电层和所述器件管芯位于所述第二介电层的相对侧上；以及在所述第三介电层上形成第二天线，其中，所述第二天线从所述第一天线电去耦，并且所述第一天线和所述第二天线组合形成堆叠的贴片天线。
根据本发明的实施例，还提供了一种半导体器件，包括：器件管芯；屏蔽结构，密封在密封材料中，其中，所述器件管芯位于所述屏蔽结构中；贯通孔，穿过所述密封材料；以及天线，具有与所述屏蔽结构重叠的至少部分，其中，所述天线通过所述贯通孔电连接至所述器件管芯。
根据本发明的实施例，所述屏蔽结构包括：导电帽；以及侧屏蔽结构，连接至所述导电帽，其中，所述侧屏蔽结构形成环绕所述器件管芯的环。
根据本发明的实施例，还包括密封材料，其中，在所述密封材料中密封所述器件管芯和所述屏蔽结构两者，并且所述导电帽的边缘与所述密封材料接触以形成界面。
根据本发明的实施例，还包括管芯附接膜，其中，所述器件管芯通过所述管芯附接膜附接至所述导电帽的表面。
根据本发明的实施例，所述导电帽和所述侧屏蔽结构之间具有可区分的界面。
根据本发明的实施例，所述屏蔽结构是没有位于其中的可区分界面的集成单元。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，包括：
在第一介电层上方形成金属杆；
在所述第一介电层上方附接第二介电层；
将器件管芯、所述第二介电层、屏蔽结构和所述金属杆密封在密封材料中，其中，所述器件管芯位于所述屏蔽结构中，并且其中所述器件管芯和所述屏蔽结构在所述第二介电层的上面；
平坦化所述密封材料以暴露所述器件管芯、所述屏蔽结构和所述金属杆；以及
形成电连接至所述器件管芯的第一天线，其中，所述第一天线具有与所述器件管芯的部分垂直对准的部分，并且所述第一天线和所述器件管芯位于所述第二介电层的相对侧上。
2.根据权利要求1所述的方法，还包括形成所述屏蔽结构，包括：
在所述第二介电层上方附接金属膜；以及
在所述金属膜上方形成侧屏蔽结构，其中，所述侧屏蔽结构和所述金属膜组合形成所述屏蔽结构。
3.根据权利要求1所述的方法，还包括形成所述屏蔽结构，包括：
在所述第二介电层上方附接金属膜；
在所述密封之后，在所述密封材料中形成开口以暴露所述金属膜的部分；以及
将导电膏填充到所述开口中以在所述金属膜上方形成侧屏蔽结构，其中，所述侧屏蔽结构与所述金属膜组合形成所述屏蔽结构。
4.根据权利要求1所述的方法，还包括：
预先形成所述屏蔽结构；
将所述器件管芯附接至所述屏蔽结构；以及
将预先形成的所述屏蔽结构和所述器件管芯作为集成单元附接在所述第二介电层上方。
5.根据权利要求1所述的方法，还包括：
将导电膏喷射到所述器件管芯的表面和侧壁上以形成所述屏蔽结构；以及
将所述屏蔽结构和所述器件管芯作为集成单元附接在所述第二介电层上方。
6.根据权利要求1所述的方法，还包括：
形成第三介电层，其中，所述第三介电层和所述器件管芯位于所述第二介电层的相对侧上；以及
在所述第三介电层上形成第二天线，其中，所述第二天线从所述第一天线电去耦，并且配置为通过电磁场以信号方式连接至所述第一天线，并且所述第一天线和所述第二天线组合形成堆叠的贴片天线。
7.根据权利要求1所述的方法，还包括使所述屏蔽结构电接地。
8.一种形成半导体器件的方法，包括：
在载体上方形成第一介电层；
将第二介电层附接至所述第一介电层；
在所述第二介电层上方设置金属膜；
在所述金属膜上方形成侧屏蔽结构；
将器件管芯附接至所述金属膜，其中，所述器件管芯位于由所述侧屏蔽结构环绕的区域中；
将所述器件管芯和所述侧屏蔽结构密封在密封材料中；以及
形成第一天线，其中，所述第一天线和所述器件管芯位于所述第二介电层的相对侧上，并且所述第一天线电连接至所述器件管芯。
9.根据权利要求8所述的方法，还包括形成多条再分布线，其中，通过所述多条再分布线进一步互连所述第一天线和所述器件管芯。
10.根据权利要求8所述的方法，还包括形成金属杆，其中，所述密封材料密封所述金属杆，并且通过所述金属杆进一步互连所述第一天线和所述器件管芯。
11.根据权利要求10所述的方法，其中，所述金属杆和所述侧屏蔽结构形成为共享共同的镀工艺。
12.根据权利要求8所述的方法，其中，形成所述侧屏蔽结构包括：
在所述第一介电层、所述第二介电层和所述金属膜上方沉积金属晶种层，其中，从所述金属晶种层开始形成所述侧屏蔽结构；以及
去除所述金属晶种层的部分，其中，所述金属晶种层的剩余部分成为所述侧屏蔽结构的部分。
13.根据权利要求8所述的方法，其中，所述第一天线的部分与所述器件管芯的部分垂直对准。
14.根据权利要求8所述的方法，还包括：
形成第三介电层，其中，所述第三介电层和所述器件管芯位于所述第二介电层的相对侧上；以及
在所述第三介电层上形成第二天线，其中，所述第二天线从所述第一天线电去耦，并且所述第一天线和所述第二天线组合形成堆叠的贴片天线。
15.一种半导体器件，包括：
介电板；
器件管芯；屏蔽结构，密封在密封材料中，其中，所述器件管芯位于所述屏蔽结构中，并且其中所述器件管芯和所述屏蔽结构都在所述介电板的下面；
贯通孔，穿过所述密封材料；以及
天线，具有与所述屏蔽结构重叠的至少部分，其中，所述天线通过所述贯通孔电连接至所述器件管芯，并且所述天线和所述器件管芯位于所述介电板的相对侧上。
16.根据权利要求15所述的半导体器件，其中，所述屏蔽结构包括：
导电帽；以及
侧屏蔽结构，连接至所述导电帽，其中，所述侧屏蔽结构形成环绕所述器件管芯的环。
17.根据权利要求16所述的半导体器件，还包括密封材料，其中，在所述密封材料中密封所述器件管芯和所述屏蔽结构两者，并且所述导电帽的边缘与所述密封材料接触以形成界面。
18.根据权利要求16所述的半导体器件，还包括管芯附接膜，其中，所述器件管芯通过所述管芯附接膜附接至所述导电帽的表面。
19.根据权利要求16所述的半导体器件，其中，所述导电帽和所述侧屏蔽结构之间具有可区分的界面。
20.根据权利要求15所述的半导体器件，其中，所述屏蔽结构是没有位于其中的可区分界面的集成单元。
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