TWI666711B - 封裝體及其形成方法 - Google Patents

封裝體及其形成方法 Download PDF

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Publication number
TWI666711B
TWI666711B TW107123374A TW107123374A TWI666711B TW I666711 B TWI666711 B TW I666711B TW 107123374 A TW107123374 A TW 107123374A TW 107123374 A TW107123374 A TW 107123374A TW I666711 B TWI666711 B TW I666711B
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Taiwan
Prior art keywords
dielectric layer
antenna
device die
shielding structure
forming
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TW107123374A
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English (en)
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TW201926488A (zh
Inventor
吳凱強
楊青峰
余振華
陳孟澤
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台灣積體電路製造股份有限公司
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Abstract

一種封裝體的形成方法，包含：在第一介電層上方形成 金屬支柱；將第二介電層附接在第一介電層上方；將裝置晶粒、第二介電層、屏蔽結構以及金屬支柱包封於包封材料中；平坦化包封材料以顯露裝置晶粒、屏蔽結構以及金屬支柱；以及形成電耦接至裝置晶粒的天線。天線具有豎直對準至裝置晶粒的部分的部分。

Description

封裝體及其形成方法
本發明的實施例是有關於一種封裝體及其形成方法。
隨著半導體技術的發展，半導體晶片/晶粒正變得愈來愈小。同時，更多功能需要整合至半導體晶粒中。因此，半導體晶粒需要具有封裝於較小區域中的越來越大數目個I/O襯墊，且I/O襯墊的密度隨時間推移而快速升高。結果，半導體晶粒的封裝變得較困難，此不利地影響封裝的良率。
習知封裝技術可劃分成兩種類別。在第一類別中，晶圓上的晶粒在進行切割前經封裝。此封裝技術具有一些有利特徵，諸如較大產量及較低成本。另外，需要較少底填充料或模製化合物。然而，此封裝技術亦遭受缺點。由於晶粒的大小正變得越來越小，且各別封裝可僅為扇入型封裝(Fan-in type package)，其中每一晶粒的I/O襯墊限於直接在各別晶粒的表面上方的區域。隨著晶粒的面積受限，I/O襯墊的數目歸因於I/O襯墊的間距限制受到限制。若襯墊的間距減小，則可出現焊料球橋接。另外，在固定焊料球大小要求下，焊料球必須具有某一大小，此舉又限制可 封裝於晶粒的表面上的焊料球的數目。
在封裝的另一類別中，自晶圓切割晶粒，隨後進行封裝。此封裝技術的有利特徵為形成扇出型封裝(Fan-out type package)的可能性，此意謂可將晶粒上的I/O襯墊重新分配至比晶粒大的區域，且因此可增大封裝於晶粒的表面上的I/O襯墊的數目。此封裝技術的另一有利特徵為封裝「已知良好裸片」且捨棄有缺陷的晶粒，且因此不在有缺陷的晶粒上浪費成本及精力。
在扇出型封裝中，裝置晶粒包封於模製化合物中，所述模製化合物接著經平坦化以暴露裝置晶粒。介電層形成於裝置晶粒上方。重佈線形成於介電層中以連接至裝置晶粒。扇出型封裝亦可包含貫穿模製化合物的穿孔。
本發明的一實施例提供一種封裝體的形成方法，包括：在第一介電層上方形成金屬支柱；將第二介電層附接在所述第一介電層上方；將裝置晶粒、所述第二介電層、屏蔽結構以及所述金屬支柱包封於包封材料中；平坦化所述包封材料以顯露所述裝置晶粒、所述屏蔽結構以及所述金屬支柱；以及形成電耦接至所述裝置晶粒的第一天線，其中所述第一天線具有豎直對準至所述裝置晶粒的部分的部分。
本發明的一實施例提供一種封裝體的形成方法，包括：在載體上方形成第一介電層；將第二介電層附接至所述第一介電層；將金屬膜安置於所述第二介電層上方；在所述金屬膜上方形成側面屏蔽結構；將裝置晶粒附接至所述金屬膜，其中所述裝置 晶粒在由所述側面屏蔽結構圍繞的區域中；將所述裝置晶粒及所述側面屏蔽結構包封在包封材料中；以及形成第一天線，其中所述第一天線及所述裝置晶粒在所述第二介電層的相對側上，且所述第一天線電耦接至所述裝置晶粒。
本發明的一實施例提供一種封裝體，包括：裝置晶粒；屏蔽結構，包封在包封材料中，其中所述裝置晶粒在所述屏蔽結構中；穿孔，穿透所述包封材料；以及天線，具有與所述屏蔽結構重疊的至少部分，其中所述天線經由所述穿孔電連接至所述裝置晶粒。
20‧‧‧載體
22‧‧‧離型膜
24‧‧‧介電緩衝層
26、84‧‧‧導電特徵
26A、66、70‧‧‧重佈線
26B、79‧‧‧平片天線
28、32、34、62、68、72、77‧‧‧介電層
30、48、64、94‧‧‧開口
36‧‧‧導電膜
38‧‧‧側面屏蔽結構
40‧‧‧導電支柱
42‧‧‧天線
44‧‧‧金屬晶種層
46‧‧‧光阻
50‧‧‧通孔
52、52A、52B、53、104‧‧‧裝置晶粒
54‧‧‧晶粒貼合膜
56‧‧‧金屬柱
58‧‧‧頂部介電層
60‧‧‧包封材料
71‧‧‧虛線
74‧‧‧凸塊下金屬
76‧‧‧電連接件
78‧‧‧條帶
80、86、92、98、100‧‧‧封裝體
82‧‧‧封裝組件
88‧‧‧底填充料
90‧‧‧屏蔽結構
106‧‧‧焊料區域
128‧‧‧介質塊
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226‧‧‧製程
D1‧‧‧距離
T1、T2‧‧‧厚度
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵的尺寸。
圖1至圖14說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。
圖15至圖18說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。
圖19及圖20說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。
圖21及圖22說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。
圖23說明根據一些實施例的封裝體的俯視圖。
圖24A、圖24B、圖24C以及圖24D說明根據一些實施例的一些屏蔽結構的透視圖。
圖25至圖28說明根據一些實施例的具有屏蔽結構的一些封裝體的橫截面圖。
圖29說明用於形成根據一些實施例的封裝體的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的多個不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包括第一特徵以及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複參考標號及/或字母。此重複是出於簡單以及清晰起見，且本身並不規定所論述的各種實施例及/或組態之間的關係。
此外，在本文中，為了易於描述，空間相對術語，諸如「在…下方(beneath)」、「下方(below)」、「下(lower)」、「上(above)」、「上方(upper)」及類似者可用於描述如圖式中所說明的一個元件或特徵與其他元件或特徵的關係。除圖中所描繪的定向以外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據各種實施例提供封裝體以及其形成方法。說明形成 封裝體的中間階段。論述一些實施例的一些變化。貫穿多個視圖及說明性實施例，相同的參考標號用以指明相同元件。
圖1至圖14說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。亦在圖29中繪示的製程流程200中示意性地說明圖1至圖14中繪示的步驟。
圖1說明載體20及設置於載體20上的離型膜22。載體20可為玻璃載體、陶瓷載體或其類似者。載體20可具有圓形俯視圖形狀，且可具有矽晶圓的大小。離型膜22可由基於聚合物的材料(諸如，光熱轉換(Light-To-Heat-Conversion；LTHC)材料)形成，其可連同載體20一起自將在後續步驟中形成的上覆結構移除。根據本揭露的一些實施例，離型膜22由環氧基熱釋放材料形成。在其他實施例中，離型膜22由紫外線(ultra-violet；UV)膠形成。離型膜22可以可流動形式分配且隨後固化。離型膜22的頂部表面經水平化且具有高共面度。
介電緩衝層24形成於離型膜22上。對應製程在圖29中所示的製程流程中說明為製程202。根據本揭露的一些實施例，介電緩衝層24由諸如聚合物的有機材料形成，所述有機材料亦可為感光性材料，諸如聚苯并噁唑(polybenzoxazole，PBO)、聚醯亞胺或類似者，其可經由曝光及顯影圖案化。根據本揭露的替代性實施例，介電緩衝層24由無機材料形成，所述無機材料可為諸如氮化矽的氮化物、諸如氧化矽的氧化物、磷矽玻璃(phosphosilicate，PSG)、硼矽玻璃(borosilicate glass，BSG)、硼摻雜磷矽玻璃(boron-doped phosphosilicate glass，BPSG)或其類似者。
參考圖2，導電特徵26形成於介電緩衝層24上方。對應製程在圖29中所示的製程流程中說明為製程204。導電特徵26可包含重佈線(Redistribution Line；RDL)26A及金屬襯墊。金屬襯墊中的一些可充當平片天線(patch antenna)26B。重佈線26A亦被稱作背側重佈線，此是由於其位於裝置晶粒52(圖7)的背側上。導電特徵26的形成可包含在介電緩衝層24上方形成金屬晶種層(未繪示)、在晶種層上方形成諸如光阻的經圖案化罩幕(未繪示)以及接著對暴露的晶種層執行金屬電鍍。隨後移除經圖案化罩幕，接著移除預先由所移除的經圖案化罩幕覆蓋的晶種層，從而如圖2中的保留導電特徵26。根據本揭露的一些實施例，晶種層包含鈦層及鈦層上方的銅層。晶種層可使用例如物理氣相沈積(Physical Vapor Deposition；PVD)來形成。電鍍可使用例如無電極電鍍、電化電鍍(electro-chemical plating)或其類似者執行。
進一步參考圖2，介電層28形成於導電特徵26上。對應製程在圖29中所示的製程流程中說明為製程206。介電層28的底部表面與導電特徵26及介電緩衝層24的頂部表面接觸。根據本揭露的一些實施例，介電層28由諸如聚合物的有機材料形成，所述聚合物可為諸如PBO、聚醯亞胺或其類似者的感光性聚合物。根據本揭露的替代性實施例，介電層28由無機材料形成，所述無機材料可為諸如氮化矽的氮化物、諸如氧化矽的氧化物、PSG、BSG、BPSG或其類似者。介電層28隨後經圖案化以在其中形成開口30。因此，導電特徵26的一些部分經由介電層28中的開口30暴露。
圖3說明介電層32及介電層34的置放，所述介電層用 於隔離電磁干擾(Electro Magnetic Interference；EMI)，如後續段落中將論述。對應製程在圖29中所示的製程流程中說明為製程208。根據本揭露的一些實施例，介電層32由黏著劑形成，其可為亦可用於黏著裝置晶粒的晶粒貼合膜(Die-Attach Film；DAF)。在介電層32為黏著膜的情況下，介電層32能夠黏附於介電層28。介電層32的厚度T1經選擇使得隨後形成的平片天線與裝置晶粒之間的電磁干擾降至可接受位準。厚度T1亦可與介電層32的介電常數(k值)相關，且k值愈大，愈大厚度T1為更佳的。舉例而言，當介電層32的k值為約3或更大且平片天線具有約60千兆赫(Giga Hertz，GHz)的操作頻率時，介電層32的厚度T1可大於約100微米(micrometer,μm)。作為另一實例，當介電層32的k值小於3(例如，約1)且平片天線具有約60千兆赫的操作頻率時，介電層32的厚度T1可大於約30微米。
介電層32上方可駐留介電層34。介電層34可由以下形成：有機材料(諸如聚合物)其可為聚醯亞胺、PBO或其類似者；或無機材料，諸如氧化物、氮化物或其類似者。應理解，介電層34亦具有隔離電磁干擾的功能。介電層32的先前所論述厚度T1是基於介電層34薄得多(例如厚度T2小於厚度T1的約10%)的假定。
根據本揭露的一些實施例，導電膜(其亦被稱作箔或板)36置放(當其預成型時)在介電層34上。對應製程在圖29中所示的製程流程中亦說明為製程208。導電膜36亦可沈積在介電層34上。導電膜可為由銅、鈦、鎳或其多層形成的金屬膜。根據本揭露的一些實施例，介電層32及介電層34以及導電膜36預成型 為一單元，且所述單元置放於介電層28上。根據替代性實施例，介電層32及介電層34預成型且隨後置放在介電層28上方，接著例如經由諸如物理氣相沈積、化學氣相沈積(Chemical Vapor Deposition；CVD)或其類似者的沈積製程形成導電膜36，隨後執行圖案化步驟。在俯視圖中，導電膜36可為其中無開口的固體板、其中具有開口以顯露底層介電層34的網狀物(網格)，或多個互連或離散的平行條帶。
圖4至圖7說明側面屏蔽結構38、導電支柱40以及可選擇性的天線42(圖6)的形成。貫穿本說明書，導電支柱40被替代地稱為穿孔，此是因為金屬支柱將穿透隨後分配的包封材料。參考圖4，金屬晶種層44例如經由PVD形成為覆蓋層。金屬晶種層44的一部分與導電膜36重疊。金屬晶種層44可包含銅，或根據一些實施例可包含鈦層及鈦層上方的銅層。光阻46形成於金屬晶種層44上方。對應製程在圖29中所示的製程流程中說明為製程210。根據本揭露的一些實施例，光阻46為乾膜，其層壓至金屬晶種層44上。根據本揭露的替代性實施例，光阻46經由旋塗分配。
隨後使用微影罩幕(未繪示)對光阻46執行曝光，所述光阻包含允許光穿過的透明部分及用於阻擋光的不透明部分。在經暴露光阻46的顯影之後，開口48形成於光阻46中。金屬晶種層44因此具有暴露於開口48的一些部分。
接著，如圖5中所示，側面屏蔽結構38、導電支柱40以及天線42(圖7)經由電鍍製程形成，諸如無電極電鍍製程或電化電鍍製程。對應製程在圖29中所示的製程流程中說明為製程 212。在後續步驟中，移除光阻46，且因此暴露金屬晶種層44的底層部分。隨後在蝕刻步驟中移除金屬晶種層44的經暴露部分。對應製程在圖29中所示的製程流程中說明為製程214。所得側面屏蔽結構38、導電支柱40以及天線42說明於圖6中。由於導電膜36(圖3)比晶種層更厚，且亦因為導電膜36可由與金屬晶種層44的底部層不同的材料形成，導電膜36在移除金屬晶種層44之後保留。貫穿本說明書，金屬晶種層44的剩餘部分亦被視為各別側面屏蔽結構38、導電支柱40以及天線42的部分。上述製程亦形成延伸至介電層28中以將導電支柱40電連接至導電特徵26的通孔50。
當自圖6中所示的結構的頂部觀看時，側面屏蔽結構38可具有選自多個候選形狀的形狀。舉例而言，側面屏蔽結構38可包含多個離散支柱(類似於圖24A及圖24B中示出的離散支柱)，所述離散支柱的底部接觸導電膜36的頂部表面。多個離散支柱緊密地定位，其中距離足夠小以阻擋電磁信號，且多個離散支柱對準至環。離散支柱可具有圓形、矩形、六邊形、橢圓形、細長帶或其類似者的俯視圖形狀。側面屏蔽結構38可替代地具有完整環形(其中無破裂)的俯視圖形狀。天線42可經形成，且配置為一個或多個群組。根據本揭露的一些實施例，每一群組包含兩個L形部分，其中兩個L形部分的底部支腳位於兩個L形部分的兩個豎直部分之間。
圖7說明裝置晶粒52的置放。對應製程在圖29中所示的製程流程中說明為製程216。裝置晶粒52經由晶粒貼合膜54黏附至導電膜36，所述晶粒貼合膜為黏著膜。為形成晶粒貼合膜 54及經附接裝置晶粒52，晶粒貼合膜54可預先附接至裝置晶粒52所定位的晶圓，且隨後晶粒貼合膜54及晶圓自晶圓切割。因此，裝置晶粒52的邊緣與晶粒貼合膜54的各別邊緣齊平。裝置晶粒52可為射頻(radio frequency，RF)晶粒，其經組態以產生及/或接收射頻信號。裝置晶粒52亦可為其中包含邏輯電晶體的邏輯裝置晶粒。裝置晶粒52亦可為基頻(Baseband；BB)晶粒。
根據本揭露的一些實施例，金屬柱56(諸如銅支柱)或金屬襯墊預成型為裝置晶粒52的最頂端部分，且金屬柱56電耦接至裝置晶粒52中的諸如電晶體的積體電路裝置(未繪示)。根據本揭露的一些實施例，諸如聚合物的介電材料填充相鄰金屬柱56之間的間隙以形成頂部介電層58。根據一些實施例，介電層58可由聚醯亞胺或PBO形成。根據本揭露的一些實施例，在置放裝置晶粒52時，介電層58的頂部表面高於金屬柱56的頂部表面或與其共面。
接著，亦如圖7中所示，包封材料(包封體)60包封在裝置晶粒52、側面屏蔽結構38、導電支柱40以及天線42上。對應製程在圖29中所示的製程流程中亦說明為製程216。包封材料60填充側面屏蔽結構38、導電支柱40、裝置晶粒52與天線42之間的間隙。包封材料60可包含模製化合物、模製底填充料、環氧樹脂或樹脂。根據本揭露的一些實施例，包封材料60包括基底材料及基底材料中的填充劑顆粒(filler particle)。基底材料可為環氧樹脂、樹脂、聚合物或其類似者。填充劑顆粒可為二氧化矽、氧化鋁或其類似者的球形顆粒。包封材料60亦可為均勻材料，此意謂包封材料60的每一部分的材料與其他部分相同。舉例而言， 整個包封材料60的可為包含相同基底材料及相同填充劑顆粒的模製化合物。此外，在側面屏蔽結構38內部的包封材料60的部分與在側面屏蔽結構38外部的包封材料60的部分相同。
進一步參考圖7，對淡薄包封材料60執行諸如化學機械拋光(Chemical Mechanical Polish；CMP)製程或機械研磨製程的平坦化製程，直至金屬柱56、側面屏蔽結構38、導電支柱40以及天線42暴露為止。對應製程在圖29中所示的製程流程中亦說明為製程216。歸因於平坦化，金屬柱56的頂端與側面屏蔽結構38、導電支柱40以及天線42的頂部表面實質上齊平(共面)，且與包封材料60的頂部表面實質上共面。貫穿本說明書，導電支柱40替代地被稱作穿孔，此是因為其穿透包封材料60。
圖8至圖12說明前側重佈線及導電連接件的形成。對應製程在圖29中所示的製程流程中說明為製程218。參考圖8，形成介電層62。根據本揭露的一些實施例，介電層62由諸如聚合物(其可為PBO、聚醯亞胺或其類似者)的有機材料形成。根據本揭露的替代性實施例，介電層62由諸如氮化矽、氧化矽或其類似者的無機材料形成。開口64形成於介電層62中以暴露側面屏蔽結構38、導電支柱40、天線42以及金屬柱56。開口64的形成可包含微影製程，所述微影製程包含曝光且隨後顯影介電層62。
接著，參考圖9，重佈線66經形成連接至(且亦可互連)金屬柱56、側面屏蔽結構38、導電支柱40、天線42以及金屬柱56。重佈線66包含在介電層62上方的金屬跡線(金屬線)以及延伸至介電層62中的開口中的通孔。重佈線66的形成可包含電鍍製程，其中重佈線66中的每一者包含晶種層(未繪示)及晶種 層上方的經電鍍金屬材料。晶種層以及經電鍍材料可由相同材料或不同材料形成。重佈線66可包括包含鋁、銅、鎢以及其合金的金屬或金屬合金。
參考圖10，介電層68、重佈線70以及介電層72形成於重佈線66及介電層62上方。介電層68可使用選自與介電層62的彼等相同的候選材料的材料形成。舉例而言，介電層68可包括PBO、聚醯亞胺或其類似者。替代地，介電層68可包含非有機介電材料，諸如，氧化矽、氮化矽、碳化矽、氮氧化矽或其類似者。
重佈線70電連接至重佈線66。重佈線70的形成可採用與用於形成重佈線66的彼等類似的方法及材料。重佈線70及重佈線66亦被稱作前側重佈線，此是因為其位於裝置晶粒52的前側上。虛線71經示出表示側面屏蔽結構38的部分與重佈線70中的一者之間的電連接。虛線指示電連接並未在所示出平面中。亦如圖10中所示，額外介電層72經形成以覆蓋重佈線70及介電層68。介電層72可由選自用於形成介電層62以及68的相同候選材料的材料形成。
圖11及圖12根據一些實施例說明凸塊下金屬(Under-Bump Metallurgies；UBM)74(圖11)的形成及電連接件76(圖12)的形成。UBM 74的形成可包含圖案化介電層72以形成開口，以及沈積及圖案化金屬層，諸如鈦層及鈦層上方的銅層。電連接件76的形成可包含將焊球置放於UBM 74的經暴露部分上，且接著回焊焊球。根據本揭露的替代性實施例，電連接件76的形成包括執行電鍍步驟以在重佈線70上方形成焊料區域且接著回焊所述焊料區域。電連接件76亦可包含金屬柱，及任選地金屬 柱上的焊蓋，所述焊蓋亦可經由電鍍形成。貫穿本說明書，包含介電緩衝層24的經組合結構及上覆結構將被稱作封裝體100，其可為具有圓形俯視圖形狀的複合晶圓。複合晶圓100包含彼此相同的多個組件，所述組件中的每一者根據一些實施例在圖12中示出。
接著，封裝體100自載體20拆卸。對應製程在圖29中所示的製程流程中說明為製程220。在拆卸中，膠帶78(圖13)可黏附至電連接件76上。在後續步驟中，諸如UV光或雷射光束的輻射投影於離型膜22上以分解離薄膜22，且載體20自封裝體100拆卸。
接著，如圖13中所示，介電層77形成於介電緩衝層24上方。對應製程在圖29中所示的製程流程中說明為製程222。根據本揭露的一些實施例，介電層77由模製化合物形成，且藉由塗佈且隨後固化模製化合物形成。模製化合物77亦可包含基底材料(諸如樹脂或聚合物)及基底材料中的球形顆粒。介電層77亦可由其他介電材料形成，所述其他介電材料可為諸如氧化物、氮化物、碳化物或其類似者的無機材料。可執行平坦化製程以平坦化介電層77的頂部表面。
平片天線79形成於介電層77上方。對應製程在圖29中所示的製程流程中亦說明為製程222。根據本揭露的一些實施例，平片天線79由金屬形成，其可由銅、鋁、鎢、鎳、銀、金、其合金及/或其多個層形成。平片天線79電性浮置且與底層平片天線26B重疊。
執行單一化(晶粒切割)步驟以將封裝體100切割成多 個封裝體，每一者類似於圖13中所示。對應製程在圖29中所示的製程流程中說明為製程224。所得封裝體中的一者示出為圖14中的封裝體80。
圖14說明封裝體80與封裝組件82的接合。對應製程在圖29中所示的製程流程中說明為製程226。根據本揭露的一些實施例，接合經由電連接件76執行，所述電連接件可包含接合至封裝組件82中的導電特徵84的焊料區域。根據本揭露的一些實施例，封裝組件82為封裝基底，其可為無核心基底或有核心(諸如玻璃纖維強制型核心)的基底。根據本揭露的其他實施例，封裝組件82為印刷電路板或封裝體。底填充料88可設置於封裝體80與封裝組件82之間。圖14中的封裝體在下文被稱作封裝體86。
如圖14中所示，平片天線26B及平片天線79形成堆疊式平片天線，其訊號耦合至裝置晶粒52。接地面板(未繪示)可形成於裝置晶粒52之下的重佈線中。接地面板可在互連裝置晶粒52及堆疊式平片天線的饋入線下方。平片天線79重疊，且經由電磁場耦合至平片天線26B。貫穿本說明書，導電膜36及側面屏蔽結構38組合起來被稱作屏蔽結構90，其中導電膜36形成屏蔽結構90的蓋，且側面屏蔽結構38形成屏蔽結構90的裙部。屏蔽結構90經由重佈線66、重佈線70以及電結構76電接地，且因此具有為裝置晶粒52屏蔽來自堆疊式平片天線的電磁干擾的功能。接地路徑中的一些由虛線71表示。根據本揭露的一些實施例，側面屏蔽結構38包含多個金屬支柱，且多個金屬支柱中的每一者可單獨地電接地以獲得更佳屏蔽效果。
在圖14中，平片天線26B及平片天線79具有與裝置晶 粒52的一些部分重疊的部分。因此，封裝體86所佔據的面積減小。所述重疊可導致裝置晶粒52與平片天線26B及平片天線79之間的電磁干擾惡化。根據本揭露的一些實施例，電磁干擾問題藉由形成屏蔽結構90及在屏蔽結構90與平片天線26B及平片天線79之間插入介電層32及介電層34(其具有足夠厚度)而減少。
圖23說明封裝體86的部分的俯視圖。屏蔽結構90包含側面屏蔽結構38，其形成圍繞裝置晶粒52以及介電層32及介電層34的環。包封材料60包封其中的屏蔽結構90。包封材料60包含圍繞屏蔽結構90的外部部分，及由屏蔽結構90的側面屏蔽結構38圍繞的內部部分。
圖15至圖22說明根據本揭露的一些實施例的封裝體的形成中的中間階段的橫截面圖。除非另外規定，否則此等實施例中的組件的材料及形成方法實質上與類似組件相同，所述組件由與圖1至圖14中示出的實施例中的相同參考編號表示。關於圖15至圖22中示出的組件的形成過程及材料的細節可因此在對圖1至圖14中示出的實施例的論述中發現。
圖15至圖18說明根據本揭露的一些實施例的封裝體的形成中的中間階段的橫截面圖。此等實施例類似於圖1至圖14中示出的實施例，不同之處在於側面屏蔽結構38以不同方式形成。此等實施例可在側面屏蔽結構38與導電支柱40之間的高度差大於製程範圍時採用，且因此側面屏蔽結構38及導電支柱40無法同時電鍍。此等實施例的初始步驟與圖1至圖7中所示的基本上相同以形成圖15中所示的結構，除了圖7中所示的側面屏蔽結構38並未形成於圖15中所示的結構中以外。接著，如圖16中所示， 開口94形成於包封材料60中以顯露導電膜36的一些部分。舉例而言，開口94可經由雷射鑽孔或蝕刻形成。當經由雷射鑽孔形成時，開口94可具有大於各別底部寬度的頂部寬度。
接著，如圖17中所示，導電膏填充至開口94(圖16)中，且隨後固化以形成側面屏蔽結構38。舉例而言，填充可經由模板印刷達成。導電膏可包含銅膏、銀膏或其類似者。後續步驟可與參考圖8至圖14所示出及論述的後續步驟基本上相同，且細節在本文中並不重複。所得封裝體86示出於圖18中。
圖19及圖20說明根據本揭露的一些實施例的封裝體的形成中的中間階段的橫截面圖。此等實施例類似於如圖1至圖14中所示的實施例，不同之處在於屏蔽結構90預成型為積體單元。此等實施例的初始步驟與圖1至圖7中所示的基本上相同以形成圖19中所示的結構，除了在導電支柱40及天線42形成時側面屏蔽結構(圖7)並未形成以外。
根據本揭露的一些實施例，如圖19中所示，屏蔽結構90經預成型，且隨後附接至介電層32及介電層34。裝置晶粒52隨後附接至屏蔽結構90。介電層32、介電層34、屏蔽結構90以及裝置晶粒52因此組合形成離散單元。離散單元隨後置放於介電層28上。根據本揭露的替代性實施例，介電層32及介電層34首先置放於介電層28上，且隨後裝置晶粒52置放於屏蔽結構90內部並附接至屏蔽結構90。根據此等實施例的屏蔽結構90可具有盆槽形狀，其中側面屏蔽結構38及導電膜36由相同材料形成，且形成為其間無可識別界面的積體件。後續步驟可與參考圖8至圖14所示出及論述的後續步驟基本上相同，且細節在本文中並不重 複。所得封裝體86示出於圖20中。
圖21及圖22說明根據本揭露的一些實施例的封裝體的形成中的中間階段的橫截面圖。此等實施例類似於如圖1至圖14中所示的實施例，不同之處在於屏蔽結構90藉由噴塗導電膏(諸如銅膏或銀膏)或經由濺鍍製程預成型於裝置晶粒52上。晶粒貼合膜54可存在，或可省略以使得導電膏接觸裝置晶粒52的底部表面。此等實施例的初始步驟與圖1至圖7中所示的基本上相同以形成圖21中所示的結構，除了在導電支柱40及天線42形成時側面屏蔽結構38(圖7)並未形成以外。
根據本揭露的一些實施例，如圖21中所示，裝置晶粒52及預成型屏蔽結構90附接至介電層32及介電層34以形成離散單元。離散單元隨後置放於介電層28上。後續步驟可與參考圖8至圖14所示出及論述的後續步驟基本上相同，且細節在本文中並不重複。所得封裝體86示出於圖22中。
圖24A、圖24B、圖24C以及圖24D說明根據本揭露的一些實施例的一些屏蔽結構90的透視圖。此等實施例(只要可適用)可用於圖14、圖18、圖20以及圖22中示出的結構。參考圖24A，屏蔽結構90的導電膜36包含多個離散金屬帶，所述多個離散金屬帶彼此分離。側面屏蔽結構38包含連接至離散帶的多個金屬支柱。金屬支柱中的每一者可單獨地電接地。相鄰金屬支柱之間的距離D1較小以實現有效的電磁干擾隔離，例如，其中距離D1小於射頻信號的波長的約5%，所述射頻信號藉由平片天線傳輸或接收。裝置晶粒52在由側面屏蔽結構38中的金屬支柱形成的環中。
圖24B說明類似於圖24A中所示的屏蔽結構90的屏蔽結構90，不同之處在於導電膜36為固體板。根據替代性實施例(未繪示)，導電膜36可為網狀物(網格)，其具有穿透導電膜36的貫通開口。圖24C說明導電膜36為固體板，且側面屏蔽結構38為固體壁，其可完全將裝置晶粒52圍繞於其中。圖24D說明所述導電膜36包含離散帶，而側面屏蔽結構38為固體環。如圖24B、圖24C以及圖24D中所示的屏蔽結構90可經預成型，且隨後如圖19中所示的附接。
圖25至圖28說明包含屏蔽結構的多個封裝體92。應理解，圖25至圖28中的實施例中的屏蔽可採用如圖1至圖24中的結構及形成方法(只要可適用)。圖25說明根據本揭露的一些實施例的封裝體，其中封裝體包含兩個屏蔽結構90，所述兩個屏蔽結構各自具有裝置晶粒(52A及52B)。裝置晶粒52A及裝置晶粒52B兩者可為射頻晶粒。封裝體可包含或可不含平片天線26B及平片天線79，且側面屏蔽結構90用於減少/消除裝置晶粒52A與裝置晶粒52B之間的干擾以及裝置晶粒52A及裝置晶粒52B與平片天線26B及平片天線79(若形成)之間的干擾。
圖26說明根據本揭露的一些實施例的封裝體92，其中側面屏蔽結構90將裝置晶粒52圍繞於其中，所述裝置晶粒可為射頻裝置晶粒或基頻晶粒。裝置晶粒53亦置放於封裝體中，其中裝置晶粒53並未由任何屏蔽結構圍繞及覆蓋。裝置晶粒53可為邏輯晶粒。封裝體可包含或可不含天線，且屏蔽結構90用於消除晶粒之間以及晶粒與天線(若形成)之間的干擾。
圖27說明根據本揭露的一些實施例的封裝體92，其中封 裝體包含具有置放於其中的邏輯裝置晶粒52的屏蔽結構90。封裝體在其中未建構有天線。根據本揭露的一些實施例，導電支柱40連接至背側重佈線26A。封裝體98經由焊料區域106接合至底層封體裝86。封裝體98在其中可包含裝置晶粒104，所述裝置晶粒可為例如記憶體晶粒。圖28類似於圖26，除了介質塊128包封於包封材料60中以外。介質塊128可具有較低熱膨脹係數(Coefficient of Thermal Expansion；CTE)，且因此可減少封裝體92的彎曲。舉例而言，介質塊128的熱膨脹係數可小於約5ppm/℃。
在以上所說明實施例中，一些製程及特徵根據本揭露的一些實施例論述。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助對3D封裝或3D積體電路裝置的驗證測試。測試結構可包含例如形成於重佈層中或基底上的測試襯墊，其允許測試3D封裝或3DIC、使用探測器及/或探測卡及其類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併有對已知良好晶粒的中間驗證的測試方法使用，以提高產率及降低成本。
本揭露的實施例具有一些有利特徵。藉由形成導電屏蔽結構以屏蔽裝置晶粒，且進一步藉由添加介電層以隔離電磁干擾，裝置晶粒與天線之間的電磁干擾減少。
根據本揭露的一些實施例，一種封裝體的形成方法包含：在第一介電層上方形成金屬支柱；將第二介電層附接在第一介電層上方；將裝置晶粒、第二介電層、屏蔽結構以及金屬支柱包封於包封材料中；平坦化包封材料以顯露裝置晶粒、屏蔽結構 以及金屬支柱；以及形成電耦接至裝置晶粒的第一天線，其中第一天線具有豎直對準至裝置晶粒的部分的部分。根據一些實施例，所述方法更包含形成屏蔽結構，包括：將金屬膜附接在第二介電層上方；以及在金屬膜上方形成側面屏蔽結構，其中側面屏蔽結構及金屬膜組合形成屏蔽結構。根據一些實施例，所述方法更包含形成屏蔽結構，包含：將金屬膜附接在第二介電層上方；在包封之後，在包封材料中形成開口以顯露金屬膜的部分；以及將導電膏填充至開口中以在金屬膜上方形成側面屏蔽結構，其中側面屏蔽結構及金屬膜組合形成屏蔽結構。根據一些實施例，所述方法更包含預成型屏蔽結構；將裝置晶粒附接至屏蔽結構；以及將預成型屏蔽結構及裝置晶粒作為積體單元附接在第二介電層上方。根據一些實施例，所述方法更包含將導電膏噴塗至裝置晶粒的表面及側壁上以形成屏蔽結構；以及將屏蔽結構及裝置晶粒作為積體單元附接在第二介電層上方。根據一些實施例，所述方法更包含形成第三介電層，其中第三介電層及裝置晶粒在第二介電層的相對側上；以及在第三介電層上形成第二天線，其中第二天線自第一天線電解耦，且經組態以經由電磁場訊號耦合至第一天線，且第一天線及第二天線組合形成堆疊式平片天線。根據一些實施例，所述方法更包含電接地屏蔽結構。
根據本揭露的一些實施例，一種封裝體的形成方法包含：在載體上方形成第一介電層；將第二介電層附接至第一介電層；將金屬膜安置於第二介電層上方；在金屬膜上方形成側面屏蔽結構；將裝置晶粒附接至金屬膜，其中裝置晶粒在藉由側面屏蔽結構圍繞的區域中；將裝置晶粒及側面屏蔽結構包封於包封材 料中；以及形成第一天線，其中第一天線及裝置晶粒在第二介電層的相對側上，且第一天線電耦接至裝置晶粒。根據一些實施例，所述方法更包含形成多個重佈線，其中第一天線及裝置晶粒經由多個重佈線進一步互連。根據一些實施例，所述方法更包含形成金屬支柱，其中包封材料包封所述金屬支柱，且第一天線及裝置晶粒經由金屬支柱進一步互連。根據一些實施例，金屬支柱及側面屏蔽結構共用常用電鍍製程形成。根據一些實施例，形成側面屏蔽結構包括：在第一介電層、第二介電層以及金屬膜上方沈積金屬晶種層，其中側面屏蔽結構自金屬晶種層開始形成；以及移除金屬晶種層的部分，其中金屬晶種層的剩餘部分為側面屏蔽結構的部分。根據一些實施例，第一天線的部分與裝置晶粒的部分豎直對準。根據一些實施例，所述方法更包含形成第三介電層，其中第三介電層及裝置晶粒在第二介電層的相對側上；以及在第三介電層上形成第二天線，其中第二天線自第一天線電解耦，且第一天線及第二天線組合形成堆疊式平片天線。
根據本揭露的一些實施例，封裝體包含：裝置晶粒；包封在包封材料中的屏蔽結構，其中裝置晶粒在屏蔽結構中；穿透包封材料的穿孔；以及具有與屏蔽結構重疊的至少部分的天線，其中天線經由穿孔電連接至裝置晶粒。根據一些實施例，屏蔽結構包含：導電蓋；以及連接至導電蓋的側面屏蔽結構，其中側面屏蔽結構形成圍繞裝置晶粒的環。根據一些實施例，封裝體更包含包封材料，其中裝置晶粒及屏蔽結構兩者皆包封在包封材料中，且導電蓋的邊緣與包封材料接觸以形成界面。根據一些實施例，封裝體更包含晶粒貼合膜，其中裝置晶粒經由晶粒貼合膜附 接至導電蓋的表面。根據一些實施例，導電蓋與側面屏蔽結構之間具有可識別的界面。根據一些實施例，屏蔽結構為其中無可識別界面的積體單元。
前文概述若干實施例的特徵，使得熟習此項技術者可更佳地理解本揭露的態樣。熟習此項技術者應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優勢的其他處理程序及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且熟習此項技術者可在不脫離本揭露的精神及範疇的情況下在本文中進行改變、替代及更改。

Claims (10)

  1. 一種封裝體的形成方法，包括：在第一介電層上方形成金屬支柱；將第二介電層附接在所述第一介電層上方；將裝置晶粒、所述第二介電層、屏蔽結構以及所述金屬支柱包封於包封材料中；平坦化所述包封材料以顯露所述裝置晶粒、所述屏蔽結構以及所述金屬支柱；以及形成電耦接至所述裝置晶粒的第一天線，其中所述第一天線具有豎直對準至所述裝置晶粒的部分的部分。
  2. 如申請專利範圍第1項所述的方法，更包括形成所述屏蔽結構，包括：將金屬膜附接在所述第二介電層上方；以及在所述金屬膜上方形成側面屏蔽結構，其中所述側面屏蔽結構及所述金屬膜組合形成所述屏蔽結構。
  3. 如申請專利範圍第1項所述的方法，更包括形成所述屏蔽結構，包括：將金屬膜附接在所述第二介電層上方；在所述包封之後，在所述包封材料中形成開口以顯露所述金屬膜的部分；以及將導電膏填充至所述開口中以在所述金屬膜上方形成側面屏蔽結構，其中所述側面屏蔽結構及所述金屬膜組合形成所述屏蔽結構。
  4. 如申請專利範圍第1項所述的方法，更包括：預成型所述屏蔽結構；將所述裝置晶粒附接至所述屏蔽結構；以及將所述預成型屏蔽結構及所述裝置晶粒作為積體單元附接在所述第二介電層上方。
  5. 一種封裝體的形成方法，包括：在載體上方形成第一介電層；將第二介電層附接至所述第一介電層；將金屬膜安置於所述第二介電層上方；在所述金屬膜上方形成側面屏蔽結構；將裝置晶粒附接至所述金屬膜，其中所述裝置晶粒在由所述側面屏蔽結構圍繞的區域中；將所述裝置晶粒及所述側面屏蔽結構包封在包封材料中；以及形成第一天線，其中所述第一天線及所述裝置晶粒在所述第二介電層的相對側上，且所述第一天線電耦接至所述裝置晶粒。
  6. 如申請專利範圍第5項所述的方法，其中所述形成所述側面屏蔽結構包括：在所述第一介電層、所述第二介電層以及所述金屬膜上方沈積金屬晶種層，其中所述側面屏蔽結構自所述金屬晶種層開始形成；以及移除所述金屬晶種層的部分，其中所述金屬晶種層的剩餘部分為所述側面屏蔽結構的部分。
  7. 如申請專利範圍第5項所述的方法，更包括：形成第三介電層，其中所述第三介電層及所述裝置晶粒在所述第二介電層的相對側上；以及在所述第三介電層上形成第二天線，其中所述第二天線自所述第一天線電解耦，且所述第一天線及所述第二天線組合形成堆疊式平片天線。
  8. 一種封裝體，包括：裝置晶粒；屏蔽結構，包封在包封材料中，其中所述裝置晶粒在所述屏蔽結構中；穿孔，穿透所述包封材料；第一天線，具有與所述屏蔽結構重疊的至少部分，其中所述第一天線經由所述穿孔電連接至所述裝置晶粒；以及第二天線，穿透所述包封材料。
  9. 如申請專利範圍第8項所述的封裝體，其中所述屏蔽結構包括：導電蓋；以及側面屏蔽結構，連接至所述導電蓋，所述側面屏蔽結構位於所述裝置晶粒與所述第二天線之間，其中所述側面屏蔽結構形成圍繞所述裝置晶粒的環。
  10. 一種封裝體，包括：裝置晶粒；屏蔽結構，包封在包封材料中，其中所述裝置晶粒在所述屏蔽結構中；穿孔，穿透所述包封材料；第一天線，具有與所述屏蔽結構重疊的至少部分，其中所述第一天線經由所述穿孔電連接至所述裝置晶粒；第二天線，與所述第一天線重疊，且所述第一天線位於所述第二天線與所述屏蔽結構的部分之間；以及介電層，位於所述第一天線與所述第二天線之間。
TW107123374A 2017-12-08 2018-07-05 封裝體及其形成方法 TWI666711B (zh)

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