TWI653719B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI653719B TWI653719B TW106142891A TW106142891A TWI653719B TW I653719 B TWI653719 B TW I653719B TW 106142891 A TW106142891 A TW 106142891A TW 106142891 A TW106142891 A TW 106142891A TW I653719 B TWI653719 B TW I653719B
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- Prior art keywords
- conductive
- die
- redistribution structure
- semiconductor device
- coating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims description 55
- 238000000576 coating method Methods 0.000 claims abstract description 110
- 239000011248 coating agent Substances 0.000 claims abstract description 109
- 239000012778 molding material Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 239000011247 coating layer Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 155
- 238000000465 moulding Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 20
- 239000013078 crystal Substances 0.000 description 32
- 230000008569 process Effects 0.000 description 30
- 239000000758 substrate Substances 0.000 description 23
- 239000003989 dielectric material Substances 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 17
- 239000010949 copper Substances 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 17
- 239000012790 adhesive layer Substances 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000011521 glass Substances 0.000 description 9
- 238000002161 passivation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000002390 adhesive tape Substances 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910005540 GaP Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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Abstract
一種半導體裝置包括第一晶粒,所述第一晶粒嵌置於模塑材料中,其中所述第一晶粒的接觸接墊鄰近所述模塑材料的第一側。所述半導體裝置更包括重佈線結構,位於所述模塑材料的所述第一側之上;第一金屬塗層,沿所述第一晶粒的側壁以及位於所述第一晶粒與所述模塑材料之間;以及第二金屬塗層,沿所述模塑材料的側壁以及位於所述模塑材料的與所述第一側相對的第二側上。
Description
本申請案主張於2017年6月30日提出申請且名稱為「具有電磁干擾屏蔽的半導體裝置(SemiconductorDevicewith Shieldfor Electromagnetic Interference)」的美國臨時專利申請案第62/527,879號的優先權,所述申請案全文併入本案供參考。
本發明的實施例是有關於一種半導體裝置及其形成方法。
由於各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度持續地提高,半導體工業經歷了快速成長。最重要的是,積體密度的此種提高源自最小特徵尺寸的不斷減小,進而使得在給定區域中能夠整合更多的組件。隨著近來對更小的電子裝置的需求的增長,已產生對更小且更具創造性的半導體晶粒封裝技術的需要。
該些封裝技術的實例是疊層封裝(Package-on-Package,POP)技術。在疊層封裝中,頂部半導體封裝堆疊於底部半導體封裝的頂部上,以使得能夠達成高積體度(level of integration)及組件密度。另一實例是多晶片模組(Multi-Chip-Module,MCM)技術,其中多個半導體晶粒被封裝於一個半導體封裝中以提供具有積體功能性的半導體裝置。
具有高積體度的先進的封裝技術能夠生產功能性增強且佔用面積(footprint)小的半導體裝置,此對於例如行動電話、平板、及數位音樂播放機等小形狀因數(small form factor)裝置而言是有利的。另一優點是對半導體封裝內的互相操作部分進行連接的導電路徑的長度縮短。此會提高半導體裝置的電性效能,乃因各電路之間的內連線的較短佈線會使得訊號傳播較快且雜訊及串擾減少。
一種半導體裝置,包括第一晶粒、重佈線結構、第一金屬塗層以及第二金屬塗層。第一晶粒嵌置於模塑材料中,其中所述第一晶粒的接觸接墊鄰近所述模塑材料的第一側。重佈線結構位於所述模塑材料的所述第一側之上。第一金屬塗層沿所述第一晶粒的側壁以及位於所述第一晶粒與所述模塑材料之間。第二金屬塗層沿所述模塑材料的側壁以及位於所述模塑材料的與所述第一側相對的第二側上。
一種半導體裝置,包括第一晶粒、第一重佈線結構、第二重佈線結構、第一導電結構以及通孔。第一晶粒位於模塑層中。第一重佈線結構位於所述模塑層的第一側上且包括導電線,所述導電線電性耦合至所述第一晶粒的接觸接墊。第二重佈線結構位於所述模塑層的與所述第一側相對的第二側上。第一導電結構位於所述模塑層中且在側向上與所述第一晶粒間隔開,其中所述第一導電結構包括第一介電區與導電塗層。第一介電區位於所述第一晶粒周圍。導電塗層位於所述第一介電區的相對兩側上。通孔位於所述模塑層中,其中所述通孔耦合至所述第一重佈線結構的第一導電線及所述第二重佈線結構的第二導電線。
一種形成半導體裝置的方法,包括:將第一晶粒貼合至載體,其中位於所述第一晶粒的前側上的接觸接墊背對所述載體;在所述載體之上以及所述第一晶粒周圍形成模塑材料;在所述模塑材料的遠離所述載體的第一側之上形成重佈線結構,其中所述重佈線結構包括導電線,所述導電線電性耦合至所述第一晶粒,其中所述重佈線結構的第一導電特徵在所述重佈線結構的側壁處暴露出;剝離所述載體;以及沿所述模塑材料的側壁以及所述模塑材料的與所述第一側相對的第二側形成第一導電塗層,其中所述第一導電塗層電性連接至所述重佈線結構的所述第一導電特徵。
30‧‧‧半導體晶粒/晶粒
30’‧‧‧半導體晶圓/晶圓
31‧‧‧線
40‧‧‧第二晶粒/晶粒
101、111‧‧‧接觸接墊
101A、111A‧‧‧接地接觸接墊
101B‧‧‧接觸接墊
103、113‧‧‧鈍化膜
105‧‧‧晶粒連接件/導電柱
105’‧‧‧導電特徵
105A、115‧‧‧導電柱
107、117‧‧‧介電材料
108‧‧‧膠帶
109、509‧‧‧導電塗層/金屬塗層
119‧‧‧導電層/金屬塗層
119D、150’‧‧‧區
120‧‧‧載體/玻璃載體
121‧‧‧黏著劑層
123‧‧‧模塑材料
130、160‧‧‧重佈線結構
131、131A、161‧‧‧導電線
132‧‧‧介電層
133‧‧‧導通孔
133A、133B‧‧‧通孔
137、137A、527‧‧‧導電接墊
140、150‧‧‧區域
143、143A、541、545、543‧‧‧外部連接件
151、153‧‧‧結構
154、155、519‧‧‧導電層
157‧‧‧障壁層
159‧‧‧介面層
161’‧‧‧導電線
163‧‧‧通孔
164‧‧‧開口
200、300、400、510‧‧‧半導體裝置
500‧‧‧電氣系統
520‧‧‧基底
521、525‧‧‧導電跡線/導電線/接地平面
523‧‧‧導電跡線/導電線
530‧‧‧連接件
531‧‧‧接地端子
533‧‧‧訊號端子
1010、1020、1030、1040、1050‧‧‧步驟
A-A、B1-B1、E-E、F-F‧‧‧橫截面
B-B‧‧‧橫截面/方向
結合附圖閱讀以下詳細說明,會最佳地理解本揭露的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1至圖2示出根據一些實施例的半導體晶粒在各種製作階段的剖視圖。
圖3及圖4示出根據一些實施例的圖2所示半導體晶粒的放大圖。
圖5、圖6、圖7A、圖7B、圖7C及圖8示出根據一些實施例的半導體裝置在各種製作階段的各種視圖。
圖9至圖12示出根據一些實施例的半導體裝置在各種製作階段的剖視圖。
圖13、圖14、圖15、圖16、圖17A及圖17B示出根據一些實施例的半導體裝置在各種製作階段的各種視圖。
圖18示出在一些實施例中的具有電磁屏蔽的電氣系統的剖視圖。
圖19示出在一些實施例中的一種用於形成半導體裝置的方法的流程圖。
以下揭露內容提供諸多不同的實施例或實例以用於實作本發明的不同特徵。以下闡述組件及配置形式的具體實例以簡化
本揭露內容。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。
此外,為易於說明,本文中可能使用例如「位於…之下(beneath㊣)」、「下方(be1ow㊣)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述如圖所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
圖1至圖2示出根據一些實施例的半導體晶粒在各種製作階段的剖視圖。在圖1中,在半導體晶圓30’中形成多個半導體晶粒30(參見圖2),所述多個半導體晶粒30亦可被稱為積體電路晶粒或晶粒。可在半導體晶圓30’中形成數十個、數百個、或甚至更多半導體晶粒30,且將對半導體晶粒30進行單體化(參見圖2),以形成多個單獨的半導體晶粒30。
晶圓30’可包括或可為半導體基底,例如經摻雜或未經摻雜的矽或絕緣層上半導體(semiconductor-on-insulator,SOI)基底的主動層。半導體基底可包含其他半導體材料:例如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷
化銦及/或銻化銦;合金半導體,包括矽鍺(SiGe)、磷化鎵砷(GaAsP)、㊣砷化銦鋁(A1InAs)、砷化鎵鋁(A1GaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)及/或磷砷化銦鎵(GaInAsP);或其組合。亦可使用其他基底,例如多層式基底或梯度基底(gradientsubstrate)。可在半導體基底中及/或半導體基底上形成例如電晶體、二極體、電容器、電阻器等裝置且可藉由內連線結構而對所述裝置進行內連,以在半導體晶粒30中形成積體電路,所述內連線結構是由例如位於半導體基底上的一或多個介電層中的金屬化圖案來形成。
半導體晶粒30更包括進行外部連接的接觸接墊101(例如鋁接墊)。接觸接墊101位於可被稱為半導體晶粒30的相應主動側或前側的位置上。鈍化膜103位於半導體晶粒30上且可位於接觸接墊101的一些部分上。開口穿過鈍化膜103而到達接觸接墊101。晶粒連接件105(例如導電柱(例如,包含例如銅等金屬))可延伸至穿過鈍化膜103的開口中,且機械地及電性地耦合至相應接觸接墊101。可藉由例如電鍍等來形成晶粒連接件105。晶粒連接件105電性耦合半導體晶粒30的相應積體電路。在以下說明中,晶粒連接件105亦可被稱為導電柱105。
介電材料107位於半導體晶粒30的主動側上、例如位於鈍化膜103及晶粒連接件105上。介電材料107在側向上包封晶粒連接件105。介電材料107可為聚合物,例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺(polymide)、苯並環丁烯
(benzocyclobutene,BCB)等;氮化物,例如氮化矽等;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)等;或其組合,並且可例如藉由旋塗、疊層、化學氣相沈積(chemical vapor deposition,CVD)等形成。在圖1所示實例中,介電材料107的頂表面距接觸接墊101延伸得較導電柱105的頂表面距接觸接墊101來得更遠。
接下來,在圖2中,將晶圓30’的前側貼合至膠帶108(例如切割膠帶),且沿線31進行單體化以形成多個晶粒30。在晶粒30的後側(例如,與前側相對的側)之上以及在晶粒30的側壁之上形成導電塗層109,導電塗層109包括銅層或能夠提供電磁屏蔽以減少電磁干擾(electromagnetic interference,EMI)或減小電磁敏感度(electromagnetic susceptibility,EMS)的其他適合的材料。導電塗層109可包括一或多個子層(參見圖3及圖4),且所述子層中的至少一者可包含適合的金屬,例如銅。在一些實施例中,在晶粒30的後側及側壁之上共形地形成導電塗層109。儘管圖2中未示出,然而亦可在膠帶108的上表面之上形成導電塗層109。導電塗層109在以下說明中亦可被稱為金屬塗層109。
圖3及圖4分別示出在一些實施例中的圖2所示半導體晶粒30的區域150及區域140的放大圖。圖3及圖4所示導電塗層109的結構僅為非限制性實例,且其他數目的子層及/或其他結構亦為可能的,並且完全旨在包含於本揭露的範圍內。
如圖3所示,導電塗層109包括三個子層,例如介面層159、障壁層157、及導電層154。介面層159形成於晶粒30的後側及側壁上,例如形成於晶粒30與障壁層157之間。介面層159可包含適合的材料(例如氧化矽),且可藉由熱氧化、化學氣相沈積、物理氣相沈積(physical vapor deposition,PVD)、其組合等、或其他適合的形成方法來形成。介面層159可充當半導體晶粒30與隨後形成的層(例如,157)之間的黏著層,且可有助於隨後形成的層(例如,157及154)黏附至半導體晶粒30。
如圖3所示,在介面層159之上形成障壁層157。障壁層157可被形成以防止或減少金屬塗層109的材料(例如,銅)擴散至例如半導體晶粒30的基底中。在一些實施例中,障壁層157包含氮化鈦,但作為另一選擇可利用其他材料,例如氮化鉭、氧化鈦、氧化鉭、鈦、鉭等。可利用化學氣相沈積製程(例如電漿增強型化學氣相沈積(plasma-enhanced CVD,PECVD))來形成障壁層157。然而,作為另一選擇可利用其他替代製程,例如濺鍍(sputtering)或金屬有機化學氣相沈積(metal organic chemicalvapor deposition,MOCVD)、原子層沈積(atomic layer deposition,ALD)。
接下來,在障壁層157之上形成導電層154。導電層154可包含適合的金屬(例如銅),且可具有處於約3微米與約5微米之間的厚度,例如為約3微米,但其他尺寸亦為可能的。可利用適合的沈積方法(例如濺鍍、噴塗(spraying)、或電鍍)來形成
導電層154。在一些實施例中,在障壁層157之上形成晶種層(圖中未示出),接著利用電鍍製程在所述晶種層之上形成導電層154。
在其中藉由對半導體晶粒30的基底(例如,矽)進行熱氧化來形成介面層159(例如,氧化矽)的實施例中,半導體晶粒30的區域140中的導電塗層109可具有與區域150中的導電塗層109不同的結構,如圖4所示。區域140中的導電塗層109對應於沿晶粒30的介電材料107的側壁設置的導電塗層109的部分。由於熱氧化製程不在介電材料107之上產生例如氧化矽,因此不在區域140中形成圖3所示的介面層159。因此,區域140中的導電塗層109包括兩者皆為導電層的障壁層157及導電層154。
圖5、圖6、圖7A、圖7B、圖7C及圖8示出根據一些實施例的半導體裝置200在各種製作階段的各種視圖。在圖5中,藉由黏著劑層121將如圖2所示的具有金屬塗層109的晶粒30貼合至載體120,其中晶粒30的前側背對載體120。亦將第二晶粒40(可為具有與晶粒30不同的功能性的晶粒)貼合至載體120,其中晶粒40的前側背對載體120。
載體120可由例如矽、聚合物、聚合物複合物、金屬箔、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、膠帶或其他適合於結構性支撐的材料等材料製成。在一些實施例中,在載體120之上沈積或疊層黏著劑層121。黏著劑層121可為感光性的且可在隨後的載體剝離製程中藉由在載體120上照射例如紫外(ultra-violet,UV)光而輕易地自載體120脫離。舉例而言,黏著劑層121可為光-熱
轉換(light-to-heat-conversion,LTHC)塗層,其由明尼蘇達州聖保羅的明尼蘇達礦業及製造公司(Minnesota Mining and Manufacturing Company,3M Company)製成。
第二晶粒40可以與上述晶粒30的處理步驟相似的處理步驟來形成,但無金屬塗層109。晶粒40具有位於鈍化膜113中的接觸接墊111、耦合至接觸接墊111的導電柱115、及位於導電柱115之上的介電材料117。晶粒40的接觸接墊111、鈍化膜113、導電柱115及介電材料117可包含分別與晶粒30的接觸接墊101、鈍化膜103、導電柱105及介電材料107相同或相似的材料,且可利用相同或相似的方法來形成。因此不再予以贅述。
在一些實施例中,晶粒30為射頻(radio frequency,RF)晶粒,而晶粒40為數位邏輯晶粒。由於射頻晶粒(例如,晶粒30)可能較邏輯晶粒(例如,晶粒40)更易於受到電磁干擾,因此晶粒30具有金屬塗層109以對晶粒30進行電磁干擾屏蔽。金屬塗層109亦可克制(例如,限制)由晶粒30產生的電磁(electromagnetic,EM)干擾,以使得由晶粒30產生的電磁干擾對其他晶粒(例如,晶粒40)造成很少的干擾或不造成干擾。在所示實施例中,晶粒40不具有金屬塗層109。在其他實施例中,晶粒30及晶粒40兩者皆具有金屬塗層109,且晶粒40遵循與圖1至圖4所示相似的處理步驟來形成。
接下來,在載體120之上以及晶粒30及40周圍形成模塑材料123。所沈積的模塑材料123可在晶粒30及40的上表面之
上延伸。模塑材料123可包含例如環氧樹脂、有機聚合物、添加有或不添加二氧化矽系填料或玻璃填料的聚合物、聚醯胺或其他材料。在一些實施例中,模塑材料123在施加時包含為凝膠型液體的液體模塑化合物(liquid molding compound,LMC)。模塑材料123在施加時亦可包含液體或固體。模塑材料123可利用例如壓縮模塑成形(compressive molding)、轉移模塑成形(transfer molding)或其他方法模塑而成。
模塑材料123一旦沈積之後便可藉由固化製程來固化。固化製程可包括利用退火製程或其他加熱製程將模塑材料123加熱至預定溫度達預定時間段。固化製程亦可包括紫外(UV)光曝光製程、紅外(infrared,IR)能量曝光製程、其組合或其與加熱製程的組合。作為另一選擇,模塑材料123可利用其他方法來固化。在一些實施例中,不執行固化製程。
接下來,可執行平面化製程(例如化學機械研磨(chemical mechanical polish,CMP)),以移除模塑材料123的上部部分,並暴露出晶粒30的導電柱105以及暴露出晶粒40的導電柱115。平面化製程在導電柱(例如,105、115)、介電材料(例如,107、117)、及模塑材料123之間達成實質上共面的上表面。平面化製程可移除介電材料107/117的上部部分,且可更移除導電柱105/115的頂部部分。
接下來,在圖6中,在晶粒30、晶粒40及模塑材料123之上形成重佈線結構130。重佈線結構130包括導電特徵,例如形
成於一或多個介電層132中的一或多層導電線131及通孔133。在一些實施例中,所述一或多個介電層132是由例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene,BCB)等聚合物形成。在其他實施例中,介電層132是由以下材料形成:氮化物,例如氮化矽;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)等;或者類似材料。所述一或多個介電層132可藉由任何可接受的沈積製程(例如旋塗、化學氣相沈積(CVD)、疊層(laminating)等或其組合)來形成。
在一些實施例中,重佈線結構130的導電特徵包括由適合的導電材料(例如銅、鈦、鎢、鋁等)形成的導電線131及/或導通孔(conductive via)133。可藉由以下方式來形成導電特徵:例如,在介電層132中形成開口以暴露出下伏導電特徵,在介電層132之上及在所述開口中形成晶種層,在所述晶種層之上形成具有所設計圖案的經圖案化的光阻,在所設計圖案中及在所述晶種層之上電鍍(例如,電鍍或無電電鍍)導電材料,以及移除光阻及晶種層的非形成所述導電材料的部分。
將重佈線結構130電性耦合至晶粒30及40。可在重佈線結構130之上形成可為球下金屬(under bump metallurgy,UBM)結構的導電接墊137,且將導電接墊137電性耦合至重佈線結構
130。如圖6所示,重佈線結構130的至少一條導電線131A延伸至重佈線結構130的側壁,且在重佈線結構130的側壁處暴露出。導電線131A可用於連接至隨後形成的導電層119(參見圖8)並將導電層119接地。
如圖6所示,晶粒30的金屬塗層109藉由例如通孔133A電性耦合至導電線131A。在一些實施例中,導電線131A電性耦合至接地接觸接墊101A(例如,被配置成連接至電性接地點的接觸接墊),例如圖6所示的晶粒30的最左側接觸接墊或最右側接觸接墊。在一些實施例中,接地接觸接墊101A藉由貼合至導電接墊137A的外部連接件143(例如,參見圖8中的143A)耦合至電性接地點(圖中未示出)。因此,晶粒30的金屬塗層109被接地以對晶粒30提供電磁干擾屏蔽。金屬塗層109亦可防止或減少由晶粒30產生的電磁干擾對系統中的其他晶粒(例如,晶粒40)進行干擾。
圖7A為在實施例中的半導體裝置200的一部分的剖視圖,其示出如圖6所示金屬塗層109的接地的詳細內容。如圖7A所示,接地接觸接墊101A耦合至導電柱105A,所述導電柱105A可被形成為具有延伸部分,所述延伸部分自接地接觸接墊101A延伸至靠近晶粒30的邊緣(例如,側壁)的位置,且因此靠近金屬塗層109,以有利於與金屬塗層109進行電性連接。可形成於重佈線結構130的第一通孔層(例如,重佈線結構130的最靠近晶粒30的通孔層)中的通孔133A將導電柱105A連接至金屬塗層109。
圖7B為圖7A所示半導體裝置200沿橫截面A-A的剖視圖。橫截面A-A橫穿通孔133A,因此導電柱105A及接地接觸接墊101A在橫截面A-A的平面中看不見,且因此在圖7B中以幻象示出。為簡明起見,未在圖7B的俯視圖中示出半導體裝置200的所有層及所有組件。圖7A為圖7B所示半導體裝置200的部分沿橫截面B-B的剖視圖。
如圖7B所示,導電塗層109位於晶粒30的側壁周圍。圖7A所示的接觸接墊101及接地接觸接墊101A被示出位於與圖7B所示橫截面B-B相同的線上。在圖7B中亦示出在圖7A中位於接觸接墊101上方的通孔133及在圖7A中耦合至接地接觸接墊101A的導電柱105A。此外,在圖7B中示出額外的接地接觸接墊101B,額外的接地接觸接墊101B形成於介電材料107中且藉由導電特徵105’(例如,形成於介電材料107中的導電線)電性連接至接地接觸接墊101A。由於接觸接墊101B及導電特徵105’不位於橫截面B-B的線上,因此接觸接墊101B及導電特徵105’在圖7A的剖視圖中看不見。
在圖7B的所示實施例中,通孔133A以與重佈線結構130的其他通孔(例如,通孔133)不同的方式形成,以有利於通孔133A與金屬塗層109之間的電性連接。具體而言,通孔133A可在俯視圖中具有細長形狀而非例如圓形形狀。在一些實施例中,通孔133A的細長形狀沿方向B-B的尺寸大於沿與方向B-B垂直的方向的尺寸。通孔133A的細長形狀為形成通孔133A的圖案所
使用的微影製程的不準確度提供大的容差。舉例而言,細長形狀使得更容易在通孔133A與金屬塗層109之間達成可靠的電性連接,即使通孔133A的實際位置相較於預期位置(例如,所設計位置)向左或向右移動一點(例如,移動幾奈米)。
在圖7B中,通孔133A被示出為具有橢圓形形狀,但亦可使用其他細長形狀,例如矩形形狀、跑道(race track)形狀(例如,在矩形的相對兩側上具有半圓形形狀的矩形,參見133B)及其他適合的形狀。在圖7A的剖視圖中看不見的第二通孔133B連接導電特徵105’與金屬塗層109。第二通孔133B被示出為例如具有跑道形狀。在其他實施例中,第二通孔133B可具有與第一通孔133A相同的形狀(例如,橢圓形形狀),或可具有其他適合的形狀。因此,在圖7B所示實例中,金屬塗層109藉由通孔133A及通孔133B而被接地,因此進一步增加金屬塗層109的接地的可靠性。
圖7C示出圖7A及圖7B所示半導體裝置200的剖視圖,但沿著圖7B的橫截面B1-B1。如圖7C所示,通孔133B電性連接導電特徵105’與金屬塗層109。由於導電特徵105’耦合至接地接觸接墊101A及101B(參見圖7B),因此金屬塗層109被接地。
接下來,在圖8中,在導電接墊137之上形成外部連接件143,剝離載體120,且在模塑材料123的側壁及上表面之上形成導電層119。在一些實施例中,外部連接件143為導電凸塊(例如受控塌縮晶片連接(controlled collapse chip connection,C4)凸
塊或球柵陣列(ball grid array,BGA)凸塊),且可包含例如錫等材料或例如銀或銅等其他適合的材料。在其中外部連接件143為錫焊料凸塊的實施例中,可藉由以下方式來形成外部連接件143:藉由例如蒸鍍(evaporation)、電鍍(electroplating)、印刷、焊料轉移(solder transfer)、植球(ball placement)等任何適合的方法首先形成錫層。一旦已在導電接墊137上形成錫層後,則執行迴焊(reflow)以將所述材料造形成所期望的凸塊形狀。
然而,如此項技術中具有通常知識者將辨識出,儘管外部連接件143已在以上被闡述為受控塌縮晶片連接凸塊或球柵陣列凸塊,然而該些僅旨在為說明性的而並非旨在限制實施例。更確切而言,作為另一選擇可利用任何適合類型的外部接點,例如微凸塊、銅柱、銅層、鎳層、無鉛(lead free,LF)層、無電鍍鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)層、銅/無鉛層、錫/銀層、錫/鉛層、該些的組合等。可對外部連接件143利用任何適合的外部連接件及任何適合的形成外部連接件的製程,且所有此類外部連接件完全旨在包含於實施例的範圍內。
在一些實施例中,在導電接墊137上形成外部連接件143之後,剝離載體120。舉例而言,將形成有外部連接件143的圖6所示結構翻轉成上面朝下,且將外部連接件143貼合至膠帶(例如,切割膠帶,圖中未示出)。在一些實施例中,膠帶為柔軟的,且具有較外部連接件143的高度大的厚度。半導體裝置200因此
可被按壓至膠帶上,以使得外部連接件143被嵌置於(例如,按壓至)所述膠帶中。此可防止半導體裝置200在隨後形成導電層119的處理步驟中電性短路。
接下來,藉由適合的方法(例如(舉例而言)化學濕式蝕刻、電漿乾式蝕刻、機械剝除(mechanical peel-off)、化學機械研磨、機械磨削(mechanical grinding)、熱烘烤、雷射掃描、或濕式剝膜)來剝離載體120。在一些實施例中,載體120為玻璃載體,且藉由在載體120上照射光而被剝離。舉例而言,由準分子雷射(excimer laser)發出的紫外(UV)光可穿過玻璃載體,且在玻璃/黏著劑介面附近被吸收。紫外光起始斷開黏著劑層121中的化學鍵的光化學製程。因此,可容易地移除玻璃載體120。
在其他實施例中,可在形成外部連接件143之前執行載體剝離,例如藉由將重佈線結構130貼合至膠帶並接著移除載體120來執行載體剝離。在載體120被剝離之後,自膠帶移除半導體裝置200並翻轉成上面朝下,且在導電接墊137之上形成外部連接件143。處理步驟的該些及其他變形完全旨在包含於本揭露的範圍內。在其中同時形成多個半導體裝置200的實施例中,執行單體化製程(圖中未示出)來形成多個單獨的半導體裝置200。
接下來,利用例如電鍍、濺鍍、噴塗或其他適合的形成方法在半導體裝置200之上形成導電層119,導電層119可包含銅或其他適合的用於電磁干擾防護的材料。導電層119的厚度可介於約3微米至約5微米範圍內,例如為3微米,但其他尺寸亦為
可能的。
如圖8所示,在晶粒30/40的後側上(例如,在黏著劑層121之上)以及沿模塑材料123的側壁形成導電層119。由於導電層119(亦可被稱為金屬塗層119)不接觸晶粒30及40的基底,因此可無需擔憂導電層119的材料的擴散(例如,銅擴散),且因此可在形成導電層119時省略與障壁層157(參見圖3)相似的障壁層。因此,與具有下伏障壁層157及下伏介面層159的導電塗層109(參見圖3)不同,在一些實施例中,可在模塑材料123的側壁之上以及黏著劑層121之上形成導電層119而導電層119與晶粒30/40之間無障壁層。在一些實施例中,導電層119具有單層式結構,且由適合的材料(例如銅)形成,在所述情形中,導電層119(例如,銅)直接接觸例如模塑材料123、黏著劑層121、及所述一或多個介電層132。在一些實施例中,端視例如導電層119的材料而定,導電層119與例如模塑材料123、黏著劑層121及所述一或多個介電層132之間可存在介面層。
如圖8所示,在一些實施例中,導電層119藉由耦合至導電線131A而被接地,導電線131A在重佈線結構130的側壁處暴露出。圖8亦示出重佈線結構130的通孔133A,所述通孔133A耦合至位於晶粒30之上的導電塗層109(與圖7A及圖7B相似)。因此,導電層119及導電塗層109藉由耦合至一或多個接地接觸接墊101A而被電性接地,所述一或多個接地接觸接墊101A藉由例如連接至電性接地點的一或多個外部連接件143A而被接地。
圖9至圖12示出根據一些實施例的半導體裝置300在各種製作階段的剖視圖。圖9至圖12中的相似的編號表示與圖3至圖8中相似的部分,因此不再予以贅述。如圖9所示,經由黏著劑層121將半導體晶粒30及40分別貼合至載體120。應注意,在圖9所示實例中,晶粒30及40在貼合至載體120之前不被塗佈以導電塗層109。晶粒30與晶粒40可為相同的類型(例如,具有相同的功能性)或為不同的類型(例如,具有不同的功能性)。在晶粒30及40被貼合至載體120之後,在晶粒30、晶粒40及載體120之上共形地形成導電塗層109。
在圖9中,導電塗層109的在區150’中的部分(例如,導電塗層109中與晶粒30及40的半導體基底接觸的部分)可具有與圖3所示相同的結構。另外,導電塗層109的其他部分(例如,導電塗層109中位於介電材料107之上、位於黏著劑層121之上及位於載體120之上的部分)可具有與圖4所示相同的結構。
接下來,如圖10所示,在載體120之上以及晶粒30/40周圍形成模塑材料123。可執行固化製程,以對模塑材料123進行固化。接下來,例如藉由化學機械研磨製程對(經固化的)模塑材料123進行平面化,以暴露出晶粒30的導電柱105及晶粒40的導電柱115。平面化製程會移除導電塗層109中位於晶粒30及40的前側之上的部分。因此,在圖10的剖視圖中,在平面化之後,導電塗層109的剩餘部分在晶粒30與晶粒40之間具有U形狀,且鄰近晶粒30及40的外側壁(例如,鄰近半導體裝置300的邊
緣的側壁)具有L形狀。
接下來,在圖11中,在晶粒30及40的前側之上形成重佈線結構130,且將重佈線結構130電性耦合至晶粒30及40。重佈線結構130包括導電線131及通孔133。在重佈線結構130的上表面之上形成可為球下金屬結構的導電接墊137。重佈線結構130的至少一條導電線131A在重佈線結構130的側壁處暴露出。
在圖11所示實例中,與圖7A及圖7B所示實施例相似,導電塗層109藉由連接至重佈線結構130(例如,藉由通孔133A)及連接至接地接觸接墊101A而被接地。導電塗層109亦可藉由重佈線結構130電性耦合至晶粒40的接地接觸接墊111A,如圖11所示。
接下來,如圖12所示,在導電接墊137之上形成外部連接件143,剝離載體120,且在晶粒30/40的後側之上(例如,在黏著劑層121之上)以及在模塑材料123的側壁之上形成導電層119。在一些實施例中,導電層119藉由耦合至被重佈線結構130的側壁暴露出的導電線131A而被接地。
在一些實施例中,導電層119共形地形成,且可具有與亦被共形地形成的導電塗層109的厚度相等的厚度。應注意,在區119D中,導電層119與導電塗層109合併而形成了相較於除了區119D以外的區中的導電層119或導電塗層109來的厚(例如,為約兩倍厚)的導電層(例如,銅)。舉例而言,晶粒30與晶粒40之間的(經合併的)導電層的厚度可為沿晶粒30及40的側壁
的導電塗層109的厚度的兩倍。作為另一實例,晶粒30與晶粒40之間的(經合併的)導電層的厚度可為沿模塑材料123的側壁或位於黏著劑層121之上的導電層119的厚度的兩倍。在圖12的剖視圖中,導電層119及導電塗層109在晶粒30與晶粒40之間以及鄰近晶粒30及40的外側壁形成U形狀。在其他實施例中,導電層119與導電塗層109具有不同的厚度。
圖13、圖14、圖15、圖16、圖17A及圖17B示出根據一些實施例的半導體裝置400在各種製作階段的各種視圖。在圖13中,在載體120之上形成介電膜(例如感光性介電層)。使用微影及/或蝕刻製程對介電膜進行圖案化以形成結構151及153。在一些實施例中,由於所使用的微影製程,圖13的剖視圖中的結構151(或153)的寬度隨著結構151(或153)延伸遠離載體120而減小。舉例而言,結構151及153如圖13所示具有梯形橫截面。以下闡述結構151/153的更多詳細內容。
在圖14中,在圖13所示結構之上形成導電層155,例如銅或其他適合的能夠提供電磁干擾屏蔽及/或防護的材料。導電層155可包含金屬(例如,銅),且可藉由濺鍍、噴塗、電鍍或其他適合的方法來形成。在一些實施例中,導電層155的厚度處於約3微米與約5微米之間,但其他尺寸亦為可能的。
在一些實施例中,結構151為介電結構。暫時參考作為半導體裝置400沿圖17A所示橫截面E-E的剖視圖的圖17B,結構151可包括圍繞晶粒30及/或晶粒40的介電結構。在一些實施
例中,結構151可為如圖17B所示包圍晶粒30及/或晶粒40的連續介電結構。在其他實施例中,結構151可包括包圍晶粒30及/或晶粒40的介電結構的多個分立的區段(例如,之間具有間隙的區段,圖中未示出)。儘管結構151由介電材料製成,然而在被塗佈以導電層155之後,經塗佈的結構151在半導體晶粒30/40周圍形成電磁屏蔽結構,以防止或減少電磁干擾(參見圖17A及圖17B)。
返回參考圖14,在一些實施例中,結構153為介電結構,且具有實質上柱體形狀或截頭錐形狀。在一些實施例中,在被塗佈以導電層155之後,每一經塗佈的結構153會形成導通孔。暫時參考圖17B,根據一些實施例,經塗佈的結構153包括實心介電芯體(例如,結構153),在介電芯體的外側壁上塗佈有導電層155。
現在參考圖15,藉由黏著劑層121將半導體晶粒30及40貼合至載體120。接下來,沈積模塑材料123,若需要則進行固化,且接著進行平面化以暴露出晶粒30/40的導電柱105/115。平面化製程亦移除導電層155的頂部部分(例如,導電層155的位於結構151/153的遠離載體120的上表面之上的部分),且暴露出結構151及153的介電材料,如圖15所示。
接下來,在圖16中,在晶粒30及40的前側之上形成重佈線結構130。重佈線結構130可包括導電線131及通孔133。在重佈線結構130之上形成導電接墊137且將導電接墊137電性耦
合至重佈線結構130。如圖16所示,導電層155藉由經由例如通孔133A電性連接至重佈線結構130而被接地,所述重佈線結構130包括耦合至接地接觸接墊101A/111A的導電線及/或通孔,接地接觸接墊101A/111A繼而耦合至被電性接地的一或多個外部連接件143(參見圖17A)。在一些實施例中,重佈線結構130的導電線131A在重佈線結構130的側壁處暴露出。
接下來,在圖17A中,形成外部連接件143,剝離載體120,且藉由適合的磨削製程及/或蝕刻製程(例如化學機械研磨)來使載體剝離之後的半導體裝置400的被暴露表面(例如,鄰近晶粒30/40的後側的表面)凹陷。在一些實施例中,凹陷製程會移除導電層155中位於晶粒30及40的後側之上的部分。凹陷製程亦可移除黏著劑層121。因此,在一些實施例中,在凹陷製程之後,暴露出鄰近晶粒30及40的後側的結構151/153的介電材料。
接下來,在晶粒30及40的後側之上形成另一重佈線結構160,且可以是利用與重佈線結構130相同或相似的形成方法來形成。重佈線結構160包括導電線161及通孔163,導電線161及通孔163電性耦合至導電層155的剩餘部分,例如導電層155的位於結構151的側壁之上及位於結構153的側壁之上的部分。在一些實施例中,重佈線結構160的導電線161’包括接地平面。接地平面(例如,161’)與具有導電層155的結構151在晶粒30及40周圍以及晶粒30及40之上形成電磁干擾屏蔽。電磁干擾屏蔽會減少對晶粒30及40的電磁干擾。電磁干擾屏蔽亦可克制由
晶粒30及40產生的電磁干擾,且因此會減少由晶粒30及40產生的電磁干擾。
如圖17A所示,在重佈線結構160中形成開口164。開口164可藉由雷射鑽孔、蝕刻或其他適合的方法來形成。在一些實施例中,開口164暴露出導電線161的部分,導電線161的所述部分電性耦合至位於結構153之上的導電層155以電性耦合重佈線結構130與重佈線結構160。導電線161的被暴露部分亦提供對晶粒30及40的後側處的電性連接的觸及。舉例而言,可將另一半導體裝置(圖中未示出)植放於半導體裝置40上方,且電性地及機械地耦合至導電線161的被暴露部分以形成疊層封裝。
圖17B為圖17A所示半導體裝置400沿橫截面E-E的剖視圖,且圖17A為圖17B所示半導體裝置400沿橫截面F-F的剖視圖。為清晰起見,模塑材料123未在圖17B中示出。如圖17B所示,結構151包括位於晶粒30及40周圍的連續結構,且在結構151的相對側壁上形成導電層155。圖17B亦示出可具有圓形橫截面的結構153以及在結構153的側壁之上形成的導電層155。
圖17B僅為結構151及結構153的非限制性實例,並且結構151及結構153的其他形狀及/或橫截面亦為可能的,且完全旨在包含於本揭露的範圍內。舉例而言,結構151可包括集體地圍繞晶粒30及40的介電區的多個分立的(例如,單獨的)區段。作為另一實例,結構153的橫截面可具有其他適合的形狀,例如橢圓形形狀、正方形形狀或矩形形狀。
圖18示出具有電磁干擾防護的電氣系統500。電氣系統500包括半導體裝置510,半導體裝置510相似於圖8所示半導體裝置200,但對於晶粒30及晶粒40二者而言具有金屬塗層509。金屬塗層509可相似於圖8所示金屬塗層109。半導體裝置510更具有導電層519,導電層519可相似於圖8所示導電層119。電氣系統500更包括基底520,基底520可為其中及/或其上形成有導電跡線(例如,521/523/525)及導電接墊(例如,527)的印刷電路板(printed circuit board,PCB)。圖18更示出機械地及電性地耦合至基底520的連接件530(例如,射頻連接件)。如圖18所示,連接件530具有訊號端子533及接地端子531。訊號端子531可為用於載送射頻訊號(例如,待經電氣系統500處理的射頻輸入訊號)的端子,接地端子531可被電性接地。在一些實施例中,接地端子531為位於訊號端子533周圍的金屬殼或金屬網格以提供良好的電磁干擾防護。
如圖18所示,半導體裝置510的兩個外部連接件541及545被電性接地,且分別連接至基底520的導電線521及525,所述導電線521及525耦合至連接件530的接地端子531。連接件530的訊號端子533連接至半導體裝置510的外部連接件543,所述外部連接件543用於與訊號(例如,來自連接件530的射頻輸入訊號)進行連接。在一些實施例中,導電線521及525為接地平面,且載送射頻訊號的導電線523設置於接地平面521與接地平面525之間。系統500具有優異的電磁干擾防護。舉例而言,
存在對半導體裝置510的雙重電磁干擾屏蔽(例如,導電塗層509及導電層519)。另外,設置於導電線523上方及下方的接地平面521及525為載送射頻訊號的導電線523提供增強的電磁干擾隔離。該些特徵與對由接地端子531提供的訊號端子533的電磁干擾屏蔽相結合在電氣系統500的整個訊號鏈上提供良好的電磁干擾防護,因此提供優異的抵抗電磁干擾的穩健性。
對所揭露的實施例的變形亦為可能的,且完全旨在包含於本揭露的範圍內。舉例而言,例如在半導體裝置中使用兩個半導體晶粒(例如,30及40)。然而,可在所形成的半導體裝置中使用多於或少於兩個晶粒。作為另一實例,結構151(參見圖17B)的形狀可包括兩個單獨的環,其中所述環中的每一者圍繞晶粒30/40中的一者。另外,所述兩個單獨的環中的每一者可為連續環或由多個分立的區段形成的環。作為再一實例,在不背離本揭露的精神條件下,結構153的數目及位置可相對於圖17B所示的數目及位置而改變。
圖19示出根據一些實施例的一種用於形成半導體裝置的方法的流程圖。應理解,圖19所示的實施例方法僅為諸多可能的實施例方法的實例。此項技術中具有通常知識者將辨認出諸多變形、替代形式以及潤飾。舉例而言,可對如圖19所示的各個步驟進行添加、移除、替換、重新配置以及重覆。
參考圖19,在步驟1010中,將第一晶粒貼合至載體,其中位於所述第一晶粒的前側上的接觸接墊背對所述載體。在步驟
1020中,在所述載體之上以及在所述第一晶粒周圍形成模塑材料。在步驟1030中,在所述模塑材料的遠離所述載體的第一側之上形成重佈線結構,其中所述重佈線結構包括導電線,所述導電線電性耦合至所述第一晶粒,其中所述重佈線結構的第一導電特徵在所述重佈線結構的側壁處暴露出。在步驟1040中,剝離所述載體。在步驟1050中,沿所述模塑材料的側壁以及所述模塑材料的與所述第一側相對的第二側形成第一導電塗層,其中所述第一導電塗層電性連接至所述重佈線結構的所述第一導電特徵。
所揭露的實施例具有諸多優點。位於半導體晶粒30/40之上的金屬塗層109及/或位於模塑材料123的外表面之上的金屬塗層119提供電磁干擾防護,且因此所形成的半導體裝置具有較佳的抵抗電磁干擾的效能。所揭露的電磁干擾防護結構可容易與現有的製造流程整合在一起,且需要很少的額外空間或不需要額外空間來容置電磁干擾防護結構,因此使得能夠達成具有小的尺寸及增強的電磁干擾防護的低成本封裝。用於連接至金屬塗層(例如,109)的特徵(例如細長通孔133A(參見圖7B))使得能夠達成微影製程的較大誤差裕度(margin),且為金屬塗層提供更可靠的接地。所揭露的電磁干擾防護/隔離結構亦會簡化對所形成的半導體裝置的電磁效能的分析,且因此用於分析半導體裝置的電磁效能的模擬時間會大大減少,此繼而會減小設計週期並減少產品推向市場的時間。分析顯示出接近完美的法拉第籠(Faraday cage)可藉由連接金屬塗層(例如,109)與重佈線結構的第一通孔層(例
如,通孔133A)處的電性接地點來達成。雙重金屬塗層結構(例如,109及119)藉由使用外部金屬塗層(例如,119)來進一步減少到達半導體裝置的電磁干擾而達成電磁效能的提高。
在實施例中,一種半導體裝置包括:第一晶粒,嵌置於模塑材料中,其中所述第一晶粒的接觸接墊鄰近所述模塑材料的第一側;重佈線結構,位於所述模塑材料的所述第一側之上;第一金屬塗層,沿所述第一晶粒的側壁以及位於所述第一晶粒與所述模塑材料之間;以及第二金屬塗層,沿所述模塑材料的側壁以及位於所述模塑材料的與所述第一側相對的第二側上。在實施例中,所述第一金屬塗層及所述第二金屬塗層電性連接至接地接點。在實施例中,所述重佈線結構包括通孔,所述通孔電性耦合至所述第一金屬塗層。在實施例中,所述通孔具有沿第一方向的第一尺寸及沿與所述第一方向垂直的第二方向的第二尺寸,所述第二尺寸小於所述第一尺寸。在實施例中,所述第一晶粒具有多個導電柱,所述多個導電柱分別耦合至所述接觸接墊中的一者,其中所述多個導電柱中的至少一者電性耦合至所述第一金屬塗層。在實施例中,所述多個導電柱的遠離所述接觸接墊的上表面與所述模塑材料的所述第一側齊平。在實施例中,所述第二金屬塗層電性耦合至所述重佈線結構的導電線,其中所述導電線在所述重佈線結構的側壁處暴露出。在實施例中,所述半導體裝置更包括第二晶粒,所述第二晶粒嵌置於所述模塑材料中且在側向上與所述第一晶粒間隔開,其中所述第二晶粒的接觸接墊電性耦合
至所述重佈線結構。在實施例中,所述第二晶粒的側壁不具有金屬塗層。在實施例中,所述第一晶粒與所述第二晶粒具有不同的功能性。在實施例中,所述第一金屬塗層自所述第一晶粒的所述側壁連續延伸至所述第二晶粒的側壁。
在實施例中,一種半導體裝置包括:第一晶粒,位於模塑層中;第一重佈線結構,位於所述模塑層的第一側上且包括導電線,所述導電線電性耦合至所述第一晶粒的接觸接墊;第二重佈線結構,位於所述模塑層的與所述第一側相對的第二側上;第一導電結構,位於所述模塑層中且在側向上與所述第一晶粒間隔開,其中所述第一導電結構包括:第一介電區,位於所述第一晶粒周圍;以及導電塗層,位於所述第一介電區的相對兩側上;以及通孔,位於所述模塑層中,其中所述通孔耦合至所述第一重佈線結構的第一導電線及所述第二重佈線結構的第二導電線。在實施例中,所述通孔包括第二介電區;以及第二導電塗層,位於所述第二介電區的側壁上。在實施例中,所述通孔位於所述第一晶粒與所述第一導電結構之間。在實施例中,所述第一導電結構電性耦合至所述第一重佈線結構的至少一條導電線及所述第二重佈線結構的至少一條導電線。在實施例中,所述第二重佈線結構包括接地平面,且所述第一導電結構電性耦合至所述接地平面。
在實施例中,一種形成半導體裝置的方法包括:將第一晶粒貼合至載體,其中位於所述第一晶粒的前側上的接觸接墊背對所述載體;在所述載體之上以及所述第一晶粒周圍形成模塑材
料;在所述模塑材料的遠離所述載體的第一側之上形成重佈線結構,其中所述重佈線結構包括導電線,所述導電線電性耦合至所述第一晶粒,其中所述重佈線結構的第一導電特徵在所述重佈線結構的側壁處暴露出;剝離所述載體;以及沿所述模塑材料的側壁以及所述模塑材料的與所述第一側相對的第二側形成第一導電塗層,其中所述第一導電塗層電性連接至所述重佈線結構的所述第一導電特徵。在實施例中,所述方法更包括在將所述第一晶粒貼合至所述載體之前在所述第一晶粒的側壁及後側之上形成第二導電塗層。在實施例中,所述第一晶粒具有導電柱,所述導電柱位於所述第一晶粒的所述接觸接墊之上且電性耦合至所述第一晶粒的所述接觸接墊,其中所述導電柱中的第一導電柱延伸至所述第一晶粒的邊緣,其中所述導電柱中的所述第一導電柱經由所述重佈線結構的通孔電性耦合至所述第二導電塗層。在實施例中,所述重佈線結構的通孔電性耦合至所述第二導電塗層。在實施例中,所述通孔被形成為在俯視圖中具有橢圓形形狀。
在實施例中,一種形成半導體裝置的方法包括:在載體上形成第一介電結構;在所述第一介電結構之上形成導電層;將第一晶粒貼合至所述載體,其中所述第一晶粒在側向上與所述第一介電結構分隔開;將所述第一晶粒及所述第一介電結構包封於模塑層中;在所述模塑層的第一側上形成第一重佈線結構,所述第一重佈線結構包括導電線,所述導電線電性耦合至所述第一晶粒的接觸接墊並耦合至位於所述第一介電結構之上的所述導電
層;剝離所述載體;以及在所述模塑層的與所述第一側相對的第二側上形成第二重佈線結構,所述第二重佈線結構包括導電線,所述導電線電性耦合至位於所述第一介電結構之上的所述導電層。在實施例中,所述方法更包括:在包封所述第一晶粒及所述第一介電結構之後且在形成所述第一重佈線結構之前,使所述模塑層自所述模塑層的所述第一側凹陷,其中所述凹陷暴露出所述第一晶粒的導電柱及所述第一介電結構的第一表面。在實施例中,所述方法更包括:在剝離所述載體之後,使所述模塑層自所述模塑層的所述第二側凹陷,其中所述凹陷暴露出所述第一介電結構的與所述第一介電結構的所述第一表面相對的第二表面。在實施例中,所述方法更包括:在所述載體上形成第二介電結構,其中所述第二介電結構是由與所述第一介電結構相同的介電材料製成,其中所述導電層形成於所述第二介電結構之上,且其中位於所述第二介電結構之上的所述導電層電性耦合於所述第一重佈線結構的所述導電線與所述第二重佈線結構的所述導電線之間。
在實施例中,一種半導體裝置包括:第一晶粒;第二晶粒,在側向上與所述第一晶粒間隔開;模塑材料,其中所述第一晶粒及所述第二晶粒被所述模塑材料圍繞;重佈線結構,位於所述模塑材料的第一側之上,其中所述重佈線結構的導電線在所述重佈線結構的側壁處暴露出;以及第一導電層,位於所述模塑材料的側壁上以及所述模塑材料的與所述第一側相對的第二側上,其中所述第一導電層電性連接至所述重佈線結構的所述導電線。
在實施例中,所述半導體裝置更包括第二導電層,所述第二導電層沿所述第一晶粒的側壁。在實施例中,所述第二晶粒的側壁不具有所述第二導電層。
在實施例中,一種封裝體包括:基底;連接件,電性耦合至所述基底的第一導電接墊,所述連接件包括訊號端子及接地端子;以及半導體裝置,電性耦合至所述基底的第二導電接墊,其中所述半導體裝置包括第一晶粒,嵌置於模塑材料中,所述第一晶粒在所述第一晶粒的側壁上具有第一導電塗層;重佈線結構,位於所述模塑材料的第一側上,所述重佈線結構具有電性耦合至所述第一晶粒的導電線;第二導電塗層,沿所述模塑材料的側壁以及所述模塑材料的與所述第一側相對的第二側;以及外部連接件,貼合至所述重佈線結構,其中所述外部連接件包括訊號連接件、第一接地連接件及第二接地連接件,其中所述訊號連接件藉由所述基底的導電線耦合至所述訊號端子,其中所述第一接地連接件及所述第二接地連接件分別藉由所述基底的第一接地平面及第二接地平面耦合至所述接地端子,其中所述導電線位於所述第一接地平面與所述第二接地平面之間。在實施例中,所述連接件為射頻(RF)連接件。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應理解,其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實
施例相同的優點。熟習此項技術者亦應認識到,此類等效構造並不背離本揭露的精神及範圍,而且他們可在不背離本揭露的精神及範圍條件下對其作出各種改變、代替及變更。
Claims (12)
- 一種半導體裝置,包括:第一晶粒,嵌置於模塑材料中,其中所述第一晶粒的接觸接墊鄰近所述模塑材料的第一側;重佈線結構,位於所述模塑材料的所述第一側之上;第一金屬塗層,沿所述第一晶粒的側壁以及位於所述第一晶粒與所述模塑材料之間;以及第二金屬塗層,沿所述模塑材料的側壁以及位於所述模塑材料的與所述第一側相對的第二側上,其中所述第一金屬塗層經由所述重佈線結構連接至所述第二金屬塗層。
- 如申請專利範圍第1項所述的半導體裝置,其中所述第一金屬塗層及所述第二金屬塗層電性連接至接地接點。
- 如申請專利範圍第1項所述的半導體裝置,其中所述重佈線結構包括通孔,所述通孔電性耦合至所述第一金屬塗層。
- 如申請專利範圍第3項所述的半導體裝置,其中所述通孔具有沿第一方向的第一尺寸及沿與所述第一方向垂直的第二方向的第二尺寸,所述第二尺寸小於所述第一尺寸。
- 如申請專利範圍第1項所述的半導體裝置,其中所述第一晶粒具有多個導電柱,所述多個導電柱分別耦合至所述接觸接墊中的一者,其中所述多個導電柱中的至少一者電性耦合至所述第一金屬塗層。
- 如申請專利範圍第1項所述的半導體裝置,其中所述第二金屬塗層電性耦合至所述重佈線結構的導電線,其中所述導電線在所述重佈線結構的側壁處暴露出。
- 一種半導體裝置,包括:第一晶粒,位於模塑層中;第一重佈線結構,位於所述模塑層的第一側上且包括導電線,所述導電線電性耦合至所述第一晶粒的接觸接墊;第二重佈線結構,位於所述模塑層的與所述第一側相對的第二側上;第一導電結構,位於所述模塑層中且在側向上與所述第一晶粒間隔開,其中所述第一導電結構包括:第一介電區,位於所述第一晶粒周圍;以及第一導電塗層及第二導電塗層,位於所述第一介電區的相對兩側上,其中所述第一導電塗層圍繞所述第一晶粒,且所述第二導電塗層圍繞所述第一導電塗層和所述第一晶粒;以及通孔,位於所述模塑層中,其中所述通孔耦合至所述第一重佈線結構的第一導電線及所述第二重佈線結構的第二導電線。
- 如申請專利範圍第7項所述的半導體裝置,其中所述通孔包括:第二介電區;以及第三導電塗層,位於所述第二介電區的側壁上。
- 如申請專利範圍第7項所述的半導體裝置,其中所述第一導電結構電性耦合至所述第一重佈線結構的至少一條導電線及所述第二重佈線結構的至少一條導電線。
- 如申請專利範圍第9項所述的半導體裝置,其中所述第二重佈線結構包括接地平面,且所述第一導電結構電性耦合至所述接地平面。
- 一種形成半導體裝置的方法,包括:將第一晶粒貼合至載體,其中位於所述第一晶粒的前側上的接觸接墊背對所述載體;在所述載體之上以及所述第一晶粒周圍形成模塑材料;在所述模塑材料的遠離所述載體的第一側之上形成重佈線結構,其中所述重佈線結構包括導電線,所述導電線電性耦合至所述第一晶粒,其中所述重佈線結構的第一導電特徵在所述重佈線結構的側壁處暴露出;剝離所述載體;沿所述模塑材料的側壁以及所述模塑材料的與所述第一側相對的第二側形成第一導電塗層,其中所述第一導電塗層電性連接至所述重佈線結構的所述第一導電特徵;以及在將所述第一晶粒貼合至所述載體之前在所述第一晶粒的側壁及後側之上形成第二導電塗層,其中所述第二導電塗層經由所述重佈線結構連接至所述第一導電塗層。
- 如申請專利範圍第11項所述的方法,其中所述第一晶粒具有導電柱,所述導電柱位於所述第一晶粒的所述接觸接墊之上且電性耦合至所述第一晶粒的所述接觸接墊,其中所述導電柱中的第一導電柱延伸至所述第一晶粒的邊緣,其中所述導電柱中的所述第一導電柱經由所述重佈線結構的通孔電性耦合至所述第二導電塗層。
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Also Published As
Publication number | Publication date |
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US20210134734A1 (en) | 2021-05-06 |
US10867936B2 (en) | 2020-12-15 |
KR20190003293A (ko) | 2019-01-09 |
US10510682B2 (en) | 2019-12-17 |
US20190109096A1 (en) | 2019-04-11 |
US20190006288A1 (en) | 2019-01-03 |
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