TW201826403A - 基底晶圓上晶片結構的形成方法 - Google Patents

基底晶圓上晶片結構的形成方法 Download PDF

Info

Publication number
TW201826403A
TW201826403A TW106117530A TW106117530A TW201826403A TW 201826403 A TW201826403 A TW 201826403A TW 106117530 A TW106117530 A TW 106117530A TW 106117530 A TW106117530 A TW 106117530A TW 201826403 A TW201826403 A TW 201826403A
Authority
TW
Taiwan
Prior art keywords
substrate
die
package
connector
interposer
Prior art date
Application number
TW106117530A
Other languages
English (en)
Inventor
陳偉銘
吳集錫
丁國強
侯上勇
俞篤豪
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201826403A publication Critical patent/TW201826403A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4817—Conductive parts for containers, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32106—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供一種基底晶圓上晶片結構及其形成方法。所述方法包括將第一晶粒及第二晶粒貼合至中介層。所述方法還包括將第一基底貼合至所述第一晶粒的第一表面及所述第二晶粒的第一表面。所述第一基底包含矽。所述第一晶粒的所述第一表面與所述第一晶粒的貼合至所述中介層的表面相對，且所述第二晶粒的所述第一表面與所述第二晶粒的貼合至所述中介層的表面相對。所述方法包括將所述中介層結合至第二基底。

Description

基底晶圓上晶片結構的形成方法
本發明實施例是有關於一種基底晶圓上晶片結構及其形成方法。
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的積體密度的持續提高，半導體行業已經歷快速增長。在很大程度上，積體密度的此種提高來自於最小特徵尺寸（minimum feature size）的重複減小（例如，使半導體製程節點朝亞20奈米節點（sub-20 nm node）縮減），此使得更多元件能夠積體在給定區域中。近來，隨著對微型化、較高速度、及較大頻寬、以及較低功耗及延時的需求的增長，需要更小且更具創造性的半導體晶粒封裝技術。
隨著半導體技術的進一步發展，已出現作為用以進一步減小半導體裝置的實體尺寸的有效替代方式的堆疊半導體裝置（例如，三維積體電路（three dimensional integrated circuit，3DIC））。在堆疊半導體裝置中，例如邏輯電路、記憶體電路、處理器電路等主動電路被製作於不同的半導體晶圓上。兩個或更多個半導體晶圓可在彼此頂上進行安裝或堆疊，以進一步減小半導體裝置的形狀因數（form factor）。
本發明實施例的一種基底晶圓上晶片結構的形成方法，包括：將第一晶粒及第二晶粒貼合至中介層；將第一基底貼合至所述第一晶粒的第一表面及所述第二晶粒的第一表面，所述第一基底包含矽，所述第一晶粒的所述第一表面與所述第一晶粒的貼合至所述中介層的表面相對，且所述第二晶粒的所述第一表面與所述第二晶粒的貼合至所述中介層的表面相對；以及將所述中介層結合至第二基底。
以下公開內容提供用於實作本發明的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“之下（beneath）”、“下面（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或處於其他取向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據某些實施例，提供基底晶圓上晶片（chip on wafer on substrate，COWOS）封裝100。在製造期間，基底可貼合至被封裝於COWOS結構中的晶粒的背側。在製造期間，基底可保護晶粒，且可減輕封裝翹曲（package warpage）。這樣一來，封裝的可靠性可提高。在製造期間，基底可用於對封裝進行實體支撐，由此減輕對單獨的載體及載體剝離製程（carrier debond process）的需要，此可有助於降低成本。
圖1至圖16B是根據某些實施例的COWOS封裝的製造過程的各中間階段的剖視圖。參照圖1，在載體102上放置基底104。通常，在後續加工步驟期間，載體102對各種特徵（例如，基底104）提供暫時的機械性及結構性支撐。通過這種方式，對裝置晶粒的損壞會減少或得到防止。載體102可包括例如玻璃、陶瓷等。在某些實施例中，載體102可實質上不具有任何主動裝置及/或功能性電路系統。在某些實施例中，使用釋放層103將基底104貼合至載體102。釋放層103可為任何適合的黏合劑，例如紫外光（ultraviolet，UV）膠等。
基底104可由例如矽、鍺、金剛石等半導體材料製成。在某些實施例中，也可使用例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些的組合等化合物材料。基底104可為中介層（interposer）。另外，基底104可為絕緣體上半導體（semiconductor-on-insulator，SOI）基底。通常，SOI基底包括由例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料形成的層。可在基底104的表面中及/或基底104的所述表面上形成例如電晶體、電容器、電阻器、二極體等裝置。在一個替代性實施例中，基底104是基於例如玻璃纖維加強型樹脂芯（fiberglass reinforced resin core）等絕緣芯。一種示例性芯材料為例如FR4等玻璃纖維樹脂。所述芯材料的各種替代形式包括雙馬來醯亞胺三嗪（bismaleimide-triazine，BT）樹脂，或者作為另外一種選擇，包括其他印刷電路板（printed circuit board，PCB）材料或膜。可對基底104使用例如味之素增層膜（Ajinomoto build-up film，ABF）等增層膜或其他層壓體（laminate）。
在圖2中，可在基底104中形成開口106。在後續加工中，可在每一開口106中形成穿孔（through via）（參見例如圖3）。穿孔可提供從基底104的一側至基底104的相對一側的電連接。如圖2中所示，開口106可不穿透過基底104。當開口106不穿透過基底104時，在後續加工中，可在基底104上執行薄化步驟（thinning step）以薄化基底104並使穿孔穿過基底104被暴露出（參見圖10）。在其他實施例中，開口106可穿透過基底104且不需要薄化步驟。
可以任何可接受方式形成開口106。在某些實施例中，將光阻（圖中未示出）形成並圖案化於基底104上。可通過旋轉塗布（spin coating）等來形成光阻並可將所述光阻暴露至光以進行圖案化。光阻的圖案對應於開口106的圖案。所述圖案化形成穿過光阻的開口以暴露出基底104。可執行穿過光阻的蝕刻製程（etch process）以形成開口106。可使用例如濕蝕刻（wet etching）或乾蝕刻（dry etching）等任何可接受蝕刻方式。在某些實施例中，所述蝕刻可為各向異性的。在完成蝕刻之後，可例如使用氧電漿等、通過可接受的灰化製程（ashing process）或剝除製程（stripping process）來移除光阻。所得結構繪示於圖2中。
參照圖3，以導電材料填充開口106，以形成穿孔110。在某些實施例中，可使用例如電鍍（electroplating）、無電鍍覆（electroless plating）等鍍覆製程（plating process）、以導電材料填充開口106。導電材料可包括金屬，如銅、鈦、鎢、鋁等。在以導電材料填充開口106以形成穿孔110之後，過量的導電材料可能外溢於開口106外並沿基底104的上表面延伸（圖3中未示出）。可執行平坦化製程（planarization process）（例如，研磨製程（grinding process）等）以移除導電材料的過量部分並使穿孔110的上表面與基底104的表面實質上共面。所得結構繪示於圖3中。
參照圖4，在基底104之上形成一層或多層重佈線層（redistribution layer，RDL）112。通常，RDL 112提供導電圖案，所述導電圖案使得完成封裝（completed package）能夠具有與晶粒118及120上隨後將貼合至連接件115的連接件118C及120C的圖案（參見圖5A）不同的引腳輸出觸點圖案（pin-out contact pattern）。RDL 112包括導電線114及通孔116，其中通孔116將上覆線（例如，上覆導電線114）連接至下伏導電特徵（例如，穿孔110及/或導電線114）。導電線114可根據特定設計沿任何方向延伸。
可使用任何適合的製程來形成RDL 112。舉例來說，在某些實施例中，在基底104上形成第一介電層。在某些實施例中，第一介電層是由可使用微影（lithography）來圖案化的聚合物形成，所述聚合物可為例如聚苯並惡唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）等感光性材料。在其他實施例中，第一介電層是由氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、磷矽酸鹽玻璃（PhosphoSilicate Glass，PSG）、硼矽酸鹽玻璃（BoroSilicate Glass，BSG）、摻雜硼的磷矽酸鹽玻璃（Boron-doped PhosphoSilicate Glass，BPSG）等形成。可通過旋轉塗布、層壓（lamination）、化學氣相沉積（chemical vapor deposition，CVD）等或其組合來形成第一介電層。接著將第一介電層圖案化以形成暴露出穿孔110的開口。在其中第一介電層是由感光性材料形成的實施例中，可通過根據所需圖案將第一介電層曝光並進行顯影以移除非期望材料來執行所述圖案化，由此暴露出穿孔110。也可使用其他方法（例如使用圖案化掩模及蝕刻）將第一介電層圖案化。
在第一介電層之上且在形成於所述第一介電層中的開口中形成晶種層（圖中未示出）。在某些實施例中，晶種層為金屬層，所述金屬層可為單一層或包括由不同材料形成的多個子層的複合層。在某些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積（physical vapor deposition，PVD）等來形成晶種層。接著根據所需重佈線圖案將掩模（圖中未示出）形成並圖案化於所述晶種層上。在某些實施例中，所述掩模是通過旋轉塗布等形成並被暴露至光以進行圖案化的光阻。所述圖案化穿過掩模形成暴露出晶種層的開口。在掩模的開口中且在晶種層的暴露的部分上形成導電材料。可使用例如電鍍、無電鍍覆等鍍覆製程來形成所述導電材料。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可例如使用氧電漿等、通過可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如通過濕蝕刻或乾蝕刻）移除晶種層的被暴露的部分。晶種層的其餘部分與導電材料形成導電線114及通孔116。接著在第一介電層之上形成第二介電層以為後續的層提供更平的表面，且可使用與用於形成第一介電層的材料及製程相似的材料及製程來形成所述第二介電層。在某些實施例中，第二介電層是由聚合物、氮化物、氧化物等形成。在某些實施例中，第二介電層是通過旋轉塗布製程形成的PBO。如有必要，則可重複進行以上製程以形成特定設計所可能需要的數目的RDL層。
根據某些實施例，在RDL 112之上形成連接件115。儘管在圖4中被繪示成凸塊，然而連接件115也可為焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊（micro bump）、由無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊、其組合（例如，貼合有焊料球的金屬柱）等。連接件115可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在某些實施例中，連接件115包含共晶材料（eutectic material）且可包括例如焊料凸塊或焊料球。焊料材料可為例如：鉛系焊料（lead-based solder）或無鉛焊料（lead-free solder），例如鉛系焊料的Pb-Sn成分；包含InSb的無鉛焊料；錫、銀、及銅（SAC）成分；以及具有共同的熔點並在電器中形成導電焊料連接的其他共晶材料。對於無鉛焊料，可使用由例如（舉例而言，SAC 105（Sn98.5%、Ag1.0%、Cu0.5%）、SAC 305、及SAC 405）等不同成分形成的SAC焊料。例如焊料球等無鉛連接件還可由SnCu化合物形成，而不使用銀（Ag）。作為另外一種選擇，無鉛焊料連接件可包含錫及銀、Sn-Ag，而不使用銅。連接件115可形成柵（grid），例如球柵陣列封裝（ball grid array，BGA）。在某些實施例中，可執行回焊製程（reflow process），以使連接件115的形狀在某些實施例中為不完整球體（partial sphere）。作為另外一種選擇，連接件115可包括其他形狀。
連接件115還可包括例如非球形導電連接件。在某些實施例中，連接件115包括通過濺鍍（sputtering）、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱（例如，銅柱），所述金屬柱上具有焊料材料或不具有焊料材料。金屬柱可不含焊料且具有實質上垂直的側壁或錐形的側壁。
連接件115還可包括根據某些實施例形成並圖案化於最上側金屬化圖案之上的凸塊下金屬（under bump metallization，UBM），由此形成與最上側金屬化層的電連接。UBM提供可在上面放置電連接件（例如，焊料球/凸塊、導電柱等）的電連接（electrical connection）。在實施例中，UBM包括擴散障壁層（diffusion barrier layer）、晶種層、或其組合。擴散障壁層可包含Ti、TiN、Ta、TaN、或其組合。晶種層可包含銅或銅合金。然而，也可包含其他金屬，例如鎳、鈀、銀、金、鋁、其組合、及其多層形式。在實施例中，使用濺鍍形成UBM。在其他實施例中，可使用電鍍。
參照圖5A，將晶粒118及120結合至連接件115。根據某些示例性實施例，晶粒118為邏輯晶粒，例如中央處理器（Central Processing Unit，CPU）、應用處理器（Application processor，AP）、系統晶片（system on chip，SOC）、應用專用積體電路（Application Specific Integrated Circuit，ASIC）、或其中包括邏輯電晶體的其他類型的邏輯晶粒。儘管示出三個晶粒118，然而可將更少或更多的晶粒118結合至連接件115。晶粒118可具有相同結構及/或相同功能，或可具有不同結構及功能。
根據某些實施例，各晶粒118可分別包括主體（main body）118A、內連線區118B、及連接件118C。主體118A可包括任何數目的晶粒、基底、電晶體、主動裝置、被動裝置等。內連線區118B可提供導電圖案，所述導電圖案使得主體118A能夠具有與連接件118C的圖案不同的引腳輸出觸點圖案，從而使得能夠更靈活地放置連接件118C。可將連接件118C放置於晶粒118的底側上，且可使用連接件118C將晶粒118實體地連接至且電連接至連接件115。可通過內連線區118B將連接件118C電連接至主體118A。可使用與以上結合連接件115所述的方法相同或相似的方法來形成連接件118C。
根據某些示例性實施例的晶粒120包括記憶體晶粒。舉例來說，晶粒120可為動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）晶粒、靜態隨機存取記憶體（Static Random Access Memory，SRAM）晶粒、高頻寬記憶體（High-Bandwidth Memory，HBM）晶粒、微機電系統（Micro-Electro-Mechanical System，MEMS）晶粒、混合存儲資料集（Hybrid Memory Cube，HMC）晶粒等。儘管示出三個晶粒120，然而可結合更少或更多的晶粒120。各晶粒120可具有相同的結構及/或功能，或可具有不同的結構及功能。根據某些實施例，晶粒120可包括主體120A、內連線區120B、及連接件120C。
在圖5B中更詳細地繪示了根據某些實施例的示例性晶粒120。主體120A可包括多個堆疊記憶體晶粒120D。堆疊記憶體晶粒120D可均為相同的晶粒，或者記憶體晶粒120可包括不同類型及/或結構的晶粒。可通過連接件120E將記憶體晶粒120D連接至上覆晶粒120D及/或下伏記憶體晶粒120D。在某些實施例中，主體120A可包括高頻寬記憶體（HBM）模組及/或混合存儲資料集（HMC）模組，所述模組可包括與邏輯晶粒120G連接的一個或多個記憶體晶粒120D。邏輯晶粒120G可包括將內連線區120B的導電特徵連接至上覆連接件120E的穿孔（圖中未示出）。如由圖5B所示，可將主體120A包封於模製材料120F中。模製材料120F可包括模製化合物（molding compound）、模製底部填充物（molding underfill）、環氧樹脂（epoxy）、或樹脂。
內連線區120B位於主體120A之下。內連線區120B可提供導電圖案，所述導電圖案使得主體120A能夠具有與連接件120C的圖案不同的引腳輸出觸點圖案，從而使得能夠更靈活地放置連接件120C。可將連接件120C放置於晶粒120的底側上，且可使用連接件120C將晶粒120實體地連接至且電連接至連接件115。可通過內連線區120B將連接件120C電連接至邏輯晶粒120G及/或堆疊記憶體晶粒120D。可使用與以上結合連接件115所述的方法相同或相似的方法來形成連接件120C。
圖5A繪示其中晶粒118與晶粒120在平面圖中相互交錯的實施例。在某些實施例中，可使用晶粒118及120的不同排列。舉例來說，在某些實施例中，晶粒118可在晶粒118的任一側上包括晶粒120。
可使用任何適合的方法將晶粒118及120結合至連接件115。根據某些實施例，可通過將連接件118C及120C結合至連接件115而將晶粒118及120分別結合至連接件115。
參照圖6，可在晶粒118/120與RDL 112之間形成底部填充物123，且底部填充物123可環繞連接件115、118C、及/或120C。在貼合晶粒118及120之後，可通過毛細流動製程（capillary flow process）來形成底部填充物123，或者在貼合晶粒118及120之前，可通過適合的沉積方法來形成底部填充物123。
接下來，將晶粒118及120包封於模製材料122中。模製材料122填充晶粒118與晶粒120之間的間隙，且可接觸連接件115、連接件118C、連接件120C、及/或RDL 112。模製材料122可包括模製化合物、模製底部填充物、環氧樹脂、或樹脂。模製材料122可為與晶粒120的模製材料120F相同的材料，或可為不同材料。在形成之後，模製材料122的頂表面可高於晶粒118及120的頂表面。
接下來，執行研磨步驟以薄化模製材料122，直至暴露出晶粒118及120的頂表面。所得結構示出於圖7中。
參照圖8，將基底126貼合至穿過模製材料122被暴露出的晶粒118及120的表面。可使用黏合層124來貼合基底126。在某些實施例中，黏合層124可包括晶粒貼合膜（die attach film，DAF）。
在後續加工期間，基底126可為封裝100提供結構性支撐。舉例來說，如上所述，晶粒118的頂表面及晶粒120的頂表面穿過模製材料122被暴露出，此可能在封裝100上造成外應力（extrinsic stress）且可能在加工期間（例如在測試或機上加工（on-board processing）期間）對封裝100的頂表面造成損壞。在後續加工期間，基底126可有助於減輕對封裝100的頂表面的損壞。在後續加工期間，基底126也可有助於減輕封裝100的翹曲，由此提高封裝100的可靠性。此外，如以下將闡述，在後續加工中將翻轉封裝100，且在封裝100的附加加工期間，基底126可為封裝100提供實體支撐。基底126的存在可消除對單獨的載體（例如，玻璃基底）及剝離製程的需要，此可有助於降低製造成本。
在某些示例性實施例中，基底126可由矽形成。舉例來說，基底126可由實質上純的矽形成。在其他實施例中，基底126可包含提供剛性（rigidity）及/或熱傳導（thermal conductance）的任何適合的材料，從而使得基底126可有助於均勻地消散來自封裝100的熱量並在附加加工期間為晶粒118及120的頂表面提供結構支撐。在某些實施例中，基底126可包含金屬，例如Cu、Ni、或Al。在某些實施例中，基底126可包含陶瓷材料。舉例來說，在某些實施例中，基底126可包含Al2 O3 。在某些實施例中，基底126可包含聚合物材料。
參照圖9，將封裝100翻轉，以使基底126為底並為封裝100提供實體支撐。剝離載體102，留下圖9中所示結構。如圖9中所繪示，在此加工階段處，基底104、RDL 112、及連接件115具有為約10μm至約1000μm（例如，約775μm）的組合厚度T1。晶粒118及晶粒120分別具有為約50μm至約1000μm（例如，760μm）的厚度T2。基底126具有為約10μm至約1000μm（例如，約775μm）的厚度T3。基底104具有為約10μm至約1000μm（例如，約775μm）的厚度T4。
接下來，參照圖10，薄化基底104，直至暴露出穿孔110。舉例來說，可使用研磨製程來薄化基底104。在所述薄化之後，基底104、RDL 112、及連接件115可具有為約5μm至約1000μm（例如，100μm）的組合厚度T5。所述薄化製程可在頂表面上形成例如金屬顆粒等金屬殘留物。因此，在所述薄化之後，可例如通過濕蝕刻執行清洗（cleaning），以使金屬殘留物被移除。
參照圖11，使用與以上結合連接件115所述的方法相同或相似的方法在基底104上形成連接件129。在圖11中繪示的實施例中，每一連接件129包括通過濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱128（例如，銅柱）。每一金屬柱128具有在與和基底104接觸的表面相對的表面上形成的焊料130。金屬柱128可具有實質上垂直的側壁（例如，圖11中繪示的實施例），或在其他實施例中可具有錐形的側壁。
接下來，如圖12中所示，在基底104之上施加保護膜132。保護膜132沿連接件129的側壁延伸且具有足以完全覆蓋連接件129的厚度。保護膜132可為膠帶（例如，背側研磨（backgrinding，BG）膠帶（紫外光膠帶（UV tape）或非紫外光膠帶（non-UV tape））），所述膠帶可用於在後續平坦化製程期間（參見圖13至圖14）保護基底104的表面及連接件129的表面不被研磨碎屑損壞。可使用例如滾筒（roller）（圖中未示出）來施加保護膜132。
參照圖13，再次將封裝100翻轉，以使保護膜132為底並為封裝100提供實體支撐。在所述翻轉之後，基底126位於封裝100頂上。
接下來，參照圖14，薄化基底126。在某些實施例中，可使用研磨製程來薄化基底126。在所述薄化之後，基底126可具有為約5μm至約1000μm（例如，50μm）的厚度T6。所述薄化製程可能會在基底126的頂表面上形成例如金屬顆粒等金屬殘留物。因此，在所述薄化之後，可例如通過濕蝕刻執行清洗，以使金屬殘留物被移除。
參照圖15，再次將封裝100翻轉，且可將基底126貼合至暫時支撐框架134（例如，包括支撐膠帶）。接下來，移除保護膜132，從而暴露出連接件129。接下來，將封裝100單體化成獨立的封裝200。在某些實施例中，可通過鋸切（sawing）等來將封裝100單體化。可將封裝100單體化成使得每一獨立的封裝200均包括晶粒118及晶粒120。在其他實施例中，可對每一封裝200使用不同數目及/或配置的晶粒118及120。
接下來，參照圖16A，將封裝200翻轉並結合至基底136。基底136可由例如矽、鍺、金剛石等半導體材料製成。在某些實施例中，也可使用例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、這些的組合等化合物材料。另外，基底136可為SOI基底。通常，SOI基底包括由例如磊晶矽、鍺、矽鍺、SOI、絕緣體上矽鍺（SGOI）或其組合等半導體材料形成的層。在一個替代性實施例中，基底136是基於例如玻璃纖維加強型樹脂芯等絕緣芯。一種示例性芯材料為例如FR4等玻璃纖維樹脂。所述芯材料的各種替代形式包括雙馬來醯亞胺三嗪（BT）樹脂，或者作為另外一種選擇，包括其他印刷電路板（PCB）材料或膜。可對基底136使用例如味之素增層膜（ABF）等增層膜或其他層壓體。
基底136可包括主動裝置及被動裝置（圖16B中未示出）。所屬領域中的普通技術人員應認識到，可使用例如電晶體、電容器、電阻器、這些的組合等眾多各種各樣的裝置來產生對半導體封裝設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
基底136還可包括金屬化層及通孔（圖中未示出）以及與所述金屬化層及通孔連接的結合墊142。可將金屬化層形成於主動裝置及被動裝置之上並設計成連接各種裝置以形成功能性電路系統。金屬化層可由交替的介電質（例如，低介電常數介電材料（low-k dielectric material））層與導電材料（例如，銅）層形成且可使用任何適合的製程（例如，沉積、鑲嵌（damascene）、雙鑲嵌（dual damascene）等）來形成所述金屬化層，其中通孔對各所述導電材料層進行內連。在某些實施例中，基底136實質上不具有主動裝置及被動裝置。
基底136可在基底136的底表面上包括連接件146。可使用連接件146將基底136實體地連接至且電連接至其他裝置、封裝、元件等。另外，可將一或多個表面裝置144連接至基底136。可使用表面裝置144為封裝200或整個封裝提供附加功能性或程式設計。在實施例中，表面裝置144可包括表面安裝裝置（surface mount device，SMD）或包括例如電阻器、電感器、電容器、跨接線（jumper）、這些的組合等被動裝置的積體被動裝置（integrated passive device，IPD），所述被動裝置需要連接至封裝200或所述封裝的其他部分並與其結合使用。可根據特定方式將表面裝置144放置於基底136的第一主表面、基底136的相對主表面、或第一主表面與相對主表面二者上。
可使用結合墊142將封裝200結合至基底136。可使用例如以上結合連接件115所述的方法等任何適合的方法來形成結合墊142。結合墊142可具有與基底136齊平的頂表面。在其他實施例中，結合墊142從基底136突出。可使用結合墊142來連接至柱128及/或焊料130，由此將封裝200結合至基底136。
在某些實施例中，可在基底136的表面上靠近連接件129（圖16A中的金屬柱128及焊料130）處形成底部填充物148。在某些實施例中，底部填充物148沿柱128的側壁且沿基底104的底表面延伸。在某些實施例中，底部填充物148進一步沿基底104的側壁、RDL 112的側壁、及/或晶粒118及120的側壁延伸。在封裝200貼合至基底136之後，可通過毛細流動製程來形成底部填充物148，或者在封裝200貼合至基底136之前，可通過適合的沉積方法來形成底部填充物148。
接下來，對基底126的頂表面施加熱介面材料140。熱介面材料140可有助於將來自封裝200的熱量消散至後續施加的散熱蓋（heat dissipation lid）138，由此有助於在封裝結構中維持較低溫度。熱介面材料140可包括例如具有良好導熱係數（thermal conductivity）（其可介於約3瓦/米·度（W/m·K））至5W/m·K之間或大於5W/m·K）的聚合物等任何適合的導熱材料。
接下來，貼合散熱蓋138。散熱蓋138除散熱外還可為封裝結構提供實體保護。散熱蓋138可具有例如介於約200W/m·K至約400W/m·K之間或高於400W/m·K的高導熱係數，且可使用金屬、金屬合金、石墨烯、碳奈米管（carbon nanotube，CNT）等來形成散熱蓋138。在某些實施例中，利用黏合劑等將散熱蓋138貼合至基底136，以使封裝200排列於散熱蓋138的內腔內。在某些實施例中，可在散熱蓋138的內腔內放置一或多個表面裝置144。在某些實施例中，可在基底136上在散熱蓋138的周邊外放置一或多個表面裝置。
可存在其他實施例。參照圖16A，其繪示其中在施加散熱蓋138之前基底126已被移除的實施例。舉例來說，在使用與以上結合圖16A所論述的方法相同或相似的方法將封裝200結合至基底16B之後、且在某些實施例中在貼合散熱蓋138之前，移除基底126。可選地在晶粒118及120的被移除基底126的表面上施加熱介面材料140。接下來，使用與以上結合圖16A所論述的方法相同或相似的方法來施加散熱蓋138。
如本文中所論述，根據某些實施例，提供一種基底晶圓上晶片（COWOS）封裝。基底可在COWOS封裝中貼合至晶粒的背側。在製造期間，基底可保護晶粒且可減輕封裝翹曲。這樣一來，封裝的可靠性可得到提高。在製造期間，基底可用於為封裝提供暫時實體支撐，由此減輕對單獨的載體及載體剝離製程的需要，此可有助於降低製造成本。
根據某些實施例提供一種方法。所述方法包括將第一晶粒及第二晶粒貼合至中介層。所述方法還包括將第一基底貼合至所述第一晶粒的第一表面及所述第二晶粒的第一表面。所述第一基底包含矽。所述第一晶粒的所述第一表面與所述第一晶粒的貼合至所述中介層的表面相對，且所述第二晶粒的所述第一表面與所述第二晶粒的貼合至所述中介層的表面相對。所述方法還包括將所述中介層結合至第二基底。
在一些實施例中，進一步包括：對所述第一基底的表面施加熱介面材料；以及將散熱蓋貼合至所述第二基底，所述第一基底設置於所述散熱蓋的內腔中。
在一些實施例中，進一步包括將表面安裝裝置結合至所述第二基底，其中在所述散熱蓋貼合至所述第二基底之後，所述表面安裝裝置位於所述散熱蓋的所述內腔中。
在一些實施例中，所述第一晶粒是邏輯晶粒且所述第二晶粒是記憶體晶粒。
在一些實施例中，所述第一基底利用晶粒貼合膜結合至所述第一晶粒的所述第一表面及所述第二晶粒的所述第一表面。
在一些實施例中，進一步包括：薄化所述中介層；其中在所述薄化期間，所述第一基底位於所述中介層之下並為所述中介層提供實體支撐。
在一些實施例中，所述薄化暴露出所述中介層中所包括的穿孔。
在一些實施例中，進一步包括薄化所述第一基底。
在一些實施例中，所述第一晶粒包括第一記憶體晶粒及第二記憶體晶粒，所述第一記憶體晶粒通過連接件連接至所述第二記憶體晶粒。
在一些實施例中，進一步包括：在所述中介層之上形成多個電連接件，所述多個電連接件中的每一電連接件均電連接至所述中介層的穿孔；其中在所述形成所述多個電連接件期間，所述第一基底對所述中介層進行實體支撐。
在一些實施例中，進一步包括在將所述中介層結合至所述第二基底之前，移除所述第一基底。
根據某些實施例提供一種方法。所述方法包括在第一基底中形成多個穿孔。所述方法還包括將多個第一晶粒及多個第二晶粒貼合至所述第一基底，並將所述多個第一晶粒及所述多個第二晶粒耦合至所述多個穿孔。所述方法還包括將所述多個第一晶粒及所述多個第二晶粒包封於模製材料中，其中所述多個第一晶粒的頂表面及所述多個第二晶粒的頂表面穿過所述模製材料被暴露出。所述方法還包括將第二基底貼合至穿過所述模製材料被暴露出的所述多個第一晶粒的所述頂表面及所述多個第二晶粒的所述頂表面。所述方法還包括將所述第一基底結合至第三基底。
在一些實施例中，進一步包括將蓋貼合至所述第三基底，所述多個第一晶粒的一個第一晶粒及所述多個第二晶粒的一個第二晶粒設置於所述蓋的腔中。
在一些實施例中，所述第二基底設置於所述蓋的所述腔內。
在一些實施例中，進一步包括：在貼合所述蓋之前，從所述多個第一晶粒的所述頂表面及所述多個第二晶粒的所述頂表面移除所述第二基底。
在一些實施例中，進一步包括在將所述第二基底貼合至所述多個第一晶粒的所述頂表面及所述多個第二晶粒的所述頂表面之後，薄化所述第二基底。
在一些實施例中，進一步包括將所述第一基底單體化，其中在所述單體化之後，將所述多個第一晶粒的一個第一晶粒及所述多個第二晶粒的一個第二晶粒貼合至被結合至所述第三基底的所述第一基底的一部分。
在一些實施例中，在所述第一基底之上形成多個電連接件，所述多個電連接件中的每一電連接件均電連接至所述第一基底中的所述多個穿孔的一個穿孔；其中在所述形成所述多個電連接件期間，所述第二基底對所述第一基底進行實體支撐。
根據某些實施例提供一種裝置。所述裝置包括第一基底及結合至所述第一基底的中介層。第一晶粒及第二晶粒結合至所述中介層。模製材料沿所述第一晶粒的側壁及所述第二晶粒的側壁延伸，其中所述第一晶粒的頂表面及所述第二晶粒的頂表面穿過所述模製材料被暴露出。第二基底貼合至穿過所述模製材料被暴露出的所述第一晶粒的所述頂表面及所述第二晶粒的所述頂表面。所述第二基底包含矽。
在一些實施例中，進一步包括：散熱蓋，結合至所述第一基底，其中所述中介層、所述第一晶粒、所述第二晶粒、及所述第二基底分別設置於所述散熱蓋的內腔內。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
100‧‧‧封裝
102‧‧‧載體
103‧‧‧釋放層
104、126、136‧‧‧基底
106‧‧‧開口
110‧‧‧穿孔
112‧‧‧重佈線層（RDL）
114‧‧‧導電線
115、118C、120C、129、146‧‧‧連接件
116‧‧‧通孔
118‧‧‧晶粒
118A‧‧‧主體
118B‧‧‧內連線區
120‧‧‧晶粒
120A‧‧‧主體
120B‧‧‧內連線區
120D‧‧‧晶粒
120E‧‧‧連接件
120F‧‧‧模製材料
120G‧‧‧邏輯晶粒
122‧‧‧模製材料
123、148‧‧‧底部填充物
124‧‧‧黏合層
128‧‧‧柱
130‧‧‧焊料
132‧‧‧保護膜
134‧‧‧暫時支撐框架
138‧‧‧散熱蓋
140‧‧‧熱介面材料
142‧‧‧結合墊
144‧‧‧表面裝置
200‧‧‧封裝
T1、T5‧‧‧組合厚度
T2、T3、T4、T6‧‧‧厚度
結合附圖閱讀以下詳細說明，會最好地理解本發明的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1至圖5A、及圖5B至圖15是形成根據某些實施例的半導體封裝的過程中的各中間階段的剖視圖。 圖16A及圖16B是根據某些實施例的半導體封裝結構的剖視圖。

Claims (1)

  1. 一種基底晶圓上晶片結構的形成方法，包括： 將第一晶粒及第二晶粒貼合至中介層； 將第一基底貼合至所述第一晶粒的第一表面及所述第二晶粒的第一表面，所述第一基底包含矽，所述第一晶粒的所述第一表面與所述第一晶粒的貼合至所述中介層的表面相對，且所述第二晶粒的所述第一表面與所述第二晶粒的貼合至所述中介層的表面相對；以及 將所述中介層結合至第二基底。
TW106117530A 2016-12-30 2017-05-26 基底晶圓上晶片結構的形成方法 TW201826403A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662441001P 2016-12-30 2016-12-30
US62/441,001 2016-12-30
US15/479,735 US10170457B2 (en) 2016-12-30 2017-04-05 COWOS structures and method of forming the same
US15/479,735 2017-04-05

Publications (1)

Publication Number Publication Date
TW201826403A true TW201826403A (zh) 2018-07-16

Family

ID=62711165

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106117530A TW201826403A (zh) 2016-12-30 2017-05-26 基底晶圓上晶片結構的形成方法

Country Status (3)

Country Link
US (1) US10170457B2 (zh)
CN (1) CN108269767A (zh)
TW (1) TW201826403A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI711145B (zh) * 2019-04-23 2020-11-21 台灣積體電路製造股份有限公司 封裝結構及其製造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727203B1 (en) * 2018-05-08 2020-07-28 Rockwell Collins, Inc. Die-in-die-cavity packaging
TWI697078B (zh) * 2018-08-03 2020-06-21 欣興電子股份有限公司 封裝基板結構與其接合方法
US10692795B2 (en) 2018-11-13 2020-06-23 International Business Machines Corporation Flip chip assembly of quantum computing devices
CN113035823A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 封装结构
US11424219B2 (en) 2020-01-16 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11114409B2 (en) * 2020-01-30 2021-09-07 Hewlett Packard Enterprise Development Lp Chip on wafer on substrate optoelectronic assembly and methods of assembly thereof
US11282825B2 (en) 2020-05-19 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US11776820B2 (en) 2020-09-30 2023-10-03 Huawei Technologies Co., Ltd. Vertical interconnection structure and manufacturing method thereof, packaged chip, and chip packaging method
US11848246B2 (en) * 2021-03-24 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11862590B2 (en) 2021-04-14 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of forming thereof
TW202245212A (zh) * 2021-05-11 2022-11-16 群創光電股份有限公司 電子裝置
US11908757B2 (en) * 2021-06-18 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Die corner removal for molding compound crack suppression in semiconductor die packaging and methods for forming the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396403A (en) * 1993-07-06 1995-03-07 Hewlett-Packard Company Heat sink assembly with thermally-conductive plate for a plurality of integrated circuits on a substrate
TWI398943B (zh) * 2010-08-25 2013-06-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI711145B (zh) * 2019-04-23 2020-11-21 台灣積體電路製造股份有限公司 封裝結構及其製造方法
US10923421B2 (en) 2019-04-23 2021-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same

Also Published As

Publication number Publication date
CN108269767A (zh) 2018-07-10
US20180190638A1 (en) 2018-07-05
US10170457B2 (en) 2019-01-01

Similar Documents

Publication Publication Date Title
US11721559B2 (en) Integrated circuit package pad and methods of forming
US11189603B2 (en) Semiconductor packages and methods of forming same
US10170457B2 (en) COWOS structures and method of forming the same
US10964641B2 (en) Method of forming semiconductor packages having through package vias
TWI683401B (zh) 半導體結構及其形成方法
US10163802B2 (en) Fan-out package having a main die and a dummy die, and method of forming
TWI614817B (zh) 封裝結構及其形成方法
US20200126959A1 (en) Semiconductor Device and Method of Manufacture
TWI727463B (zh) 封裝體及其形成方法
US20190148276A1 (en) Semiconductor packages and methods of forming same
US20190393195A1 (en) Device and Method for UBM/RDL Routing
US20200312774A1 (en) Semiconductor devices and methods of forming the same
TW201804589A (zh) 封裝結構及其形成方法
CN107665852B (zh) 形成半导体器件的方法
TWI744628B (zh) 晶片封裝件及其製作方法
TW202134713A (zh) 積體電路封裝及其形成方法
US10586763B2 (en) Semiconductor device and method of manufacture
TW202220062A (zh) 封裝結構、半導體裝置、及封裝結構的製造方法
US11205615B2 (en) Semiconductor device and method of manufacture
TW202401695A (zh) 半導體封裝及方法