CN113035823A - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN113035823A
CN113035823A CN202011545070.7A CN202011545070A CN113035823A CN 113035823 A CN113035823 A CN 113035823A CN 202011545070 A CN202011545070 A CN 202011545070A CN 113035823 A CN113035823 A CN 113035823A
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CN
China
Prior art keywords
wafer
interposer
interconnect structure
groove
disposed
Prior art date
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Pending
Application number
CN202011545070.7A
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English (en)
Inventor
叶宫辰
卢思维
蔡宗甫
施应庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication date
Priority claimed from US16/888,868 external-priority patent/US11508692B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113035823A publication Critical patent/CN113035823A/zh
Pending legal-status Critical Current

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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

本发明提供一种封装结构，包含插入件、至少一个半导体管芯以及绝缘密封体。插入件包含半导体衬底和设置在半导体衬底上的内连线结构，内连线结构包含层间介电膜和嵌入于层间介电膜中的内连线布线，半导体衬底包含第一部分和设置在第一部分上的第二部分，内连线结构设置在第二部分上，且第一部分的第一最大横向尺寸大于第二部分的第二最大横向尺寸。至少一个半导体管芯设置在内连线结构上方且电连接到内连线结构。绝缘密封体设置在第一部分上，其中绝缘密封体横向地密封至少一个半导体管芯和第二部分。本发明可防止插入件晶片中的内连线结构的裂纹问题或碎裂问题。

Description

封装结构
技术领域
本公开的实施例涉及一种封装结构。
背景技术
半导体行业已归因于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度的持续改进而经历快速增长。主要来说，集成密度的这一改进来自于最小特征大小的反复减小，这允许将更多组件集成到给定区域中。随着近来对小型化、更高速度和更大带宽以及更低功耗和延迟的需求已增长，对半导体管芯的更小和更有创造性的封装技术的需求已增长。目前,衬底上晶片上芯片(Chip-on-Wafer-on-Substrate；CoWoS)封装结构因其多功能和高效能变得越来越普遍。然而，存在与CoWoS封装结构的封装工艺相关的挑战。
发明内容
本公开实施例的一种封装结构，包括：插入件、至少一个半导体管芯以及绝缘密封体，所述插入件包括半导体衬底以及内连线结构，所述内连线结构设置在所述半导体衬底上，所述内连线结构包括层间介电膜和嵌入于所述层间介电膜中的内连线布线，所述半导体衬底包括第一部分和设置在所述第一部分上的第二部分，所述内连线结构设置在所述第二部分上，且所述第一部分的第一最大横向尺寸大于所述第二部分的第二最大横向尺寸；所述至少一个半导体管芯设置在所述内连线结构上方且电连接到所述内连线结构；所述绝缘密封体设置在所述第一部分上，其中所述绝缘密封体横向地密封所述至少一个半导体管芯和所述第二部分。
本公开实施例的一种封装结构，包括插入件、至少一个半导体管芯以及绝缘密封体，所述插入件包括半导体衬底和设置在所述半导体衬底上的内连线结构，所述内连线结构包括层间介电膜和嵌入于所述层间介电膜中的内连线布线，所述半导体衬底包括分布在所述插入件的周边区中的环形凹槽，其中所述环形凹槽包括波浪形侧壁；所述至少一个半导体管芯，设置在所述内连线结构上方且电连接到所述内连线结构；以及所述绝缘密封体设置在所述插入件上，其中所述绝缘密封体密封所述至少一个半导体管芯且填充所述插入件的所述环形凹槽。
本公开实施例的一种制造封装结构的方法，包括：设置包括半导体衬底和设置在所述半导体衬底上的内连线结构的插入件晶片，所述内连线结构包括层间介电膜和嵌入于所述层间介电膜中的内连线布线；通过非接触预切割工艺在所述插入件晶片上形成凹槽，所述凹槽延伸穿过所述内连线结构，且所述半导体衬底通过所述凹槽显露；将半导体管芯放置到包括形成于其上的所述凹槽的所述插入件晶片；在所述插入件晶片上方形成绝缘密封体以横向地密封所述半导体管芯且填充所述凹槽；以及执行晶片锯切工艺以沿形成于所述插入件晶片上的所述凹槽锯切所述绝缘密封体和所述插入件晶片以获得封装结构，其中所述凹槽的最大横向尺寸宽于所述晶片锯切工艺的切割宽度。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本公开的各方面。应注意，根据业界中的标准惯例，各种特征未按比例绘制。实际上，为了论述清楚起见，可任意增大或减小各种特征的尺寸。
图1A到图1M为根据本公开的一些实施例的示意性地示出用于制造衬底上晶片上芯片(CoWoS)封装结构的工艺流程的横截面视图。
图2为根据本公开的一些其它实施例的示意性地示出通过刻蚀工艺在插入件晶片中形成凹槽的横截面视图。
图3为根据本公开的一些替代性实施例的示意性地示出通过刻蚀工艺在插入件晶片中形成凹槽的横截面视图。
[附图标号说明]
100：插入件
100a：第一部分
100b：第二部分
110、110'：半导体衬底
120、120'：内连线结构
122：内连线布线
124：层间介电膜
130、162a、162b：导电通孔
140：焊料材料层
150：半导体穿孔
160a、160b：半导体管芯
170、300：底部填充物
180、180a、180b、180b'：绝缘密封体
182：主体部分
184：环部分
184a：第一环部分
184b：第二环部分
185：介电层
190、210：导电端子
192：凸块下金属化层
194：受控塌陷芯片连接凸块
200：电路衬底
C：载体
D1、D3：最大横向尺寸
D2、D4：深度
D5：最大切割宽度
DB：剥离层
F：框架
G1'、G2'：环形凹槽
G1、G2：交叉凹槽
P：封装结构
PR：图案化光刻胶层
S1、S2：预切割工艺
S3：刻蚀工艺
S4：晶片锯切工艺
SL：交叉切割道
SW：侧壁
T1：晶片开槽带
T2：晶片锯切带
W、W'：插入件晶片
α1、α2：夹角
具体实施方式
以下公开提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例来简化本公开。当然，这些仅是实例且并不意图为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或第二特征上形成可包含第一特征与第二特征直接接触地形成的实施例，且还可包含可在第一特征与第二特征之间形成额外特征，使得第一特征与第二特征可以不直接接触的实施例。此外，本公开可能在各种实例中重复附图标号和/或字母。这一重复是出于简单和清晰的目的，且本身并不指示所论述的各种实施例和/或配置之间的关系。
此外，为易于描述，可在本文中使用例如“在……下方”、“在……之下”、“下部”、“在……之上”、“上部”以及类似物的空间相对术语，以描述如图中所示出的一个元件或特征与另一元件或特征的关系。除图中所描绘的定向之外，空间相关术语意图涵盖器件在使用或操作中的不同定向。装置可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相对描述词可同样相应地进行解释。
还可包含其它特征和工艺。举例来说，可包含测试结构以辅助3D封装或3DIC器件的验证测试。测试结构可包含例如形成于重布线层中或衬底上的测试衬垫，其允许对3D封装或3DIC的测试、对探针和/或探针卡的使用以及类似物。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构和方法可与并入有对已知良好管芯的中间验证的测试方法结合使用以增加良率且降低成本。
图1A到图1M为根据本公开的一些实施例的示意性地示出用于制造衬底上晶片上芯片(CoWoS)封装结构的工艺流程的横截面视图。图2为根据本公开的一些其它实施例的示意性地示出通过刻蚀工艺在插入件晶片中形成凹槽的横截面视图。
参考图1A，设置由晶片开槽带T1承载的插入件晶片W。插入件晶片W可包含半导体衬底110、设置在半导体衬底110上的内连线结构120、设置在内连线结构120上且电连接到内连线结构120的导电通孔130，以及设置在导电通孔130上的焊料材料层140。插入件晶片W可为包含形成于其中的有源组件的有源插入件晶片。半导体衬底110可为包含形成于其中的有源组件(例如晶体管或类似物)和无源组件(例如电阻器、电容器、电感器或类似物)的硅衬底。有源组件和无源组件可通过插入件晶片W的前道(front end of line；FEOL)制造工艺形成于半导体衬底110中。内连线结构120可交替地包含内连线布线122(例如铜内连线布线)和层间介电膜124，其中内连线布线122嵌入于层间介电膜124中，内连线结构120的内连线布线122电连接到半导体衬底110中的有源组件和/或无源组件。内连线布线122可为铜内连线布线或其它合适的金属布线，且层间介电膜124可为氧化硅层、氮化硅层、氮氧化硅层、由其它合适的低介电常数(1ow-k，即介电常数＜2.5)介电材料形成的介电层，或其组合。可通过插入件晶片W的后道(back end of line；BEOL)制造工艺形成内连线结构120。
导电通孔130可从内连线结构120的顶部表面突出。在一些实施例中，导电通孔130包含铜微凸块、Cu/Ni微凸块或类似物，且焊料材料层140包含无铅焊料材料层。举例来说，焊料材料层140可包含Sn-Ag合金层。此外，导电通孔130和焊料材料层140可通过一种或多种电镀工艺形成于内连线结构120上方。在一些实施例中，晶种层(例如Ti/Cu晶种层)通过溅镀工艺形成于内连线结构120上；图案化光刻胶层形成于溅镀晶种层上；其中图案化光刻胶层包含用于暴露渐镀晶种层的开口；执行一种或多种电镀工艺，使得导电通孔130和焊料材料层140依序电镀在由限定于图案化光刻胶层中的开口暴露的溅镀晶种层上；剥除图案化光刻胶层；且通过刻蚀工艺去除溅镀晶种层的未由导电通孔130和焊料材料层140覆盖的部分，直到暴露内连线结构120。
在一些实施例中，如图1A中所示出，插入件晶片W进一步包含半导体穿孔(throughsemiconductor via；TSV)150，其中半导体穿孔150嵌入于半导体衬底110中且电连接到内连线结构120。在一些替代性实施例中，在图1A中未示出，插入件晶片进一步包含半导体穿孔，其中半导体穿孔嵌入于半导体衬底中、电连接到内连线结构且延伸到内连线结构中。
参考图1B，沿插入件晶片W的交叉切割道SL执行预切割工艺S1，使得交叉凹槽G1形成于插入件晶片W的正表面上。在一些实施例中，通过沿插入件晶片W的交叉切割道SL执行的非接触预切割工艺(即，预切割工艺S1)形成凹槽G1。举例来说，通过沿插入件晶片W的交叉切割道SL执行的激光开槽工艺形成凹槽G1。凹槽G1可向下延伸穿过内连线结构120，且通过凹槽G1显露半导体衬底110的部分。凹槽G1的深度可大于内连线结构120的厚度，且凹槽G1的深度可小于半导体穿孔150的高度。在一些实施例中，凹槽G1的最大横向尺寸D1在约55微米到约90微米范围内，且凹槽G1的深度D2在约5微米到约10微米范围内。换句话说，预切割工艺S1的最大切割宽度D1在约55微米到约90微米范围内，且预切割工艺S1的切割深度D2在约5微米到约10微米范围内。
参考图1C，沿插入件晶片W的交叉切割道SL执行预切割工艺S2，使得交叉凹槽G2形成于插入件晶片W的正表面上。在一些实施例中，通过沿插入件晶片W的交叉切割道SL执行的晶片划片工艺形成凹槽G2。举例来说，对插入件晶片W执行片锯工艺以形成凹槽G2。凹槽G2形成于半导体衬底110中且朝向插入件晶片W的背表面从凹槽G1的底部向下延伸。凹槽G2位于凹槽G1的下面。凹槽G1的深度与凹槽G2的深度的总和可小于TSV 150的高度和半导体衬底110的厚度。在一些实施例中，凹槽G2的最大横向尺寸D3在约50微米到约85微米范围内，且凹槽G2的深度D4在约20微米到约50微米范围内。换句话说，预切割工艺S2的最大切割宽度D3在约50微米到约85微米范围内，且预切割工艺S2的切割深度D4在约20微米到约50微米范围内。此外，凹槽G1的深度与凹槽G2的深度的总和可在约5微米到约50微米范围内。
如图1C中所示出，凹槽G1的最大横向尺寸D1可大于凹槽G2的最大横向尺寸D3，凹槽G1的深度可大体上等于凹槽G2的深度。在一些实施例中，凹槽G1包含锥形侧壁，且凹槽G2包含大体上竖直侧壁。换句话说，夹角α1可大于夹角α2，夹角α1可在约90度到约150度范围内，且夹角α2可在约89.5度到约90度范围内。夹角α1可为包含于凹槽G1的锥形侧壁与内连线结构120的顶部表面之间的角，且夹角α2可为包含于凹槽G2的锥形侧壁与平行于内连线结构120的顶部表面的虚拟平面之间的角。凹槽G1中的每一个可具有顶部横向尺寸和小于顶部横向尺寸的底部横向尺寸，且凹槽G1的顶部横向尺寸等于最大横向尺寸D1，且凹槽G1的底部横向尺寸可大体上等于凹槽G2的最大横向尺寸D3。由于预切割工艺S1的最大切割宽度D1(即，凹槽G1的最大横向尺寸)宽于预切割工艺S2的最大切割宽度D3(即，凹槽G2的最大横向尺寸)，所以插入件晶片W的内连线结构120不与用于预切割工艺S2中的刀片接触。因此，预切割工艺S1(即，凹槽G1)可保护插入件晶片W的内连线结构120在预切割工艺S2期间不受损坏，且可防止插入件晶片W中的内连线结构120的裂纹问题(或碎裂问题)。
在一些其它实施例中，凹槽G1的底部横向尺寸大于凹槽G2的最大横向尺寸D3，使得凹槽G1的水平底部轮廓可形成于凹槽G1的竖直侧壁与凹槽G2的锥形侧壁之间。此外，凹槽G1的深度D2可大于或小于凹槽G2的深度D4。
在一些其它实施例中，省略插入件晶片W的预切割工艺S2。换句话说，只对插入件晶片W的正表面执行预切割工艺S1，且只有凹槽G1形成于插入件晶片W的正表面上，如图1B中所示出。在另外一些其它实施例中，如图2中所示出，可通过对插入件晶片W的由图案化光刻胶层PR覆盖的正表面执行的刻蚀工艺S3形成凹槽G1。可通过干式刻蚀工艺、湿式刻蚀工艺、其组合或类似物刻蚀由图案化光刻胶层PR覆盖的插入件晶片W。在一些替代性实施例中，可通过刻蚀工艺(即，如图2中所示出的刻蚀工艺S3)形成凹槽G1，且随后可通过晶片划片工艺(即，如图1C中所示出的预切割工艺S2)形成凹槽G2。
图3为根据本公开的一些替代性实施例的示意性地示出通过刻蚀工艺在插入件晶片中形成凹槽的横截面视图。
在一些实施例中，如图3中所示出，可执行等离子划片(即，博世工艺(Boschprocess))以刻蚀插入件晶片W。在刻蚀插入件晶片W之后，图案化光刻胶层PR可具有锥形侧壁、通过图案化光刻胶层PR显露的插入件晶片W的部分，且凹槽G1可具有由等离子划片工艺产生的波浪形或扇形侧壁SW。
参考图1D，在插入件晶片W的正表面上形成凹槽G1和凹槽G2之后，设置半导体管芯160a和半导体管芯160b且通过例如晶片上芯片(chip-on-wafer；CoW)接合工艺安装到插入件晶片W的正表面上。半导体管芯160a和半导体管芯160b通过凸块接合点电连接到插入件晶片W。半导体管芯160a的导电通孔162a和半导体管芯160b的导电通孔162b可通过焊料材料层140电连接到导电通孔130。在一些实施例中，导电通孔130包含铜微凸块、Cu/Ni微凸块或类似物，且导电通孔162a和导电通孔162b包含铜微凸块、Cu/Ni微凸块或类似物。导电通孔130的结构可与导电通孔160a和导电通孔160b的结构相同或不同。半导体管芯160a可包含逻辑管芯，且半导体管芯160b可包含存储器管芯。在一些替代性实施例中，半导体管芯160a可包含系统芯片(system-on-chip；SOC)逻辑管芯，且半导体管芯160b可包含高带宽存储器(high bandwidth memory；HBM)立方体，其中HBM立方体中的每一个可包含堆叠存储器管芯。
底部填充物170可形成于插入件晶片W的内连线结构120上方。底部填充物170设置在插入件晶片W与半导体管芯160a和半导体管芯160b之间，使得密封焊料材料层140和导电通孔130、导电通孔162a以及导电通孔162b。底部填充物170可充当应力缓冲器以提高导电通孔130与导电通孔162a和导电通孔162b之间的电连接的可靠性。
参考图1E和图1F，在插入件晶片W上形成绝缘密封体180以覆盖半导体管芯160a、半导体管芯160b以及底部填充物170。绝缘密封体180填充凹槽G1和凹槽G2。可通过包覆成型工艺或膜沉积工艺形成绝缘密封体180。在执行用于形成绝缘密封体180的包覆成型(over-mold)工艺或膜沉积工艺之后，如图1F中所示出，可执行第一研磨工艺以部分地去除绝缘密封体180。在执行第一研磨工艺之后，半导体管芯160a和半导体管芯160b由具有减小的厚度的绝缘密封体180a覆盖。在一些实施例中，第一研磨工艺包含机械研磨工艺、CMP工艺或其组合。举例来说，绝缘密封体180和绝缘密封体180a的材料包含环氧模塑化合物或其它合适的介电材料。
参考图1F和图1G，设置包含形成于其上的剥离层DB的晶片形式载体C。将图1F中所示出的所产生结构上下翻转以安装到由晶片形式载体C承载的剥离层DB上，且从晶片开槽带T1剥离图1F中所示出的所产生结构。换句话说，图1F中所示出的所产生结构从晶片开槽带T1转移接合到由晶片形式载体C承载的剥离层DB。在转移接合之后，将绝缘密封体180a附接到剥离层DB，使得插入件晶片W的背表面可面朝上。
参考图1G和图1H，从插入件晶片W的背表面执行薄化工艺，使得插入件晶片W的半导体衬底110薄化，且在插入件晶片W的背表面处显露半导体穿孔150的部分。可通过机械研磨工艺、CMP工艺、刻蚀工艺、其组合或其它合适的去除工艺来薄化插入件晶片W的半导体衬底110。在执行薄化工艺之后，形成包含半导体衬底110'、内连线结构120、导电通孔130、焊料材料层140以及半导体穿孔150的插入件晶片W'。在一些实施例中，半导体穿孔150的已显露表面与半导体衬底110'的背表面大体上齐平。在一些其它实施例中，半导体穿孔150的已显露表面由于研磨选择性而稍微低于半导体衬底110'的背表面。在一些替代性实施例中，半导体穿孔150的已显露表面由于研磨选择性而稍微高于半导体衬底110'的背表面。
参考图1I，介电层185和导电端子190形成于插入件晶片W'上，其中介电层185覆盖半导体衬底110'的背表面，且导电端子190电连接到穿透半导体衬底110'的半导体穿孔150。在一些实施例中，介电层185可包含氮化硅层或其它合适的介电层，且导电端子190可包含凸块下金属化(under bump metallization；UBM)层192和落在UBM层192上的受控塌陷芯片连接(controlled collapse chip connection；C4)凸块194，其中UBM层192设置在C4凸块194与半导体穿孔150之间。
参考图1I和图1J，可执行框架安装工艺，使得包含介电层185和形成于其上的导电端子190的插入件晶片W'可翻转且安装在框架F上。在框架安装工艺期间，导电端子190可附接到框架F，且从绝缘密封体180a剥离晶片形式载体C和剥离层DB。在从绝缘密封体180a剥离晶片形式载体C和剥离层DB之后，可执行第二研磨工艺以部分地去除绝缘密封体180a，直到半导体管芯160a的背表面和半导体管芯160b的背表面显露。在执行第二研磨工艺之后，由具有减小的厚度的绝缘密封体180b横向地密封半导体管芯160a和半导体管芯160b。在一些实施例中，第二研磨工艺包含机械研磨工艺、CMP工艺或其组合。
参考参考1J、图1K以及图1L，设置晶片锯切带T2。将图1J中所示出的所产生结构上下翻转以安装到晶片锯切带T2上，且从框架F剥离图1J中所示出的所产生结构。换句话说，图1J中所示出的所产生结构从框架F转移接合到晶片锯切带T2。将绝缘密封体180b以及半导体管芯160a的背表面和半导体管芯160b的背表面附接到晶片锯切带T2，使得插入件晶片W'的背表面可再次面朝上。
从插入件晶片W'的背表面执行晶片锯切工艺S4以锯切插入件晶片W'和绝缘密封体180b。沿插入件晶片W'的凹槽G1、凹槽G2或交叉切割道SL执行晶片锯切工艺S4，以便获得多个单体化封装结构P。预切割工艺S1的最大切割宽度D1和预切割工艺S2的最大切割宽度D3可宽于晶片锯切工艺S4的最大切割宽度D5。换句话说，凹槽G1的最大横向尺寸D1和凹槽G2的最大横向尺寸D3(图1J和图1K中所示出)可宽于晶片锯切工艺S4的最大切割宽度D5。在一些实施例中，预切割工艺S1为激光开槽工艺，预切割工艺S2为晶片划片工艺(即，第一片锯工艺)，且晶片锯切工艺S4为斜角阶梯切割工艺(即，第二片锯工艺)，其中预切割工艺S1(即，激光开槽工艺)的最大切割宽度D1和预切割工艺S2的最大切割宽度D3宽于晶片锯切工艺S4(即，第二片锯工艺)的最大切割宽度D5。由于预切割工艺S1的最大切割宽度D1(即，凹槽G1的最大横向尺寸)宽于预切割工艺S2的最大切割宽度D3(即，凹槽G2的最大横向尺寸)和晶片锯切工艺S4的最大切割宽度D5，所以每一单体化封装结构P的内连线结构120可不与用于预切割工艺S2和晶片锯切工艺S4中的刀片接触。因此，预切割工艺S1(即，凹槽G1)可保护内连线结构120在预切割工艺S2和晶片锯切工艺S4期间不受损坏，且可防止封装结构P中的内连线结构120的裂纹问题(或碎裂问题)。
如图1L中所示出，封装结构P中的每一个可分别包含插入件100、半导体管芯160a和半导体管芯160b以及绝缘密封体180b'。插入件100包含半导体衬底110'和设置在半导体衬底110'上的内连线结构120'、设置在内连线结构120'上的导电通孔130、焊料材料层140以及半导体穿孔150。插入件100的半导体衬底110'可包含第一部分110a和设置在第一部分110a上的第二部分110b，其中第一内连线结构120设置在第二部分110b上，且第一部分110a的第一最大横向尺寸大于第二部分110b的第二最大横向尺寸。半导体衬底110'可包含分布在插入件100的周边区中的环形凹槽或凹部G1'和环形凹槽或凹部G2'。环形凹槽G1'与环形凹槽G2'连通。
与图1A类似，内连线结构120'可包含层间介电膜124和嵌入于层间介电膜124中的内连线布线122。半导体管芯160a和半导体管芯160b设置在内连线结构120'上方且电连接到内连线结构120'。绝缘密封体180b'设置在半导体衬底110'的第一部分100a上，其中绝缘密封体180b'横向地密封半导体管芯160a和半导体管芯160b以及半导体衬底110'的第二部分100b。在一些实施例中，绝缘密封体180b'可填充插入件100的环形凹槽G1'和环形凹槽G2'。
绝缘密封体180b'可覆盖内连线结构120'的侧壁和半导体衬底110'的第二部分110b的侧壁，且绝缘密封体180b'的外侧壁与半导体衬底110'的第一部分110a的侧壁大体上对准。在一些实施例中，绝缘密封体180b'包含主体部分182和环部分184，其中主体部分182横向地密封半导体管芯160a和半导体管芯160b，且环部分184沿内连线结构120'的侧壁和半导体衬底110'的第二部分110b的侧壁延伸。在一些实施例中，半导体管芯160a和半导体管芯160b通过凸块接合点电连接到插入件100的内连线结构120'。封装结构P进一步包含设置在半导体管芯160a和半导体管芯160b与半导体衬底110'的第二部分110b之间的底部填充物170，其中第一底部填充物170密封凸块接合点，且凸块接合点通过底部填充物170与绝缘密封体180b'间隔开。
在一些实施例中，环形凹槽G1'的最大横向尺寸在约27.5微米到约45微米范围内，且环形凹槽G1'的深度在约5微米到约10微米范围内。在一些实施例中，环形凹槽G2'的最大横向尺寸在约25微米到约42.5微米范围内，且环形凹槽G2'的深度在约20微米到约50微米范围内。如图1L中所示出，环形凹槽G1'的最大横向尺寸可大于环形凹槽G2'的最大横向尺寸，环形凹槽G1'的深度可大体上等于环形凹槽G2'的深度。在一些其它实施例中，环形凹槽G1'的深度可大于或小于环形凹槽G2'的深度。此外，环形凹槽G1'的深度可大于内连线结构120'的厚度，且环形凹槽G1'的深度可小于半导体穿孔150的高度。环形凹槽G1'的深度与环形凹槽G2'的深度的总和可小于半导体穿孔150的高度和半导体衬底110'的厚度。
环部分184可包含设置在环形凹槽G1'中的第一环部分184a和设置在环形凹槽G2'中的第二环部分184b。在一些实施例中，第一环部分184a的最大横向尺寸在约27.5微米到约45微米范围内，且第一环部分184a的深度在约5微米到约10微米范围内。在一些实施例中，第二环部分184b的最大横向尺寸在约25微米到约42.5微米范围内，且第二环部分184b的深度在约20微米到约50微米范围内。
参考图1M，设置包含导电端子210的电路衬底200。电路衬底200可为印刷电路板，且导电端子210可包含导电球(例如BGA球)。封装结构P安装于电路衬底200上且通过导电端子190电连接到电路衬底200。在一些实施例中，封装结构P进一步包含底部填充物300和导电端子190，导电端子190和导电端子210设置在电路衬底200的相对侧上。此外，第二底部填充物300设置在插入件100与电路衬底200之间以密封导电端子190。
如图1L和图1M所示出，环形凹槽G1'的深度可大于内连线结构120'的厚度。环形凹槽G1'可具有顶部横向尺寸和小于顶部横向尺寸的底部横向尺寸。在一些实施例中，环形凹槽G1'的顶部横向尺寸为环形凹槽G1'的最大横向尺寸，且环形凹槽G1'的底部横向尺寸可大体上等于环形凹槽G2'的最大横向尺寸。在一些实施例中，环形凹槽G1'包含锥形内侧壁，且凹槽G2'包含大体上竖直侧壁。环形凹槽G1'的底部横向尺寸可大于环形凹槽G2'的最大横向尺寸，使得环形凹槽G1'的水平底部轮廓可形成于环形凹槽G1'的竖直侧壁与环形凹槽G2'的锥形侧壁之间。
在上述实施例中，由于通过至少一种非接触预切割工艺(例如激光开槽工艺、刻蚀开槽工艺)接着通过另一晶片预切割工艺和晶片锯切工艺来预切割插入件晶片，所以插入件晶片的内连线结构可与用于随后执行的晶片预切割工艺和晶片锯切工艺中的刀片保持距离，使得插入件晶片的内连线结构可不与用于随后执行的晶片预切割工艺和晶片锯切工艺中的刀片接触，且不因用于随后执行的晶片预切割工艺和晶片锯切工艺中的刀片损坏。因此，可防止插入件晶片中的内连线结构的裂纹问题或碎裂问题。
根据本公开的一些实施例，提供一种封装结构，包含插入件、至少一个半导体管芯以及绝缘密封体。所述插入件包含半导体衬底和设置在所述半导体衬底上的内连线结构，所述内连线结构包含层间介电膜和嵌入于所述层间介电膜中的内连线布线，所述半导体衬底包含第一部分和设置在所述第一部分上的第二部分，内连线结构设置在所述第二部分上，且所述第一部分的第一最大横向尺寸大于所述第二部分的第二最大横向尺寸。至少一个半导体管芯设置在所述内连线结构上方且电连接到所述内连线结构。绝缘密封体设置在所述第一部分上，其中所述绝缘密封体横向地密封所述至少一个半导体管芯和所述第二部分。在一些实施例中，所述绝缘密封体覆盖所述内连线结构的侧壁和所述第二部分的侧壁，且所述绝缘密封体的外侧壁与所述第一部分的侧壁大体上对准。在一些实施例中，所述绝缘密封体包含主体部分和环部分，所述主体部分横向地密封所述至少一个半导体管芯，且所述环部分沿所述内连线结构的侧壁和所述第二部分的所述侧壁延伸。在一些实施例中，所述至少一个半导体管芯通过凸块接合点电连接到所述插入件。在一些实施例中，所述结构进一步包含设置在所述至少一个半导体管芯与所述插入件的第二部分之间的第一底部填充物，其中所述第一底部填充物密封凸块接合点，且所述凸块接合点通过所述第一底部填充物与所述绝缘密封体间隔开。在一些实施例中，所述插入件进一步包含穿透所述半导体衬底的半导体穿孔。在一些实施例中，结构进一步包含电路衬底、第一导电端子、第二导电端子以及第二底部填充物。第一导电端子设置在所述电路衬底上且电连接到所述电路衬底。第二导电端子设置在所述电路衬底上且电连接到所述电路衬底，其中所述插入件的所述半导体穿孔通过所述第一导电端子电连接到所述电路衬底，且所述第一导电端子和所述第二导电端子设置在所述电路衬底的相对侧上。第二底部填充物设置在所述插入件与所述电路衬底之间，其中所述第二底部填充物密封所述第一导电端子。
根据本公开的一些其它实施例，提供一种封装结构，包含插入件、至少一个半导体管芯以及绝缘密封体。所述插入件包含半导体衬底和设置在所述半导体衬底上的内连线结构，所述内连线结构包含层间介电膜和嵌入于所述层间介电膜中的内连线布线，且所述半导体衬底包含分布在所述插入件的周边区中的环形凹槽，其中所述环形凹槽包括波浪形侧壁。所述至少一个半导体管芯设置在所述内连线结构上方且电连接到所述内连线结构。所述绝缘密封体设置在所述插入件上，其中所述绝缘密封体密封所述至少一个半导体管芯且填充所述插入件的环形凹槽。在一些实施例中，所述绝缘密封体覆盖所述内连线结构的侧壁且延伸到所述环形凹槽中，且所述绝缘密封体的外侧壁与所述半导体衬底的侧壁大体上对准。在一些实施例中，所述绝缘密封体包含主体部分和环部分，所述主体部分横向地密封所述至少一个半导体管芯，所述环部分覆盖所述内连线结构的侧壁且填充所述环形凹槽，且所述环部分与所述半导体衬底接触。在一些实施例中，所述至少一个半导体管芯通过凸块接合点电连接到所述插入件。在一些实施例中，所述结构进一步包含设置在所述至少一个半导体管芯与所述插入件的所述第二部分之间的第一底部填充物，其中所述第一底部填充物密封所述凸块接合点，且所述凸块接合点通过所述第一底部填充物与所述绝缘密封体间隔开。在一些实施例中，所述插入件进一步包含穿透所述半导体衬底的半导体穿孔。在一些实施例中，所述结构进一步包含电路衬底、第一导电端子以及第二导电端子。所述第一导电端子设置在所述电路衬底上且电连接到所述电路衬底。所述第二导电端子设置在所述电路衬底上且电连接到所述电路衬底，其中所述插入件的半导体穿孔通过第一导电端子电连接到所述电路衬底，且所述第一导电端子和所述第二导电端子设置在所述电路衬底的相对侧上。第二底部填充物设置在所述插入件与所述电路衬底之间，其中所述第二底部填充物密封所述第一导电端子。
根据本公开的一些其它实施例，提供一种制造封装结构的方法，包含以下步骤。设置包含半导体衬底和内连线结构的插入件晶片，所述内连线结构设置在所述半导体衬底上，其中所述内连线结构包含层间介电膜和嵌入于所述层间介电膜中的内连线布线。通过非接触预切割工艺将交叉凹槽形成于插入件晶片上，其中所述交叉凹槽延伸穿过所述内连线结构且所述半导体衬底通过所述交叉凹槽显露。半导体管芯放置到包含形成于其上的所述交叉凹槽的插入件晶片。绝缘密封体形成于所述插入件晶片上方以横向地密封所述半导体管芯且填充所述交叉凹槽。执行晶片锯切工艺以沿形成于所述插入件晶片上的所述交叉凹槽锯切所述绝缘密封体和所述插入件晶片，以便获得封装结构，其中所述凹槽的最大横向尺寸宽于所述晶片锯切工艺的切割宽度。在一些实施例中，通过激光开槽工艺或刻蚀工艺形成所述交叉凹槽，所述晶片锯切工艺包括片锯工艺，且所述激光开槽工艺的第一切割宽度或所述刻蚀工艺的第一切割宽度宽于所述片锯工艺的第二切割宽度。在一些实施例中，通过激光开槽工艺接着通过划片工艺形成所述交叉凹槽，所述划片工艺包括片锯工艺，且所述激光开槽工艺的第一切割宽度宽于所述片锯工艺的第二切割宽度。在一些实施例中，从所述半导体晶片的其上放置有所述半导体管芯的第一表面执行所述激光开槽工艺或所述刻蚀工艺，从所述半导体晶片的第二表面执行所述片锯工艺，且所述第一表面与所述第二表面相对。在一些实施例中，所述方法进一步包含：在形成绝缘密封体之后且在执行所述晶片锯切工艺之前，执行薄化工艺以薄化所述半导体衬底，直到嵌入于所述半导体衬底中的半导体穿孔显露；以及形成电连接到所述半导体穿孔的导电端子。在一些实施例中，所述方法进一步包含：在执行所述晶片锯切工艺之后，在电路衬底上安装所述封装结构，其中所述封装结构通过所述导电端子电连接到所述电路衬底；以及在所述封装结构与所述电路衬底之间形成底部填充物以密封所述导电端子。
前文概述若干实施例的特征，使得本领域的技术人员可更好地理解本公开的各方面。本领域的技术人员应了解，其可容易地将本公开用作设计或修改用于实现本文中所引入的实施例的相同目的和/或达成相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到，这种等效构造并不脱离本公开的精神和范围，且本领域的技术人员可在不脱离本公开的精神和范围的情况下在本文中作出各种改变、替代以及更改。

Claims (1)

1.一种封装结构，包括：
插入件，包括：
半导体衬底；以及
内连线结构，设置在所述半导体衬底上，所述内连线结构包括层间介电膜和嵌入于所述层间介电膜中的内连线布线，所述半导体衬底包括第一部分和设置在所述第一部分上的第二部分，所述内连线结构设置在所述第二部分上，且所述第一部分的第一最大横向尺寸大于所述第二部分的第二最大横向尺寸；
至少一个半导体管芯，设置在所述内连线结构上方且电连接到所述内连线结构；以及
绝缘密封体，设置在所述第一部分上，其中所述绝缘密封体横向地密封所述至少一个半导体管芯和所述第二部分。
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