TWI614817B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

Info

Publication number
TWI614817B
TWI614817B TW104129283A TW104129283A TWI614817B TW I614817 B TWI614817 B TW I614817B TW 104129283 A TW104129283 A TW 104129283A TW 104129283 A TW104129283 A TW 104129283A TW I614817 B TWI614817 B TW I614817B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
circuit die
redistribution structure
forming
sealing material
Prior art date
Application number
TW104129283A
Other languages
English (en)
Other versions
TW201622021A (zh
Inventor
余振華
葉德強
陳憲偉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201622021A publication Critical patent/TW201622021A/zh
Application granted granted Critical
Publication of TWI614817B publication Critical patent/TWI614817B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本申請案係揭露封裝之結構及其形成方法。在一實施例中，方法包含形成背面重佈結構，以及在形成背面重佈結構之後，將第一積體電路晶粒黏附至背面重佈結構。方法進一步包含以密封材料將第一積體電路晶粒封裝在背面重佈結構上，在密封材料上形成前面重佈結構，以及將第二積體電路晶粒電耦合至第一積體電路晶粒。第二積體電路晶粒係經由第一外部電連接物而電耦合至第一積體電路晶粒，該第一外部電連接物係機械附接至前面重佈結構。

Description

封裝結構及其形成方法
本揭露係關於封裝結構及其形成方法。
半導體裝置係用於許多電子應用，例如個人電腦、行動電話、數位相機以及其他電子設備。半導體裝置的製造典型係藉由在半導體基板上方依序沉積絕緣或介電層、傳導層以及材料的半導體體層，並且使用微影蝕刻將不同的材料層圖案化，以於其上形成電路組件與元件。典型係在半導體晶圓上製造數十或數百個積體電路。藉由沿著切割線切割積體電路而將個別晶粒單粒化。而後，例如，將個別晶粒分別封裝、封裝為多晶片模組、或是其他型式的封裝。
半導體工業藉由持續縮小最小特徵尺寸而繼續改良各種電子組件(例如，電晶體、二極體、電阻器、電容器等)的整合密度，使得在給定面積上整合更多的組件。在一些應用中，較小的電子組件，例如積體電路晶粒，亦需要較小的封裝，其使用比習知封裝更小的面積。
本揭露的一些實施例係提供一種方法，其包括形成背面重佈結構；在形成該背面重佈結構之後，將第一積體電路晶粒黏附至該背面重佈結構；以密封材料將該第一積體電路晶粒封裝在該背面 重佈結構上；在該密封材料上形成前面重佈結構；以及將第二積體電路晶粒電耦合至該第一積體電路晶粒，第二積體電路晶粒係經由第一外部電連接物而電耦合至該第一積體電路晶粒，該第一外部電連接物係機械附接至該前面重佈結構。
本揭露的一些實施例係提供一種方法，其包括形成第一重佈結構；將第一積體電路晶粒的背面黏附至該第一重佈結構；在該黏附之後，以密封材料將該第一積體電路晶粒封裝在該第一重佈結構上；在該密封材料上，形成第二重佈結構，該第一積體電路晶粒的主動側係面對該第二重佈結構；以及使用第一外部電連接物，將第二積體電路晶粒附接至該第二重佈結構，該第一外部電連接物係機械附接至該第二重佈結構。
本揭露的一些實施例係提供一種結構，其包括第一封裝，其包括第一積體電路晶粒，其具有主動側以及與該主動側對立的背面，密封材料，其係側向封裝該第一積體電路晶粒，該密封材料的第一表面係與該第一積體電路晶粒的主動側上之晶粒連接物的表面共平面，該密封材料的第二表面係與該密封材料的該第一表面對立，第一重佈結構，其係位在該密封材料的該第一表面上，以及第二重佈結構，其係位在該密封材料的該第二表面上；以及第二積體電路晶粒，其係經由該第一外部電連接物而電耦合至該第一積體電路晶粒，該第一外部電連接物係機械附接至該第一重佈結構。
20‧‧‧載體基板
22‧‧‧釋放層
24‧‧‧介電層
28‧‧‧介電層
26‧‧‧金屬化圖案
30‧‧‧通路
40‧‧‧背面重佈結構
42‧‧‧貫穿通路
44‧‧‧積體電路晶粒
46‧‧‧黏著劑
48‧‧‧墊
50‧‧‧鈍化膜
52‧‧‧晶粒連接物
54‧‧‧介電材料
60‧‧‧密封材料
80‧‧‧前面重佈結構
70、76‧‧‧介電層
72‧‧‧金屬化圖案
74‧‧‧通路
82‧‧‧墊
100‧‧‧第一封裝
102‧‧‧第二封裝
84‧‧‧外部電連接物
112‧‧‧背面膜
114‧‧‧開口
116‧‧‧墊
118‧‧‧外部電連接物
110‧‧‧膠帶
120‧‧‧環氧助焊劑
130‧‧‧前面膜
140、142‧‧‧積體電路晶粒
由以下詳細說明與附隨圖式得以最佳了解本揭露之各方面。注意，根據產業之標準實施方式，各種特徵並非依比例繪示。實際上，為了清楚討論，可任意增大或縮小各種特徵的尺寸。
圖1至圖13係根據一些實施例說明在形成層疊封裝結構(package-on-package)的製程過程中的中間步驟之剖面圖。
圖14係根據一些實施例說明層疊封裝結構的概示圖。
圖15係根據一些實施例說明層疊封裝結構的概示圖。
圖16係根據一些實施例說明層疊封裝結構的概示圖。
圖17係根據一些實施例說明層疊封裝結構的概示圖。
圖18係根據一些實施例說明晶粒封裝(die-on-package)結構。
以下揭示內容提供許多不同的實施例或範例，用於實施本申請案之不同特徵。元件與配置的特定範例之描述如下，以簡化本申請案之揭示內容。當然，這些僅為範例，並非用於限制本申請案。例如，以下描述在第二特徵上或上方形成第一特徵可包含形成直接接觸的第一與第二特徵之實施例，亦可包含在該第一與第二特徵之間形成其他特徵的實施例，因而該第一與第二特徵並非直接接觸。此外，本申請案可在不同範例中重複元件符號與/或字母。此重複係為了簡化與清楚之目的，而非支配不同實施例與/或所討論架構之間的關係。
再者，本申請案可使用空間對應語詞，例如「之下」、「低於」、「較低」、「高於」、「較高」等類似語詞之簡單說明，以描述圖式中一元件或特徵與另一元件或特徵的關係。空間對應語詞係用以包括除了圖式中描述的位向之外，裝置於使用或操作中之不同位向。裝置或可被定位(旋轉90度或是其他位向)，並且可相應解釋本申請案使用的空間對應描述。
本文所述之實施例可討論為特定內容，稱為具有扇出或扇入晶圓層級封裝之層疊封裝或是晶粒封裝架構。其他實施例考量其他應用，例如不同的封裝型式或是不同的架構，其對於該技藝之技術人士而言在讀取本揭露之後係為明顯的。應理解本文所述的實施例 不需要說明存在於結構中的每個組件或特徵。例如，當討論組件之一可足以傳達實施例的各方面時，可在圖式中省略複數個相同的組件。再者，本文所述的方法實施例之討論係以特定順序進行；然而，其他方法實施例可以任何邏輯順序進行。
圖1至圖13係根據一些實施例說明在形成層疊封裝結構(package-on-package)的製程過程中的中間步驟之剖面圖。圖1係說明載體基板20、形成於載體基板20上的釋放層22、以及形成於釋放層22上的介電層24。載體基板20可為玻璃載體基板、陶瓷載體基板、或類似物。載體基板20可為晶圓。釋放層22可由聚合物為基底的材料所形成，可從後續步驟所形成的覆蓋結構沿著載體結構20而將其移除。在一些實施例中，釋放層22係環氧化合物為基底的熱釋放材料，當其被加熱時會失去其黏著性質，例如光熱轉換(Light-to-Heat-Conversion，LTHC)釋放塗覆。在其他實施例中，釋放層22可為紫外光(UV)膠，當其暴露至UV光時會失去其黏著性質。釋放層22可被調配誠為液體並且硬化、可為壓層在載體基板20上的壓層膜、或可為類似物。釋放層22的頂部表面可為水平的，並且可具有高度共平面性。
介電層24係形成在釋放層22上。介電層24的底部表面可接觸釋放層22的頂部表面。在一些實施例中，介電層24係由聚合物所形成，例如聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺、苯并環丁烯(benzocyclobutene，BCB)、或類似物。在其他實施例中，介電層24係由氮化物形成，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼摻雜的磷矽酸鹽玻璃(BPSG)、或類似物；或類似物。介電層24可由任何可接受的沉積製程所製成，例如旋塗、化學氣相沉積(CVD)、壓層、類似方法、或其結合。
參閱圖2，形成背面重佈結構40。背面重佈結構40可包括任何數目的介電層28、金屬化圖案26與通路30。如圖所述，背面 重佈結構40包含三個介電層28，其各自具有個別的金屬化圖案26。
在介電層24上先形成金屬化圖案26。形成金屬化圖案型26，例如，在介電層24上方，形成晶種層(未繪示)。在一些實施例中，晶種層係金屬層，其可為單層、或是包括由不同材料形成的複數個子層之複合層。在一些實施例中，晶種層包括鈦層，以及在鈦層上方的銅層。例如，可使用物理氣相沉積(PVD)或是類似方法，形成晶種層。而後，在晶種層上，形成且圖案化光阻。可藉由旋塗或類似方法形成光阻，並且可將暴露於光用於圖案化。光阻的圖案係對應於金屬化圖案26。圖案化形成開口穿過光阻，以暴露晶種層。在光阻的開口中以及晶種層的暴露部分上，形成傳導材料。可藉由鍍膜方法，例如電鍍或無電鍍或類似方法，形成傳導材料。傳導材料可包括金屬，例如銅、鈦、鎢、鋁或類似物。而後，移除光阻以及其上未有傳導材料形成之部分的晶種層。藉由可接受的灰化或剝除製程，例如使用氧氣電漿或類似方法，移除光阻。一旦移除光阻，使用可接受的蝕刻製程，例如濕式或乾式蝕刻，移除晶種層的暴露部分。晶種層的剩餘部分與傳導材料形成金屬化圖案26。
在金屬化圖案26與介電層24上，形成介電層28。在一些實施例中，介電層28係由聚合物形成，其可為光敏材料，例如PBO、聚亞醯胺、BCB、或類似物，可使用蝕刻遮罩將其圖案化。在其他實施例中，介電層28係由例如氮化矽之氮化物；例如氧化矽、PSG、BSG、BPSG之氧化物；或類似物而形成。可藉由旋塗、壓層、CVD、類似方法、或其組合，形成介電層28。而後，將介電層28圖案化，以形成開口，暴露部分的金屬化圖案26。圖案化為可接受的製程，例如當介電層為光敏材料時，將介電層28暴露至光，或是藉由使用例如非等向性蝕刻之蝕刻方法。
可藉由重複形成金屬化圖案26與介電層28的製程，在 背面重佈結構40中形成一或多個附加的金屬化圖案26。可藉由在下方介電層28的開口中形成晶種層與金屬化圖案26的傳導材料，而在形成金屬化圖案26的過程中，形成通路30。因此，通路30可互連且電耦合各種金屬化圖案。
參閱圖3，形成貫穿通路42。形成貫穿通路42的例子，在背面重佈結構40上方，例如圖式中在最上面的介電層28以及最上面金屬化圖案26的暴露部分，形成晶種層。在一些實施例中，晶種層為金屬層，其可為單層、或是包括由不同材料形成的複數個子層之複合層。在一些實施例中，晶種層包括鈦層，以及在鈦層上方的銅層。例如，可使用PVD或類似方法，形成晶種層。在晶種層上，形成且圖案化光阻。可藉由旋塗或類似方法形成光阻，並且可將其暴露至光用於圖案化。光阻的圖案係對應於貫穿通路。圖案化形成穿過光阻的開口，以暴露晶種層。在光阻的開口中與晶種層的暴露部分上，形成傳導材料。可藉由鍍膜方法，例如電鍍或是無電鍍、或類似方法，形成傳導材料。傳導材料可包括金屬，例如銅、鈦、鎢、鋁、或類似物。移除光阻以及其上未形成傳導材料之晶種層的部分。藉由可接受的灰化或是剝除製程，例如使用氧氣電漿或類似方法，移除光阻。一旦移除光阻，使用可接受的蝕刻製程，例如濕式或乾式蝕刻，移除晶種層的暴露部分。晶種層的剩餘部分與傳導材料形成貫穿通路42。
在圖4中，積體電路晶粒44係藉由黏著劑46而附著至介電層28。如圖所示，附著兩個積體電路晶粒44，以及在其他實施例中，可附著一個積體電路晶粒或是多個積體電路晶粒。在附著至介電層28之前，根據可接受的製程，可處理積體電路晶粒44，以於積體電路晶粒44中形成積體電路。例如，積體電路晶粒44各自包括半導體基板，例如矽、摻雜的或未摻雜的，或是絕緣體上半導體(SOI)基板的主動層。半導體基板可包含其他半導體材料，例如鍺；化合物半導 體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦以及/或銻化銦；合金半導體，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP與/或GaInAsP；其組合。亦可使用其他基板，例如多層或是梯度基板。可在半導體基板中與/或半導體基板上，形成例如電晶體、二極體、電容器、電阻器之裝置，並且可藉由互連結構而互連該裝置，該互連結構的形成係藉由例如在半導體基板的一或多個介電層中的金屬化圖案以形成積體電路。
積體電路晶粒44進一步包括墊48，例如鋁墊，其形成外部連接。墊48係在積體電路晶粒44的個別主動側上。鈍化膜50係在積體電路晶粒44上與部分的墊48上。開口係穿過鈍化膜50至墊48。晶粒連接物52，例如傳導柱(例如包括金屬，例如銅)，係在穿過鈍化膜50的開口中，並且機械耦合且電耦合至個別墊48。例如，可藉由鍍膜方法或類似方法，形成晶粒連接物52。晶粒連接物52電耦合積體電路晶粒44的個別積體電路。為了清楚說明與簡化，圖式係說明在各個積體電路晶粒44上的一個晶粒連接物52，該技藝中具有通常技術者可輕易理解可有超過一個晶粒連接物52存在。
介電材料54係在積體電路晶粒44的主動側上，例如在鈍化膜50與晶粒連接物52上。介電材料54係側向包覆晶粒連接物52，以及介電材料54係與個別積體電路晶粒44側向共同終止。介電材料54可為聚合物，例如PBO、聚亞醯胺、BCB、或類似物；氮化物，例如氮化矽或類似物；氧化物，例如氧化矽、PSG、BSG、BPSG或類似物；類似物、或其組合，並且可藉由旋塗、壓層、CVD、或類似方法而形成。
黏著劑46係在積體電路晶粒的背面上，並且將積體電晶粒44附著至背面重佈結構40，例如圖式中的最上面的介電層28。黏著劑46可為任何合適的黏著劑、環氧化合物、或類似物。黏著劑46可 用於積體電路晶粒44的背面，例如個別半導體晶圓的背面。例如可藉由切割將積體電路晶粒44單粒化，並且例如使用取放工具(pick-and-place tool)藉由黏著劑46附著至介電層28。
在圖5中，在不同組件上，形成密封材料60。密封材料60可為模塑料、環氧化合物、或類似物，並且可藉由壓縮成形、轉移成形或類似方法而使用。在圖6中，對密封材料60進行研磨製程，以暴露貫穿通路42與晶粒連接物52。在研磨製程之後，貫穿通路42、晶粒連接物52以及密封材料60的頂部表面係共平面。在一些實施例中，例如，如果貫穿通路42與晶粒連接物52已經暴露，則可省略研磨。
在圖7中，形成前面重佈結構80。前面重佈結構80可包括任何數目的介電層70與76、金屬化圖案72以及通路74。如圖所示，前面重佈結構80包含介電層70以及兩個介電層76，其各自具有個別的金屬化圖案72。
在密封材料60、貫穿通路42以及晶粒連接物52上，形成介電層70。在一些實施例中，介電層70係由聚合物形成，其可為光敏材料，例如PBO、聚亞醯胺、BCB或類似物，可使用微影蝕刻遮罩而輕易地將其圖案化。在其他實施例中，介電層70係由例如氮化矽之氮化物；例如氧化矽、PSG、BSG、BPSG之氧化物；或類似物而形成。可藉由旋塗、壓層、CVD、類似方法、或其組合，而形成介電層70。而後，將介電層70圖案化，以形成開口，暴露部分的貫穿通路42。圖案化為可接受的製程，例如當介電層為光敏材料時，將介電層暴露至光，或是使用例如非等向性蝕刻的蝕刻方法。
先在介電層70上，形成具有通路74的金屬化圖案72。形成金屬化圖案72的例子，在介電層70上方，形成晶種層(未繪示)。在一些實施例中，晶種層為金屬層，其可為單層、或是包括由不同材 料形成的複數個子層之複合層。在一些實施例中，晶種層包括鈦層，以及在鈦層上方的銅層。例如，可使用PVD或類似方法，形成晶種層。而後，在晶種層上，形成且圖案化光阻。可藉由旋塗或是類似方法形成光阻，並且可將其暴露至光用於圖案化。光阻的圖案係對應於金屬化圖案72。圖案化形成穿過光阻的開口，以暴露晶種層。在光阻的開口中以及在晶種層的暴露部分上，形成傳導材料。可藉由鍍膜方法，例如電鍍或是無電鍍、或類似方法，形成傳導材料。傳導材料可包括金屬，例如銅、鈦、鎢、鋁、或類似物。而後，移除光阻以及未有傳導材料形成於其上的部分晶種層。藉由可接受的灰化或剝除製程，例如使用氧氣電漿或類似方法，移除光阻。一旦移除光阻，使用可接受的蝕刻製程，例如濕式或乾式蝕刻，移除晶種層的暴露部分。晶種層的剩餘部分與傳導材料形成金屬化圖案72與通路74。在下層中的開口中，例如在介電層70的開口中，形成通路74。
在金屬化圖案72與介電層70上，形成介電層76。在一些實施例中，介電層76係由聚合物形成，其可為光敏材料，例如PBO、聚亞醯胺、BCB、或類似物，可使用微影蝕刻遮罩而輕易將其圖案化。在其他的實施例中，介電層76係由例如氮化矽之氮化物；例如氧化矽、PSG、BSG、BPSG的氧化物；或類似物而形成。可藉由旋塗、壓層、CVD、類似方法、或其組合，而形成介電層76。而後，將介電層76圖案化形成開口，以暴露部分的金屬化圖案72。圖案化可為可接受的製程，例如當介電層為光敏材料時，將介電層76暴露至光，或是使用例如非等向性蝕刻之蝕刻方法。
可藉由重複進行形成金屬化圖案72與介電層76的製程，在前面重佈結構80中，形成一或多個附加的金屬化圖案72與介電層76。藉由在下方介電層76的開口中形成晶種層與金屬化圖案72的傳導材料，在形成金屬化圖案72的過程中，形成通路74。因此，通路74 互連且電耦合不同的金屬化圖案。
在圖8中，在前面重佈結構80的外部表面上，形成墊82，其係指凸塊下金屬(UBM)。在所述的實施例中，墊82包含穿過最上面的介電層76上之開口的通路。形成墊82的例子，在最上面的介電層76上方，形成晶種層(未繪示)。在一些實施例中，晶種層為金屬層，其可為單層、或是包括由不同材料形成的複數個子層之複合層。在一些實施例中，晶種層包括鈦層，以及在鈦層上方的銅層。例如，可使用PVD或類似方法，形成晶種層。而後，在晶種層上，形成且圖案化光阻。可藉由旋塗或類似方法形成光阻，並且可將其暴露至光用於圖案化。光阻的圖案係對應於墊82。圖案化形成穿過光阻的開口以暴露晶種層。在光阻的開口中以及在晶種層的暴露部分上，形成傳導材料。可藉由鍍膜方法，例如電鍍或無電鍍、或類似方法，形成傳導材料。傳導材料可包括金屬，例如銅、鈦、鎢、鋁或類似物。而後，移除光阻以及未有傳導材料形成於其上的部分晶種層。藉由可接受的灰化或剝除製程，例如使用氧氣電漿或類似方法，移除光阻。一旦移除光阻，使用可接受的蝕刻製程，例如濕式或乾式蝕刻而移除晶種層的暴露部分。晶種層的剩餘部分與傳導材料形成墊82，其可包含通路。在下方層的開口中，例如最上面的介電層76的開口中，形成通路。
為求方便，圖8所示的結構係指第一封裝100。在所述的實施例中，第一封裝係包括背面重佈結構40、積體電路晶粒44、密封材料60、前面重佈結構80，以及各種電互連與耦合於其中。第一封裝的前面，例如前面重佈結構80所在之側，亦可稱為第一封裝的「面」或「面側」，由於前側係積體電路晶粒44之主動側所面對的封裝之側。如此實施例所述，可繼續製程，並且於第一封裝100上進行。
在圖9中，第二封裝102係附接至第一封裝100。例如，如圖所示，第二封裝102包括基板、在基板上的兩個堆疊的積體電路晶粒、將積體電路晶粒電耦合至基板的打線接合，以及封裝堆疊的積體電路晶粒與打線接合的密封材料。在一範例中，第二封裝102的積體電路晶粒係記憶體晶粒，例如，第二封裝102的積體電路晶粒，例如動態隨機存取記憶體(DRAM)晶粒。第二封裝102係藉由附接至墊82的外部電連接物84而電耦合且機械耦合至第一封裝。在一些實施例中，外部電連接物84可包含低溫可回銲材料，例如焊料，例如無鉛焊料，以及在其他實施例中，外部電連接物84可包含金屬柱。在一些實施例中，外部電連接物84係可控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、或類似物。在一些實施例中，可回焊外部電連接物84，用以將第二封裝102附接至第一封裝的墊82。第二封裝102的積體電路晶粒係經由第二封裝102的打線接合與基板、外部電連接物84以及前面重佈結構80，而電耦合且通信耦合至第一封裝100的積體電路晶粒44。
在圖10中，進行載體基板脫層，使得載體基板20自第一封裝脫離(去接合)。根據一些實施例，脫層包含在釋放層22上投影光，例如雷射光或UV光，因而在光熱下，釋放層22分解，並且可移除載體基板22。而後，結構翻轉並且放置在膠帶110上。而後，在背面重佈結構40上，例如在介電層24上，可任意地形成背面膜112。背面膜112可為類似聚合物膜、環氧化合物、或類似物。在後續製程過中，例如在回焊製程中的熱循環，背面膜112可補償翹曲。
在圖11中，形成穿過介電層24的開口114，以暴露最頂部的金屬化圖案26的部分。例如，可使用雷射鑽孔、蝕刻、或類似方法，形成開口114。
在圖12中，在最頂部的金屬化圖案26上穿過開口 114，形成墊116，例如UBM，以及外部電連接物118，例如焊球，例如球柵陣列(BGA)球。可在開口114中形成墊116，其電連接最頂部的金屬化圖案26。墊116可包括三層傳導材料，例如鈦層、銅層以及鎳層。可使用材料與層的其他配置，例如鉻/鉻-銅合金/銅/金的配置、鈦/鈦鎢/銅的配置、或是銅/鎳/金的配置，用於形成墊116。在介電層24與/或背面膜112上方以及沿著開口114的內部至最頂部的金屬化圖案26，形成各層，而形成墊116。可使用鍍製程，例如電鍍或無電鍍，形成各層，亦可使用其他形成製程，例如濺鍍、蒸發、或PECVD製程。一旦已經形成所欲之層，而後可經由合適的光微影蝕刻遮罩與蝕刻製程以移除不想要的材料並且留下所欲之形狀的墊116，而移除層的部分。在其他實施例中，可省略墊116。
在墊116上，形成外部電連接物118。外部電連接物118可包含低溫可回銲材料，例如焊料，其可為無鉛或含鉛。可使用適當的植球製程，形成外部電連接物118。在其他的實施例中，省略墊116，在金屬化圖案26上直接形成外部電連接物穿過開口114。
在圖13與14中，從膠帶110移除第一封裝100與第二封裝102。因此，形成層疊封裝結構。圖13係說明具有墊116的實施例，以及圖14係說明省略墊116的實施例。
圖15與16係分別說明圖13與14的層疊封裝結構，其具有修飾，包含環氧助焊劑120，其係位在環繞外部電連接物118以及在外部電連接物118與背面膜112(若有)及/或背面重佈結構40的介電層24之間區域中。環氧助焊劑120可形成在外部電連接物118周圍的密封，以防止水氣或是其他汙染物滲入外部電連接物118、墊116、背面膜112與/或介電層24之間的接合。在形成外部電連接物118之後以及在圖12與13中從膠帶110移除封裝之前，可施加環氧助焊劑120。
圖17係說明圖15的層疊封裝結構，其具有含有前面膜 130的修飾。前面膜130可類似於背面膜112，並且可形成在前面重佈結構80上，例如在介電層76上。前面膜130可為類似聚合物膜、樹脂、環氧化合物、或類似物，並且可在附接圖9的第二封裝之前，藉由旋塗或壓層技術而形成。雖未繪示，然而前面膜130可形成在圖16的層疊封裝結構中。
圖18係說明另一實施例。在此實施例中，積體電路晶粒140與142係藉由外部電連接物84而直接附接至第一封裝100的前面重佈結構80。據此，可形成晶粒封裝結構。可併入圖13至17中所討論的封裝之各種修飾。
本文中已經討論層疊封裝結構或晶粒封裝結構的各種修飾。然而，該技藝中具有通常技術者可輕易理解可進行其他修飾，以及各種修飾可併入或在不同組合中省略。例如，(1)可併入或省略墊82與116其中之一或二者；(2)可合併或省略背面膜112與前面膜130其中之一或二者；(3)可合併或省略環氧助焊劑120；或(4)類似物或其組合。如果省略墊82與/或116，則可在金屬化圖案72與26上分別直接形成外部電連接物84與/或118，其可稱為在跡線架構上的凸塊或球。
實施例可達成優點。第一封裝中的一或多個積體電路晶粒可通信耦合至直接附接至第一封裝的一或多個積體電路晶粒，或是包埋在附接至第一封裝之第二封裝中的一或多個積體電路晶粒。具有附接至第一封裝的前面或「面側」的第二封裝與/或積體電路晶粒，可將電耦合在第一封裝與第一封裝外部的積體電路晶粒之電連接做得較短。具有較短的電連接，可降低連接的總電阻。具有降低的電阻，連接的電阻-電容(RC)常數降低，其可增加在電連接上方通訊的電子信號之速度。因此，積體電路晶粒可以增加的速度操作。
第一實施例係一方法。該方法包括形成背面重佈結構，以及在形成背面重佈結構之後，將第一積體電路晶粒黏附在背面 重佈結構。該方法進一步包括以密封材料封裝背面重佈結構上的第一積體電路晶粒，在密封材料上形成前面重佈結構，以及將第二積體電路晶粒電耦合至第一積體電路晶粒。第二積體電路晶粒係經由第一外部電連接物而電耦合至第一積體電路晶粒，該第一外部電連接物係機械附接至前面重佈結構。
另一實施例係一方法。該方法係包括形成第一重佈結構；將第一積體電路晶粒的背面黏附至第一重佈結構；在黏附之後，以密封材料封裝第一重佈結構上的第一積體電路晶粒；在密封材料上形成第二重佈結構，第一積體電路晶粒的主動側係面對第二重佈結構；以及使用第一外部電連接物將第二積體電路晶粒附接至第二重佈結構，第一外部電連接物係機械附接至第二重佈結構。
另一實施例係一結構。該結構包括第一封裝，其包括第一積體電路晶粒、側向封裝第一積體電路晶粒的密封材料、在密封材料之第一表面上的第一重佈結構，以及在密封材料之第二表面上的第二重佈結構。第一積體電路晶粒具有主動側，以及與主動側對立的背面。密封材料的第一表面係與第一積體電路晶粒的主動側上之晶粒連接物的表面共平面。密封材料的第二表面係與密封材料的第一表面對立。該結構進一步包括第二積體電路晶粒，其係經由第一外部電連接物而電耦合至第一積體電路晶粒。第一外部電連接物係機械附接至第一重佈結構。
前述說明概述一些實施例的特徵，因而該技藝之技術人士可更加理解本揭露的各方面。該技藝的技術人士應理解其可輕易使用本揭露作為設計或修飾其他製程與結構的基礎，而產生與本申請案相同之目的以及/或達到相同優點。該技藝之技術人士亦應理解此均等架構並不脫離本揭露的精神與範圍，並且其可進行各種改變、取代與變化而不脫離本揭露的精神與範圍。前述說明概述一些實施例的 特徵，因而該技藝之技術人士可更加理解本揭露的各方面。該技藝的技術人士應理解其可輕易使用本揭露作為設計或修飾其他製程與結構的基礎，而產生與本申請案相同之目的以及/或達到相同優點。該技藝之技術人士亦應理解此均等架構並不脫離本揭露的精神與範圍，並且其可進行各種改變、取代與變化而不脫離本揭露的精神與範圍。
24‧‧‧介電層
26‧‧‧金屬化圖案
40‧‧‧背面重佈結構
42‧‧‧貫穿通路
44‧‧‧積體電路晶粒
46‧‧‧黏著劑
52‧‧‧晶粒連接物
54‧‧‧介電材料
60‧‧‧密封材料
80‧‧‧前面重佈結構
82‧‧‧墊
100‧‧‧第一封裝
102‧‧‧第二封裝
84‧‧‧外部電連接物
112‧‧‧背面膜
118‧‧‧外部電連接物

Claims (10)

  1. 一種形成半導體封裝結構的方法，其包括：形成背面重佈結構；在形成該背面重佈結構之後，將第一積體電路晶粒黏附至該背面重佈結構，該黏附包括施加一黏著劑至該第一積體電路晶粒的一表面上並且將該第一積體電路晶粒放置於該背面重佈結構上，藉由該黏著劑分隔該第一積體電路晶粒的該表面與該背面重佈結構；以密封材料將該第一積體電路晶粒封裝在該背面重佈結構上；在該密封材料上形成前面重佈結構；以及將第二積體電路晶粒電耦合至該第一積體電路晶粒，第二積體電路晶粒係經由第一外部電連接物而電耦合至該第一積體電路晶粒，該第一外部電連接物係機械附接至該前面重佈結構。
  2. 如請求項1所述之方法，進一步包括在該封裝步驟之前形成貫穿通路，其中在該封裝步驟之後，該貫穿通路延伸穿過該密封材料。
  3. 如請求項1所述之方法，進一步包括在該背面重佈結構上形成第二外部電連接物。
  4. 如請求項3所述之方法，進一步包括在該第二外部電連接物附近形成環氧助焊劑。
  5. 如請求項1所述之方法，其中該第二積體電路晶粒係藉由該第一外部電連接物而直接機械附接至該前面重佈結構。
  6. 一種形成半導體封裝結構的方法，其包括：形成第一重佈結構；在形成該第一重佈結構之後，將第一積體電路晶粒的背面黏附 至該第一重佈結構；在該黏附之後，以密封材料將該第一積體電路晶粒封裝在該第一重佈結構上；在該密封材料上，形成第二重佈結構，該第一積體電路晶粒的主動側係面對該第二重佈結構；以及使用第一外部電連接物，將第二積體電路晶粒附接至該第二重佈結構，該第一外部電連接物係機械附接至該第二重佈結構。
  7. 一種半導體封裝結構，其包括：第一封裝，其包括：第一積體電路晶粒，其具有主動側以及與該主動側對立的背面，密封材料，其係側向封裝該第一積體電路晶粒，該密封材料的第一表面係超過該主動側的表面並且與該第一積體電路晶粒的該主動側上之晶粒連接物的表面共平面，該密封材料的第二表面係與該密封材料的該第一表面對立，第一重佈結構，其係位在該密封材料的該第一表面上，第二重佈結構，其係位在該密封材料的該第二表面上；以及第二積體電路晶粒，其係經由第一外部電連接物而電耦合至該第一積體電路晶粒，該第一外部電連接物係機械附接至該第一重佈結構。
  8. 如請求項7所述之半導體封裝結構，進一步包括第二外部電連接物，其係機械附接至該第二重佈結構。
  9. 如請求項8所述之半導體封裝結構，其中該第二外部電連接物係經由該凸塊下金屬層而機械附接至該第二重佈結構。
  10. 如請求項7所述之半導體封裝結構，進一步包括第二封裝，該第二封裝係包括該第二積體電路晶粒，該第二封裝係機械附接至該第一外部電連接物。
TW104129283A 2014-09-05 2015-09-04 封裝結構及其形成方法 TWI614817B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/478,471 2014-09-05
US14/478,471 US10177115B2 (en) 2014-09-05 2014-09-05 Package structures and methods of forming

Publications (2)

Publication Number Publication Date
TW201622021A TW201622021A (zh) 2016-06-16
TWI614817B true TWI614817B (zh) 2018-02-11

Family

ID=55358355

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104129283A TWI614817B (zh) 2014-09-05 2015-09-04 封裝結構及其形成方法

Country Status (5)

Country Link
US (3) US10177115B2 (zh)
KR (1) KR101750143B1 (zh)
CN (1) CN105789062B (zh)
DE (1) DE102014114633A1 (zh)
TW (1) TWI614817B (zh)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8832283B1 (en) * 2010-09-16 2014-09-09 Google Inc. Content provided DNS resolution validation and use
US10050004B2 (en) * 2015-11-20 2018-08-14 Deca Technologies Inc. Fully molded peripheral package on package device
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
US9984960B2 (en) * 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10541226B2 (en) * 2016-07-29 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming the same
US10340206B2 (en) 2016-08-05 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
KR101982044B1 (ko) * 2016-08-31 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
US10276548B2 (en) * 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
TWI587465B (zh) * 2016-10-03 2017-06-11 矽品精密工業股份有限公司 電子封裝件及其製法
US20180114786A1 (en) * 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
CN107978584B (zh) * 2016-10-21 2020-03-31 力成科技股份有限公司 芯片封装结构及其制造方法
US11158619B2 (en) 2016-10-31 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10304801B2 (en) * 2016-10-31 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
KR102647213B1 (ko) * 2016-12-31 2024-03-15 인텔 코포레이션 전자 디바이스 패키지
US10438931B2 (en) 2017-01-16 2019-10-08 Powertech Technology Inc. Package structure and manufacturing method thereof
US9887148B1 (en) * 2017-02-21 2018-02-06 Powertech Technology Inc. Fan-out semiconductor package structure and fabricating method
US11569176B2 (en) * 2017-03-21 2023-01-31 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing thereof
US10157862B1 (en) * 2017-07-27 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10522526B2 (en) * 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10304805B2 (en) 2017-08-24 2019-05-28 Micron Technology, Inc. Dual sided fan-out package having low warpage across all temperatures
US10269773B1 (en) 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10304697B2 (en) * 2017-10-05 2019-05-28 Amkor Technology, Inc. Electronic device with top side pin array and manufacturing method thereof
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
DE102018106038A1 (de) 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte schaltkreis-packages und verfahren zu deren herstellung
US11410918B2 (en) * 2017-11-15 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making an integrated circuit package including an integrated circuit die soldered to a bond pad of a carrier
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
KR102491103B1 (ko) * 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR102395199B1 (ko) 2018-02-22 2022-05-06 삼성전자주식회사 반도체 패키지
US10658287B2 (en) * 2018-05-30 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a tapered protruding pillar portion
US10978408B2 (en) * 2018-06-07 2021-04-13 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US11049805B2 (en) * 2018-06-29 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10515848B1 (en) * 2018-08-01 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
KR102081088B1 (ko) * 2018-08-29 2020-02-25 삼성전자주식회사 반도체 패키지
US11171098B2 (en) * 2018-09-27 2021-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package and manufacturing method thereof
US11049779B2 (en) 2018-10-12 2021-06-29 Dyi-chung Hu Carrier for chip packaging and manufacturing method thereof
US10755979B2 (en) * 2018-10-31 2020-08-25 Ningbo Semiconductor International Corporation Wafer-level packaging methods using a photolithographic bonding material
US11121089B2 (en) * 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10971446B2 (en) 2018-11-30 2021-04-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
DE102019118466A1 (de) * 2018-11-30 2020-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und herstellungsverfahren
US11195823B2 (en) 2019-02-01 2021-12-07 Nanya Technology Corporation Semiconductor package and manufacturing method thereof
US10937736B2 (en) * 2019-06-14 2021-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid integrated circuit package and method
US11056453B2 (en) 2019-06-18 2021-07-06 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with vertical interconnects
US10954745B2 (en) 2019-07-03 2021-03-23 Cnpc Usa Corporation Plug assembly
US11063019B2 (en) * 2019-07-17 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure, chip structure and method of fabricating the same
CN112309998B (zh) * 2019-07-30 2023-05-16 华为技术有限公司 封装器件及其制备方法、电子设备
US11635566B2 (en) * 2019-11-27 2023-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of forming same
KR20210071539A (ko) 2019-12-06 2021-06-16 삼성전자주식회사 인터포저, 반도체 패키지, 및 인터포저의 제조 방법
DE102020116340A1 (de) * 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Gestapelter bildsensorvorrichtung und deren herstellungsverfahren
CN111883521B (zh) * 2020-07-13 2022-03-01 矽磐微电子(重庆)有限公司 多芯片3d封装结构及其制作方法
US11450581B2 (en) * 2020-08-26 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
KR20220047066A (ko) 2020-10-08 2022-04-15 삼성전자주식회사 반도체 패키지 장치
KR20220090793A (ko) 2020-12-23 2022-06-30 삼성전자주식회사 반도체 패키지
US11973070B2 (en) * 2021-02-20 2024-04-30 Sj Semiconductor (Jiangyin) Corporation Double-layer stacked 3D fan-out packaging structure and method making the same
US20220302081A1 (en) * 2021-03-18 2022-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11742323B2 (en) * 2021-04-27 2023-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161833A1 (en) * 2004-01-20 2005-07-28 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20120161315A1 (en) * 2010-12-22 2012-06-28 ADL Engineering Inc. Three-dimensional system-in-package package-on-package structure
US20130075902A1 (en) * 2008-12-05 2013-03-28 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3772066B2 (ja) * 2000-03-09 2006-05-10 沖電気工業株式会社 半導体装置
KR100636259B1 (ko) * 2001-12-07 2006-10-19 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
JP4541753B2 (ja) * 2004-05-10 2010-09-08 新光電気工業株式会社 電子部品実装構造の製造方法
JP4343044B2 (ja) * 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
KR20070051165A (ko) 2005-11-14 2007-05-17 삼성전자주식회사 프리 솔더 범프를 갖는 반도체 패키지와, 그를 이용한 적층패키지 및 그의 제조 방법
CN100452330C (zh) * 2006-01-06 2009-01-14 日月光半导体制造股份有限公司 具有光学组件的半导体封装结构及其封装方法
JP4851794B2 (ja) * 2006-01-10 2012-01-11 カシオ計算機株式会社 半導体装置
US7993972B2 (en) * 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
US20080116564A1 (en) * 2006-11-21 2008-05-22 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving cavity and method of the same
US20080136004A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US8390117B2 (en) * 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
US8456002B2 (en) * 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
KR101486420B1 (ko) * 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
US8093711B2 (en) * 2009-02-02 2012-01-10 Infineon Technologies Ag Semiconductor device
US7989270B2 (en) * 2009-03-13 2011-08-02 Stats Chippac, Ltd. Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
CN101987719B (zh) * 2009-08-03 2012-02-29 财团法人工业技术研究院 感测元件结构与制造方法
US8446017B2 (en) * 2009-09-18 2013-05-21 Amkor Technology Korea, Inc. Stackable wafer level package and fabricating method thereof
US8742561B2 (en) * 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8183696B2 (en) * 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
KR101067109B1 (ko) * 2010-04-26 2011-09-26 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
US8866301B2 (en) * 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
TWI426587B (zh) * 2010-08-12 2014-02-11 矽品精密工業股份有限公司 晶片尺寸封裝件及其製法
US9337116B2 (en) * 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
KR20130005465A (ko) 2011-07-06 2013-01-16 삼성전자주식회사 반도체 스택 패키지 장치
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US8552556B1 (en) * 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
US8633551B1 (en) * 2012-06-29 2014-01-21 Intel Corporation Semiconductor package with mechanical fuse
US9059107B2 (en) * 2012-09-12 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged devices
US9368460B2 (en) * 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9659805B2 (en) * 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050161833A1 (en) * 2004-01-20 2005-07-28 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20130075902A1 (en) * 2008-12-05 2013-03-28 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant
US20120161315A1 (en) * 2010-12-22 2012-06-28 ADL Engineering Inc. Three-dimensional system-in-package package-on-package structure

Also Published As

Publication number Publication date
US20190006317A1 (en) 2019-01-03
US10177115B2 (en) 2019-01-08
KR101750143B1 (ko) 2017-06-22
US10672738B2 (en) 2020-06-02
DE102014114633A1 (de) 2016-03-10
US20160071820A1 (en) 2016-03-10
CN105789062B (zh) 2021-02-26
TW201622021A (zh) 2016-06-16
US20200294967A1 (en) 2020-09-17
CN105789062A (zh) 2016-07-20
KR20160029621A (ko) 2016-03-15
US11444057B2 (en) 2022-09-13

Similar Documents

Publication Publication Date Title
TWI614817B (zh) 封裝結構及其形成方法
US10957616B2 (en) Package structure and method
US11177201B2 (en) Semiconductor packages including routing dies and methods of forming same
TWI669785B (zh) 半導體封裝體及其形成方法
US11443957B2 (en) Metal oxide layered structure and methods of forming the same
US10062648B2 (en) Semiconductor package and method of forming the same
US9741690B1 (en) Redistribution layers in semiconductor packages and methods of forming same
US9859267B2 (en) Package structures and methods of forming the same
KR101823225B1 (ko) 패키지 구조물 및 이의 형성 방법
US10170457B2 (en) COWOS structures and method of forming the same
US20190393195A1 (en) Device and Method for UBM/RDL Routing
TWI574312B (zh) 具有球下金屬層（ｕｂｍ）的封裝及其形成方法
US9754928B2 (en) SMD, IPD, and/or wire mount in a package
TWI724653B (zh) 半導體裝置及其形成方法
TWI771870B (zh) 半導體封裝及其形成方法
TW202134713A (zh) 積體電路封裝及其形成方法
TW202117874A (zh) 封裝結構及其製造方法與封裝體
TWI804148B (zh) 封裝結構及其形成方法
US20200013704A1 (en) Integrated circuit packages and methods of forming same
KR102473590B1 (ko) 반도체 디바이스 및 방법