TW202245212A - 電子裝置 - Google Patents

電子裝置 Download PDF

Info

Publication number
TW202245212A
TW202245212A TW111110751A TW111110751A TW202245212A TW 202245212 A TW202245212 A TW 202245212A TW 111110751 A TW111110751 A TW 111110751A TW 111110751 A TW111110751 A TW 111110751A TW 202245212 A TW202245212 A TW 202245212A
Authority
TW
Taiwan
Prior art keywords
substrate
electronic device
conductive
electronic
conductive pattern
Prior art date
Application number
TW111110751A
Other languages
English (en)
Inventor
紀仁海
陳韻升
何家齊
Original Assignee
群創光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202210036440.7A external-priority patent/CN115332237A/zh
Application filed by 群創光電股份有限公司 filed Critical 群創光電股份有限公司
Publication of TW202245212A publication Critical patent/TW202245212A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/16013—Structure relative to the bonding area, e.g. bond pad the bump connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H01L2224/17055—Bump connectors having different shapes of their bonding interfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17519—Bump connectors having different functions including bump connectors providing primarily thermal dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13069—Thin film transistor [TFT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30101—Resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一種電子裝置，包括基板結構、驅動元件以及導電圖案。驅動元件以及導電圖案形成在基板結構上，其中導電圖案的厚度大於或等於0.5μm且小於或等於15μm。

Description

電子裝置
本發明是有關於一種電子裝置。
隨著科技的進步，電子裝置的發展漸趨成熟。然而，電子裝置仍有許多問題有待改善，例如散熱、電阻電容負載(RC loading)或翹曲等問題。
本揭露提供一種電子裝置，其有助於改善散熱、電阻電容負載或翹曲等問題中的至少一個。
根據本揭露的實施例，電子裝置包括基板結構、驅動元件以及導電圖案。驅動元件以及導電圖案形成在基板結構上，其中導電圖案的厚度大於或等於0.5μm且小於或等於15μm。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
現將詳細地參考本發明的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在圖式和描述中用來表示相同或相似部分。
本揭露通篇說明書與所附的申請專利範圍中會使用某些詞彙來指稱特定元件。本領域具有通常知識者應理解，電子裝置製造商可能會以不同的名稱來指稱相同的元件。本文並不意在區分那些功能相同但名稱不同的元件。在下文說明書與申請專利範圍中，“含有”與“包含”等詞為開放式詞語，因此其應被解釋為“含有但不限定為…”之意。
本文中所提到的方向用語，例如：“上”、“下”、“前”、“後”、“左”、“右”等，僅是參考附圖的方向。因此，使用的方向用語是用來說明，而並非用來限制本揭露。在附圖中，各圖式繪示的是特定實施例中所使用的方法、結構及/或材料的通常性特徵。然而，這些圖式不應被解釋為界定或限制由這些實施例所涵蓋的範圍或性質。舉例來說，為了清楚起見，各膜層、區域及/或結構的相對尺寸、厚度及位置可能縮小或放大。
本揭露中所敘述之一結構（或層別、元件、基材）位於另一結構（或層別、元件、基材）之上/上方，可以指二結構相鄰且直接連接，或是可以指二結構相鄰而非直接連接。非直接連接是指二結構之間具有至少一中介結構（或中介層別、中介元件、中介基材、中介間隔），一結構的下側表面向鄰或直接連接於中介結構的上側表面，另一結構的上側表面向鄰或直接連接於中介結構的下側表面。而中介結構可以是單層或多層的實體結構或非實體結構所組成，並無限制。在本揭露中，當某結構設置在其它結構“上”時，有可能是指某結構“直接”在其它結構上，或指某結構“間接”在其它結構上，即某結構和其它結構間還夾設有至少一結構。
術語“大約”、“等於”、“相等”或“相同”、“實質上”或“大致上”一般解釋為在所給定的值或範圍的20%以內，或解釋為在所給定的值或範圍的10%、5%、3%、2%、1%或0.5%以內。
說明書與申請專利範圍中所使用的序數例如“第一”、“第二”等之用詞用以修飾元件，其本身並不意含及代表該（或該些）元件有任何之前的序數，也不代表某一元件與另一元件的順序、或是製造方法上的順序，該些序數的使用僅用來使具有某命名的元件得以和另一具有相同命名的元件能作出清楚區分。申請專利範圍與說明書中可不使用相同用詞，據此，說明書中的第一構件在申請專利範圍中可能為第二構件。
本揭露中所敘述之電耦合包括電性連接以及耦接。本揭露中所敘述之電性連接，可以指直接連接或間接連接，於直接連接的情況下，兩電路上元件的端點直接連接，而於間接連接的情況下，兩電路上元件的端點之間以一個或多個導體互相連接。本揭露中所敘述之耦接，可以指兩電路上元件的端點之間未以任何導體互相連接。
在本揭露中，厚度、長度與寬度的量測方式可以是採用光學顯微鏡量測而得，厚度或寬度則可以由電子顯微鏡中的剖面影像量測而得，但不以此為限。另外，任兩個用來比較的數值或方向，可存在著一定的誤差。另外，本揭露中所提到的術語“等於”、“相等”、“相同”、“實質上”或“大致上”通常代表落在給定數值或範圍的10%範圍內。此外，用語“給定範圍為第一數值至第二數值”、“給定範圍落在第一數值至第二數值的範圍內”表示所述給定範圍包括第一數值、第二數值以及它們之間的其它數值。若第一方向垂直於第二方向，則第一方向與第二方向之間的角度可介於80度至100度之間；若第一方向平行於第二方向，則第一方向與第二方向之間的角度可介於0度至10度之間。
須知悉的是，以下所舉實施例可以在不脫離本揭露的精神下，可將數個不同實施例中的特徵進行替換、重組、混合以完成其他實施例。各實施例間特徵只要不違背發明精神或相衝突，均可任意混合搭配使用。
除非另外定義，在此使用的全部用語(包含技術及科學用語)具有與本揭露所屬技術領域的技術人員通常理解的相同涵義。能理解的是，這些用語例如在通常使用的字典中定義用語，應被解讀成具有與相關技術及本揭露的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在本揭露實施例有特別定義。
在本揭露中，電子裝置可包括顯示裝置、背光裝置、天線裝置、感測裝置或拼接裝置，但不以此為限。電子裝置可為可彎折或可撓式電子裝置。顯示裝置可為非自發光型顯示裝置或自發光型顯示裝置。天線裝置可為液晶型態的天線裝置或非液晶型態的天線裝置，感測裝置可為感測電容、光線、熱能或超聲波的感測裝置，但不以此為限。在本揭露中，電子元件可包括被動元件與主動元件，例如電容、可變電容、電阻、可變電阻、電感、二極體、電晶體等。二極體可包括發光二極體或非發光二極體。發光二極體可例如包括有機發光二極體(organic light emitting diode，OLED)、次毫米發光二極體(mini LED)、微發光二極體(micro LED)或量子點發光二極體(quantum dot LED)，但不以此為限。拼接裝置可例如是顯示器拼接裝置或天線拼接裝置，但不以此為限。需注意的是，電子裝置可為前述之任意排列組合，但不以此為限。
圖1至圖11分別是根據本揭露的一些實施例的電子裝置的局部剖面示意圖。須說明的是，下文中不同實施例所提供的技術方案可相互替換、組合或混合使用，以在未違反本揭露精神的情況下構成另一實施例。
請參照圖1，電子裝置1可包括基板結構10、驅動元件11以及導電圖案12。驅動元件11以及導電圖案12形成在基板結構10上，其中導電圖案12的厚度T12大於或等於0.5μm且小於或等於15μm。導電圖案12的厚度T12指橫截面(如圖1所示的剖面圖)中導電圖案12在電子裝置1的厚度方向(如方向Z)上的最大厚度。
詳細來說，基板結構10可包括一個或多個基板。以圖1為例，基板結構10可包括第一基板SUB1以及第二基板SUB2，且第一基板SUB1以及第二基板SUB2例如透過黏合層GL而結合，但不以此為限。
第一基板SUB1以及第二基板SUB2各自可包括聚合物薄膜、多孔薄膜(porous film)、玻璃、印刷電路板或由陶瓷、不銹鋼板或金屬板形成的基層，但不以此為限。黏合層GL可包括光學透明黏著劑(optically clear adhesive，OCA)或光學透明樹脂(optically clear resin，OCR)，但不以此為限。
驅動元件11形成在基板結構10上。舉例來說，驅動元件11可透過黃光製程而直接形成在基板結構10的一個基板上。以圖1為例，驅動元件11例如設置在第一基板SUB1上。
圖1示意性繪示出兩個驅動元件11，每一個驅動元件11例如為電晶體且包括閘極GE、源極SE以及汲極DE，但不以此為限。應理解，電子裝置1可包括更多的驅動元件11，且驅動元件11的種類可根據需求改變。舉例來說，驅動元件11可為非晶矽薄膜電晶體、低溫多晶矽薄膜電晶體或氧化物薄膜電晶體(如氧化銦鎵鋅薄膜電晶體)。各種類的薄膜電晶體可為頂閘極或底閘極形式的薄膜電晶體。其中，底閘極氧化物薄膜電晶體的通道層上可形成或不形成蝕刻阻擋層。
每一個驅動元件11可用以控制電子裝置1中的一個或多個電子元件(包括主動元件或被動元件)。這些驅動元件11可直接形成在基板結構10的第一基板SUB1上。替代地，這些驅動元件11可透過引線鍵合(wire bonding)、覆晶技術(flip chip)、膠帶自動黏合(Tape-Automated Bonding，TAB)、表面貼裝技術(Surface mount technology，SMT)或板上晶片封裝(Chip On Board，COB)等方式接合在第一基板SUB1上。當驅動元件11為晶片時，其上可為積體電路、電晶體(如薄膜電晶體)電路、矽控制整流器(silicon controlled rectifiers)或上述的組合，但不以此為限。驅動元件11可先形成在基底(未繪示)上再接合在第一基板SUB1上。基底的材料可包括聚合物、玻璃、矽、砷化鎵、氮化鎵、碳化鎵或藍寶石，但不以此為限。
導電圖案12形成在基板結構10上。舉例來說，導電圖案12可透過黃光製程、電鍍或化鍍直接形成在基板結構10的一個基板上。以圖1為例，導電圖案12例如設置在第二基板SUB2上。進一步來說，第二基板SUB2包括面向第一基板SUB1的第一側S1以及與第一側S1相對的第二側S2，且導電圖案12例如設置在第一側S1上，但不以此為限。在其他實施例中，導電圖案12可設置在第二側S2上。
圖1示意性繪示出五個導電圖案12，五個導電圖案12皆屬於導電層M1，但應理解，導電層M1可包括更多或更少的導電圖案12。此外，導電圖案12的材料可依據導電圖案12的用途來選擇。舉例來說，當導電圖案12用於傳遞訊號時，導電圖案12的材料可選擇導電性高的材料；當導電圖案12用於遮罩電磁波時，導電圖案12的材料可選擇吸收率或反射率高的材料。在一些實施例中，導電圖案12(或導電層M1)的材料可包括銅、鋁、其他高導電的材料或上述的組合，但不以此為限。
根據不同的需求，電子裝置1還可包括其他的元件或膜層。以圖1為例，除了基板結構10、驅動元件11以及導電圖案12(導電層M1)之外，電子裝置1還可包括介電層DL1、介電層DL2、介電層DL3、介電層DL4、介電層DL5、介電層DL6、鈍化層PL1、導電層M2、導電層M3、導電層M4、半導體層(未繪示)、多個接墊P1、多個接墊P2(僅繪示出一個)、多個導電凸塊BP、多個電子元件EC、導電材料CM、底部填充件UF以及保護層PT，但不以此為限。
介電層DL1設置在第一基板SUB1上。介電層DL1可用以保護第一基板SUB1、提升第一基板SUB1的阻水能力或提升第一基板SUB1與導電層(如導電層M2)之間的結合力。舉例來說，介電層DL1的材料可包括氮化矽、氧化矽、非導電無機材料、非導電聚合物薄膜或膠水等，但不以此為限。
導電層M2設置在介電層DL1上。導電層M2例如為圖案化導電層且可包括多個閘極GE以及其他電路(未繪示)。導電層M2的材料可包括銅、鋁、其他高導電的材料或上述的組合，但不以此為限。
介電層DL2設置在介電層DL1上且覆蓋導電層M2。舉例來說，介電層DL2的材料可包括氮化矽、氧化矽、非導電無機材料、非導電聚合物薄膜或膠水等，但不以此為限。
半導體層(未繪示)設置在介電層DL2上。半導體層例如為圖案化半導體層且可包括多個通道圖案，多個通道圖案設置在多個閘極GE的上方。舉例來說，通道圖案可在方向Z上與對應的閘極GE至少部分重疊，但不以此為限。半導體層的材料可包括非晶矽、低溫多晶矽或氧化物薄膜，但不以此為限。
導電層M3設置在半導體層上。導電層M3例如為圖案化導電層且可包括多個導電圖案(如多個源極SE、多個汲極DE、電路CK1、電路CK2，但不以此為限)。導電層M3的材料可包括銅、鋁、其他高導電的材料或上述的組合，但不以此為限。
介電層DL3設置在介電層DL2上且覆蓋導電層M3。舉例來說，介電層DL3的材料可包括氮化矽、氧化矽、非導電無機材料、非導電聚合物薄膜或膠水等，但不以此為限。介電層DL3可包括分別曝露出導電層M3的多個導電圖案(如多個汲極DE、電路CK1以及電路CK2)的多個開口A1。
導電層M4設置在介電層DL3上。導電層M4例如為圖案化導電層且可包括多個導電圖案CP。每一個導電圖案CP可透過對應的開口A1而與對應的汲極DE、電路CK1或電路CK2電性連接。導電層M4的材料可包括銅、鋁、其他高導電的材料或上述的組合，但不以此為限。
介電層DL4設置在介電層DL3上且覆蓋導電層M4。舉例來說，介電層DL4的材料可包括氮化矽、氧化矽、非導電無機材料、非導電聚合物薄膜或膠水等，但不以此為限。介電層DL4可包括分別曝露出導電層M4的多個導電圖案CP的多個開口A2。
鈍化層PL1設置在介電層DL4上。舉例來說，鈍化層PL1的材料可包括有機高分子材料。例如：黑色光阻、灰色光阻、白色光阻或黑矩陣，但不以此為限。鈍化層PL1可包括分別曝露出多個導電圖案CP的多個開口A3。開口A3對應開口A2設置，即開口A3與開口A2在方向Z上至少部分重疊。
多個接墊P1分別對應多個開口A3設置。接墊P1可用以降低導電凸塊BP與導電圖案CP之間形成金屬間化合物(Intermetallic Compound)的機率。舉例來說，接墊P1可包括化學鍍鎳浸金(Electroless Nickel Immersion Gold，ENIG)、化學鍍鎳鈀浸金(Electroless Nickel Electroless Palladium Immersion Gold，ENEPIG)、浸銀(Immersion Silver)、電解金(Electrolytic Gold)或電解鎳(Electrolytic Nickel)，但不以此為限。
介電層DL5設置在第二基板SUB2上，且介電層DL5與多個導電圖案12位於第二基板SUB2的同一側(如第一側S1)。介電層DL5可用以保護第二基板SUB2、提升第二基板SUB2的阻水能力或提升第二基板SUB2與導電層(如導電層M1)之間的結合力。舉例來說，介電層DL5的材料可包括氮化矽、氧化矽、非導電無機材料、非導電聚合物薄膜或膠水等，但不以此為限。
導電層M1設置在介電層DL5上。導電層M1例如為圖案化導電層且可包括多個導電圖案12，但不以此為限。導電層M1的材料可包括銅、鋁、其他高導電的材料或上述的組合，但不以此為限。
介電層DL6設置在介電層DL5上且覆蓋導電層M1。舉例來說，介電層DL6的材料可包括氮化矽、氧化矽、非導電無機材料、非導電聚合物薄膜或膠水等，但不以此為限。介電層DL6可包括分別曝露出多個導電圖案12的多個開口A4(僅繪示出一個)。
多個接墊P2(僅繪示出一個)設置在介電層DL6上，且接墊P2可透過對應的開口A4與對應的導電圖案12電性連接。接墊P2可用以降低導電材料CM與導電圖案12之間形成金屬間化合物的機率。舉例來說，接墊P2可包括化學鍍鎳浸金、化學鍍鎳鈀浸金、浸銀、電解金或電解鎳，但不以此為限。
可透過例如雷射鑽孔製程形成貫孔TH。以圖1為例，貫孔TH可貫穿接墊P1、介電層DL3、介電層DL2、介電層DL1、第一基板SUB1以及黏合層GL，以曝露出接墊P2。
導電材料CM形成在貫孔TH中。以圖1為例，導電材料CM可接觸接墊P2並覆蓋對應的接墊P1，但不以此為限。舉例來說，導電材料CM可包括錫、銅膏或其他金屬材料，且將導電材料CM形成在貫孔TH中的方法可包括印刷，但不以此為限。
多個導電凸塊BP分別設置在多個接墊P1上。導電凸塊BP的材料可包括錫、銅膏、其他金屬材料或異方性導電膜(anisotropic conductive film，ACF)，但不以此為限。
電子元件EC設置在基板結構10上且電耦合至導電圖案12。舉例來說，電子元件EC可透過多個導電凸塊BP而與多個接墊P1接合。如此，電子元件EC可透過導電凸塊BP、接墊P1以及導電圖案CP而電性連接於驅動元件11，且電子元件EC可透過導電凸塊BP、接墊P1、導電圖案CP、電路CK1(或電路CK2)、導電材料CM以及接墊P2而電性連接於導電圖案12(即，電子元件EC直接電性連接於導電圖案12)。另一方面，驅動元件11可透過導電圖案CP、接墊P1、導電凸塊BP、電子元件EC、電路CK1(或電路CK2)、導電材料CM以及接墊P2而電性連接於導電圖案12。
圖1示意性繪示出電子元件EC為發光二極體晶片，但電子元件EC的種類不以此為限。依據不同的應用，電子元件EC也可為電容、電感、可變電容、過濾器(filter)、電阻、二極體、微機電系統(MEMS)或液晶晶片(liquid crystal chip)，但不以此為限。舉例來說，當電子裝置1作為背光裝置或顯示裝置時，電子元件EC可為發光二極體晶片。當電子裝置1作為天線裝置時，可以導電層M1遮罩電磁波，電磁波可經由多個導電圖案12之間的間隙G向上傳遞至電子元件EC，電子元件EC可以電容、電感、可變電容或二極體等取代發光二極體晶片。透過改變施加至可變電容的電壓，可使電磁波的相位(phase)和振幅(amplitude)發生相應的變化，進而控制電磁波的方向或提升天線裝置的指向性。
底部填充件UF設置在電子元件EC與鈍化層PL1之間。底部填充件UF可用以加強電子元件EC的固定、提升可靠性、吸收外部光線、降低反射或保護下方的驅動元件11或電路。舉例來說，底部填充件UF的材料可包括矽膠或環氧樹脂材料，但不以此為限。
保護層PT形成在電子元件EC上。舉例來說，保護層PT可設置在鈍化層PL1上且覆蓋底部填充件UF以及導電材料CM。保護層PT可用以保護下方的元件或提升可靠性。舉例來說，保護層PT的材料可包括矽膠或環氧樹脂材料，但不以此為限。
在本實施例中，透過形成厚的導電圖案12，例如0.5μm≦厚度T12≦15μm，導電圖案12除了可用於傳遞訊號或遮罩電磁波之外，還可用於散熱。例如，導電圖案12可利用熱傳導的方式將電子元件EC工作所產生的熱排出。此外，多個導電圖案12(圖案化的導電層M1)還有助於增加散熱面積或使熱分佈均勻化。另外，透過將需要高溫製程的驅動元件11以及導電圖案12分別形成在第一基板SUB1以及第二基板SUB2上，再透過黏合層GL將第一基板SUB1以及第二基板SUB2結合，有助於改善高溫製程造成的翹曲問題。再者，透過第一基板SUB1以及黏合層GL將驅動元件11以及導電圖案12間隔開，有助於降低驅動元件11與導電圖案12之間的電阻電容負載。
應理解，依據不同的需求，電子裝置1可包括更多或更少的膜層，例如更多或更少的介電層、更多或更少的導電層。或者，電子裝置1可省略上述的某些膜層。舉例來說，電子裝置1可省略底部填充件UF，以簡化製程，但不以此為限。替代地，電子裝置1可省略保護層PT。
在一些實施例中，電子裝置1的製造方法可包括在第一基板SUB1上依序形成介電層DL1、導電層M2、介電層DL2、半導體層(未繪示)、導電層M3、介電層DL3、導電層M4、介電層DL4、鈍化層PL1以及多個接墊P1。接著，切割第一基板SUB1(可省略)以及將第一基板SUB1薄化(可省略)。然後，將多個電子元件EC透過多個導電凸塊BP接合在多個接墊P1上，再形成底部填充件UF。在第二基板SUB2上依序形成介電層DL5、導電層M1、介電層DL6以及多個接墊P2(僅繪示出一個)。接著，切割第二基板SUB2(可省略)以及將第二基板SUB2薄化(可省略)。然後，透過黏合層GL將第一基板SUB1以及第二基板SUB2結合。接著，透過鑽孔製程形成貫孔TH，並在貫孔TH中形成導電材料CM。然後，形成保護層PT。在其他實施例中，第一基板和第二基板可以先黏合再一起切割。
在一些實施例中，如圖2及圖3所示，電子裝置還可包括驅動電路DK，驅動電路DK可在形成保護層PT之後與基板結構10接合，但不以此為限。
在一些實施例中，驅動電路DK可接合在基板結構10(例如第一基板SUB1)上且可透過上述導電層(如導電層M1、導電層M2、導電層M3以及導電層M4)中的至少一層或其他導電層(如導電層M5)而電性連接於電子元件EC(繪示於圖1)。驅動電路DK可包括積體電路晶片、薄膜電晶體晶片、軟性印刷電路(FPC)、印刷電路板(PCB)、COB(chip on board)或COF(chip on film)，但不以此為限。其中，薄膜電晶體晶片可為薄膜電晶體電路形成於一基材上，再裁切為晶片尺寸。此基材可為玻璃、高分子薄膜、多孔隙薄膜等等。
以圖2為例，驅動電路DK可透過導電凸塊BP而與形成在第一基板SUB1上的多個導電圖案CP’電性連接。多個導電圖案CP’例如屬於導電層M5，但不以此為限。導電層M5的材料可包括金屬氧化物，如氧化銦錫(ITO)，但不以此為限。多個導電圖案CP’中的一個導電圖案CP’例如透過導電層M3中的電路CK4而電性連接於電子元件EC，且多個導電圖案CP’中的另一個導電圖案CP’可透過導電層M2中的電路CK3而電性連接於其他元件。
圖3與圖2類似，差異在於圖3中導電凸塊BP進一步透過多個接墊P1而與多個導電圖案CP’電性連接。
出於說明目的，圖2及圖3省略繪示出電子裝置的其餘元件及膜層。應理解，驅動電路DK與基板結構10的接合方式(例如驅動電路DK所接合的基板或所接合的元件/層別)或驅動電路DK與電子元件EC之間的連接電路的層別可依據需求改變，而不以圖2及圖3所顯示的為限。此外，下述實施例的電子裝置皆可進一步包括驅動電路DK及/或其他的主動或被動元件。驅動電路DK、其他的主動或被動元件可透過焊錫、異方性導電膜、金屬鍵合、超音波鍵合、銅膏(包括奈米銅)、銀膏(包括奈米銀)或銅柱等方式而與基板結構10接合，以下便不再重述。
請參照圖4，電子裝置1A與圖1的電子裝置1的主要差異說明如後。在電子裝置1A中，增加了電子元件EC與導電層M1之間連接的數量，以進一步提升散熱效果。舉例來說，在電子元件EC及與其電性連接的驅動元件11之間可形成有貫孔TH，且貫孔TH中可形成有導電材料CM。導電層M3可進一步包括電路CK3，且電路CK3位於導電材料CM與電子元件EC之間。電子元件EC例如透過導電凸塊BP、接墊P1、導電圖案CP、電路CK3、導電材料CM、接墊P2以及導電圖案12而電性連接於驅動元件11。
請參照圖5，電子裝置1B與圖1的電子裝置1的主要差異說明如後。在電子裝置1B中，電子元件EC是耦接於導電圖案12。也就是說，電子元件EC與導電圖案12之間未以任何導體互相連接。如圖5所示，電子裝置1B可省略貫孔TH以及導電材料CM，而有助於簡化製程、縮減製程時間、降低製程成本或使電子裝置1D更為輕薄。導電層M3可進一步包括電路CK4，且相鄰兩個電子元件EC可透過電路CK4而電性連接。
請參照圖6，電子裝置1C與圖5的電子裝置1B的主要差異說明如後。在電子裝置1C中，介電層DL5、導電層M1以及介電層DL6是設置在第二基板SUB2的第二側S2上，以提升散熱效果或遮罩電磁波的效果。
請參照圖7，電子裝置1D與圖5的電子裝置1B的主要差異說明如後。在電子裝置1D中，基板結構10D由一個基板組成，即一第一基板SUB1。介電層DL5以及導電層M1依序設置在第一基板SUB1上。介電層DL1設置在介電層DL5上且覆蓋導電層M1。導電層M2、介電層DL2、半導體層(未繪示)、導電層M3、介電層DL3以及鈍化層PL1依序設置在介電層DL1上。電子裝置1D包括多個貫孔TH1以及多個貫孔TH2。貫孔TH1貫穿介電層DL1以及介電層DL2且曝露出對應的導電圖案12。導電層M3中的汲極DE還設置在貫孔TH1中並透過貫孔TH1而電性連接於對應的導電圖案12。貫孔TH2貫穿介電層DL1、介電層DL2以及介電層DL3且與對應的開口A3在方向Z上至少部分重疊。接墊P1設置在開口A3以及對應的貫孔TH2中並透過開口A3以及貫孔TH2而電性連接於對應的導電圖案12。導電凸塊BP設置在開口A3中並透過開口A3而電性連接於對應的接墊P1。
電子元件EC可透過導電凸塊BP、接墊P1以及導電圖案12而電性連接於驅動元件11，且電子元件EC可透過導電凸塊BP、接墊P1以及導電圖案12而電性連接於相鄰的電子元件EC。
在本實施例中，透過減少所需的層別(如基板、導電層或介電層等的數量)，有助於簡化製程、縮減製程時間、降低製程成本或使電子裝置1D更為輕薄。
在一些實施例中，電子裝置1D的製造方法可包括在第一基板SUB1上依序形成介電層DL5、導電層M1、介電層DL1、導電層M2、介電層DL2、半導體層(未繪示)、導電層M3、介電層DL3、鈍化層PL1以及多個接墊P1。接著，切割第一基板SUB1(可省略)以及將第一基板SUB1薄化(可省略)。然後，將多個電子元件EC透過多個導電凸塊BP接合在多個接墊P1上，再形成底部填充件UF。然後，形成保護層PT。在一些實施例中，電子裝置1D也可包括如圖2及圖3所示的驅動電路DK，驅動電路DK可在形成保護層PT之後與基板結構10D接合，但不以此為限。
請參照圖8，電子裝置1E與圖5的電子裝置1B的主要差異說明如後。在電子裝置1E中，基板結構10D由一個基板組成，即一第一基板SUB1。介電層DL5以及導電層M1依序設置在第一基板SUB1上。介電層DL1設置在介電層DL5上且覆蓋導電層M1。介電層DL1上的膜層的相關描述請參照圖5的相關描述，於此不再重述。
在本實施例中，透過減少所需的層別(如基板、導電層或介電層等的數量)，有助於簡化製程、縮減製程時間、降低製程成本或使電子裝置1E更為輕薄。另外，在設置有介電層DL4以及導電層M4的架構下，可依需求增加導電層M1與導電層M2之間的距離、導電層M1與導電層M3之間的距離或導電層M1與導電層M4之間的距離，以降低電阻電容負載。
請參照圖9，電子裝置1F與圖8的電子裝置1E的主要差異說明如後。在電子裝置1F中，導電層M3中的電路CK4透過貫穿介電層DL1以及介電層DL2的貫孔TH1而連接導電圖案12，以進一步提升散熱效果。
請參照圖10，電子裝置1G與圖1的電子裝置1的主要差異說明如後。在電子裝置1G中，基板結構10D由一個基板組成，即一第一基板SUB1。介電層DL5、導電層M1以及介電層DL6依序設置在第一基板SUB1之遠離驅動元件11的表面上。此外，電子裝置1G還包括鈍化層PL2。鈍化層PL2設置在介電層DL6上。鈍化層PL2可用以保護介電層DL6。舉例來說，鈍化層PL1的材料可包括矽膠或環氧樹脂材料，但不以此為限。接墊P2設置在貫穿接墊P1、介電層DL3、介電層DL2、介電層DL1以及第一基板SUB1的貫孔TH’以及介電層DL5的開口A4中且與對應的導電圖案12電性連接。導電材料CM形成在貫孔TH’中。
在本實施例中，透過減少所需的層別(如第二基板SUB2以及黏合層GL)，有助於降低製程成本或使電子裝置1D更為輕薄。此外，透過將導電層M1設置在第一基板SUB1之遠離驅動元件11的表面上，有助於降低電阻電容負載。
請參照圖11，電子裝置1H與圖1的電子裝置1的主要差異說明如後。電子裝置1H還包括第三基板SUB3以及密封件SL，且電子裝置1H可不包括保護層PT。第三基板SUB3可包括聚合物薄膜、多孔薄膜(porous film)、玻璃、印刷電路板或由陶瓷形成的基層，但不以此為限。第三基板SUB3覆蓋多個電子元件EC，且第三基板SUB3可透過密封件SL固定在基板結構10上。例如，第三基板SUB3可透過密封件SL固定在鈍化層PL1上，且第三基板SUB3與鈍化層PL1在方向Z上的距離D可透過底部填充件UF來控制。底部填充件UF可選擇軟性材料，例如矽膠、間隙物(spacer)、膠水或聚合物，但不以此為限。間隙物可包括光阻間隙物(photo spacer)、球狀間隙物(ball spacer)或黏性球狀間隙物(adhesive ball spacer)，但不以此為限。
在一些實施例中，第三基板SUB3與鈍化層PL1之間的間隙空間GS可填充空氣、惰性氣體、膠水、穩定液體或聚合物，但不以此為限。替代地，三基板SUB3與鈍化層PL1之間的間隙空間GS可為真空的。
綜上所述，在本揭露的實施例中，可透過形成導電圖案，來散熱、增加散熱面積或使熱分佈均勻化。在一些實施例中，可透過將驅動元件以及導電圖案分別形成在不同的基板上，再透過黏合層將兩個基板結合，有助於改善高溫製程造成的翹曲問題。此外，透過將驅動元件以及導電圖案間隔開，有助於降低驅動元件與導電圖案之間的電阻電容負載。
以上各實施例僅用以說明本揭露的技術方案，而非對其限制；儘管參照前述各實施例對本揭露進行了詳細的說明，本領域具有通常知識者應當理解：其依然可以對前述各實施例所記載的技術方案進行修改，或者對其中部分或者全部技術特徵進行等同替換；而這些修改或者替換，並不使相應技術方案的本質脫離本揭露各實施例技術方案的範圍。
雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾，且各實施例間的特徵可任意互相混合替換而成其他新實施例。此外，本揭露之保護範圍並未局限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露使用。因此，本揭露的保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一請求項構成個別的實施例，且本揭露之保護範圍也包括各個請求項及實施例的組合。本揭露之保護範圍當視隨附之申請專利範圍所界定者為准。
1、1A、1B、1C、1D、1E、1F、1G、1H:電子裝置 10、10D:基板結構 11:驅動元件 12、CP、CP’:導電圖案 A1、A2、A3、A4:開口 BP:導電凸塊 CK1、CK2、CK3、CK4:電路 CM:導電材料 D:距離 DE:汲極 DL1、DL2、DL3、DL4、DL5、DL6:介電層 DK:驅動電路 EC:電子元件 G:間隙 GE:閘極 GL:黏合層 GS:間隙空間 M1、M2、M3、M4、M5:導電層 P1、P2:接墊 PL1、PL2:鈍化層 PT:保護層 S1:第一側 S2:第二側 SE:源極 SUB1:第一基板 SUB2:第二基板 SUB3:第三基板 SL:密封件 T12:厚度 TH、TH’、TH1、TH2:貫孔 UF:底部填充件 Z:方向
圖1至圖11分別是根據本揭露的一些實施例的電子裝置的局部剖面示意圖。
1:電子裝置
10:基板結構
11:驅動元件
12、CP:導電圖案
A1、A2、A3、A4:開口
BP:導電凸塊
CK1、CK2:電路
CM:導電材料
DE:汲極
DL1、DL2、DL3、DL4、DL5、DL6:介電層
EC:電子元件
G:間隙
GE:閘極
GL:黏合層
M1、M2、M3、M4:導電層
P1、P2:接墊
PL1:鈍化層
PT:保護層
S1:第一側
S2:第二側
SE:源極
SUB1:第一基板
SUB2:第二基板
T12:厚度
TH:貫孔
UF:底部填充件
Z:方向

Claims (20)

  1. 一種電子裝置，包括： 基板結構； 導電圖案，形成在所述基板結構上； 驅動元件，設置在所述基板結構上且電耦合至該導電圖案；以及 電子元件，設置在所述基板結構上且電耦合至該導電圖案， 其中所述導電圖案的厚度大於或等於0.5μm且小於或等於15μm。
  2. 如請求項1所述的電子裝置，其中所述基板結構包括第一基板以及第二基板，所述驅動元件設置在所述第一基板上，所述導電圖案設置在所述第二基板上，且所述第一基板與所述第二基板結合。
  3. 如請求項2所述的電子裝置，其中所述第二基板包括面向所述第一基板的第一側以及與所述第一側相對的第二側，且所述導電圖案設置在所述第一側上。
  4. 如請求項2所述的電子裝置，其中所述第二基板包括面向所述第一基板的第一側以及與所述第一側相對的第二側，且所述導電圖案設置在所述第二側上。
  5. 如請求項2所述的電子裝置，其中所述第一基板以及所述第二基板的至少一個包括貫孔，導電材料形成在所述貫孔中，且所述驅動元件透過所述導電材料而電性連接於所述導電圖案。
  6. 如請求項5所述的電子裝置，其中所述導電材料包括錫或銅膏。
  7. 如請求項5所述的電子裝置，其中所述電子元件位於所述驅動元件以及所述貫孔之間，且所述驅動元件依序透過所述電子元件以及形成在所述貫孔中的所述導電材料而電性連接於所述導電圖案。
  8. 如請求項5所述的電子裝置，其中所述電子裝置包括多個所述電子元件，且所述貫孔設置在兩個相鄰的電子元件之間。
  9. 如請求項8所述的電子裝置，其中所述兩個相鄰的電子元件共同透過形成在所述貫孔中的所述導電材料而電性連接於所述導電圖案。
  10. 如請求項5所述的電子裝置，其中所述第一基板以及所述第二基板的所述至少一個包括多個所述貫孔，所述導電材料形成在多個所述貫孔中，其中一個貫孔設置在所述驅動元件以及所述電子元件之間，且所述電子元件透過形成在所述其中一個貫孔中的導電材料而電性連接於所述驅動元件。
  11. 如請求項10所述的電子裝置，其中所述電子元件位於兩個相鄰的貫孔之間，所述電子裝置包括多個所述導電圖案，所述電子元件透過分別位於所述兩個相鄰的貫孔中的所述導電材料電性連接於不同的導電圖案。
  12. 如請求項1所述的電子裝置，其中所述驅動元件是電晶體。
  13. 如請求項1所述的電子裝置，其中所述電子元件是直接電性連接於所述導電圖案。
  14. 如請求項1所述的電子裝置，其中所述電子元件是耦接於所述導電圖案。
  15. 如請求項1所述的電子裝置，還包括： 保護層，形成在所述電子元件上。
  16. 如請求項1所述的電子裝置，還包括： 第三基板，覆蓋電子元件；以及 密封件，所述第三基板透過所述密封件固定在所述基板結構上。
  17. 如請求項11所述的電子裝置，其中所述電子元件包括發光二極體晶片、電容、電感、可變電容、過濾器、電阻、二極體、微機電系統或液晶晶片。
  18. 如請求項11所述的電子裝置，其中所述電子元件與所述導電圖案分別位元於所述驅動元件的相對側。
  19. 如請求項11所述的電子裝置，其中所述基板結構包括第一基板，且所述導電圖案、所述驅動元件以及所述電子元件依序設置在所述第一基板上。
  20. 如請求項19所述的電子裝置，其中所述電子裝置包括多個所述導電圖案，所述電子元件電性連接於兩個相鄰的導電圖案，且所述電子元件透過所述兩個相鄰的導電圖案中的一個與所述驅動元件電性連接。
TW111110751A 2021-05-11 2022-03-23 電子裝置 TW202245212A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163186808P 2021-05-11 2021-05-11
US63/186,808 2021-05-11
CN202210036440.7 2022-01-13
CN202210036440.7A CN115332237A (zh) 2021-05-11 2022-01-13 电子装置

Publications (1)

Publication Number Publication Date
TW202245212A true TW202245212A (zh) 2022-11-16

Family

ID=82100293

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111110751A TW202245212A (zh) 2021-05-11 2022-03-23 電子裝置

Country Status (3)

Country Link
US (1) US20220367370A1 (zh)
EP (1) EP4099385A3 (zh)
TW (1) TW202245212A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114023781B (zh) * 2021-10-08 2023-06-16 业成科技（成都）有限公司 曲面电子装置及其制造方法
TWI831116B (zh) * 2022-01-17 2024-02-01 欣興電子股份有限公司 封裝結構及其製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100546431C (zh) * 2004-11-11 2009-09-30 夏普株式会社 柔性布线基板及其制造方法、半导体装置和电子设备
JP5178650B2 (ja) * 2009-07-06 2013-04-10 株式会社日立製作所 光電気複合配線モジュールおよびその製造方法
US9159700B2 (en) * 2012-12-10 2015-10-13 LuxVue Technology Corporation Active matrix emissive micro LED display
US10170457B2 (en) * 2016-12-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and method of forming the same
TWI810380B (zh) * 2019-02-22 2023-08-01 南韓商愛思開海力士有限公司 包括橋接晶粒的系統級封裝件
US11978685B2 (en) * 2019-07-25 2024-05-07 Intel Corporation Glass core patch with in situ fabricated fan-out layer to enable die tiling applications
KR20210132786A (ko) * 2020-04-27 2021-11-05 삼성디스플레이 주식회사 화소 및 이를 구비한 표시 장치

Also Published As

Publication number Publication date
EP4099385A2 (en) 2022-12-07
US20220367370A1 (en) 2022-11-17
EP4099385A3 (en) 2023-03-15

Similar Documents

Publication Publication Date Title
TW202245212A (zh) 電子裝置
US11100351B2 (en) Fingerprint recognition module and electronic device comprising same
US20150085527A1 (en) Light source module, fabrication method therefor, and backlight unit including the same
CN111312742B (zh) 背光模组及其制备方法、显示装置
TWI671572B (zh) 顯示面板及其製造方法
CN112366220B (zh) 一种显示基板及其制备方法、显示装置
JP2009027166A (ja) 化合物半導体デバイスのパッケージ封入構造及びその作成方法
TWI671571B (zh) 用於背光模組的封裝結構
CN109712932B (zh) 可挠式阵列基板及其制造方法
US20190319080A1 (en) Display apparatus and manufacturing method thereof
CN113540180A (zh) 显示装置
KR20220165719A (ko) 구동 기판, 구동 기판의 제작 방법 및 표시 장치
KR20190122150A (ko) 전자 장치
TW202004710A (zh) 顯示裝置及其製造方法
TW202240713A (zh) 電子裝置的製作方法
CN115332237A (zh) 电子装置
TWI840996B (zh) 電子裝置及其製造方法
JP2023533880A (ja) 駆動基板及びその製作方法、表示装置
TWI804110B (zh) 電子裝置及其製造方法
US11830833B2 (en) Electronic substrate and electronic device
CN114649215A (zh) 电子装置的制作方法
US20240128184A1 (en) Electronic device and manufacturing method thereof
TW202416775A (zh) 電子裝置及其製造方法
US20240155777A1 (en) Electronic device
US20230352595A1 (en) Electronic device and manufacturing method of electronic device