CN108269767A - 衬底晶片上芯片结构的形成方法 - Google Patents

衬底晶片上芯片结构的形成方法 Download PDF

Info

Publication number
CN108269767A
CN108269767A CN201710377159.9A CN201710377159A CN108269767A CN 108269767 A CN108269767 A CN 108269767A CN 201710377159 A CN201710377159 A CN 201710377159A CN 108269767 A CN108269767 A CN 108269767A
Authority
CN
China
Prior art keywords
substrate
tube core
connector
die
encapsulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710377159.9A
Other languages
English (en)
Inventor
陈伟铭
吴集锡
丁国强
侯上勇
俞笃豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108269767A publication Critical patent/CN108269767A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4817—Conductive parts for containers, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/11452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32106—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1437—Static random-access memory [SRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

提供一种衬底晶片上芯片结构的形成方法。所述方法包括将第一管芯及第二管芯贴合至介插器。所述方法还包括将第一衬底贴合至所述第一管芯的第一表面及所述第二管芯的第一表面。所述第一衬底包含硅。所述第一管芯的所述第一表面与所述第一管芯的贴合至所述介插器的表面相对，且所述第二管芯的所述第一表面与所述第二管芯的贴合至所述介插器的表面相对。所述方法包括将所述介插器结合至第二衬底。

Description

衬底晶片上芯片结构的形成方法
技术领域
本发明实施例涉及一种衬底晶片上芯片结构及其形成方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速增长。在很大程度上，集成密度的此种提高来自于最小特征大小(minimum feature size)的重复减小(例如，使半导体工艺节点朝亚20纳米节点(sub-20nm node)缩减)，此使得更多组件能够集成到给定区域中。近来，随着对微型化、较高速度、及较大频宽、以及较低功耗及延时的需求的增长，需要更小且更具创造性的半导体管芯封装技术。
随着半导体技术的进一步发展，已出现作为用以进一步减小半导体装置的实体大小的有效替代方式的堆叠半导体装置(例如，三维集成电路(three dimensionalintegrated circuit，3DIC))。在堆叠半导体装置中，例如逻辑电路、存储器电路、处理器电路等有源电路被制作于不同的半导体晶片上。两个或更多个半导体晶片可在彼此顶上进行安装或堆叠，以进一步减小半导体装置的形状因数(form factor)。
发明内容
本发明实施例的一种衬底晶片上芯片结构的形成方法，包括：将第一管芯及第二管芯贴合至介插器；将第一衬底贴合至所述第一管芯的第一表面及所述第二管芯的第一表面，所述第一衬底包含硅，所述第一管芯的所述第一表面与所述第一管芯的贴合至所述介插器的表面相对，且所述第二管芯的所述第一表面与所述第二管芯的贴合至所述介插器的表面相对；以及将所述介插器结合至第二衬底。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1至图5A、及图5B至图15是形成根据某些实施例的半导体封装的过程中的各中间阶段的剖视图；以及
图16A及图16B是根据某些实施例的半导体封装结构的剖视图。
具体实施方式
以下公开内容提供用于实作本发明的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
根据某些实施例，提供衬底晶片上芯片(chip on wafer on substrate，COWOS)封装100。在制造期间，衬底可贴合至被封装于COWOS结构中的管芯的背侧。在制造期间，衬底可保护管芯，且可减轻封装翘曲(package warpage)。这样一来，封装的可靠性可提高。在制造期间，衬底可用于对封装进行实体支撑，由此减轻对单独的载体及载体剥离工艺(carrier debond process)的需要，此可有助于降低成本。
图1至图16B是根据某些实施例的COWOS封装的制造过程的各中间阶段的剖视图。参照图1，在载体102上放置衬底104。通常，在后续加工步骤期间，载体102对各种特征(例如，衬底104)提供暂时的机械性及结构性支撑。通过这种方式，对装置管芯的损坏会减少或得到防止。载体102可包括例如玻璃、陶瓷等。在某些实施例中，载体102可实质上不具有任何有源装置及/或功能性电路系统。在某些实施例中，使用释放层103将衬底104贴合至载体102。释放层103可为任何适合的粘合剂，例如紫外光(ultraviolet，UV)胶等。
衬底104可由例如硅、锗、金刚石等半导体材料制成。在某些实施例中，也可使用例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些的组合等化合物材料。衬底104可为介插器(interposer)。另外，衬底104可为绝缘体上半导体(semiconductor-on-insulator，SOI)衬底。通常，SOI衬底包括由例如外延硅、锗、硅锗、SOI、绝缘体上硅锗(silicon germanium on insulator，SGOI)或其组合等半导体材料形成的层。可在衬底104的表面中及/或衬底104的所述表面上形成例如晶体管、电容器、电阻器、二极管等装置。在一个替代性实施例中，衬底104是基于例如玻璃纤维加强型树脂芯(fiberglass reinforced resin core)等绝缘芯。一种示例性芯材料为例如FR4等玻璃纤维树脂。所述芯材料的各种替代形式包括双马来酰亚胺三嗪(bismaleimide-triazine，BT)树脂，或者作为另外一种选择，包括其他印刷电路板(printed circuit board，PCB)材料或膜。可对衬底104使用例如味之素增层膜(Ajinomoto build-up film，ABF)等增层膜或其他层压体(laminate)。
在图2中，可在衬底104中形成开口106。在后续加工中，可在每一开口106中形成穿孔(through via)(参见例如图3)。穿孔可提供从衬底104的一侧至衬底104的相对一侧的电连接。如图2中所示，开口106可不穿透过衬底104。当开口106不穿透过衬底104时，在后续加工中，可在衬底104上执行薄化步骤(thinning step)以薄化衬底104并使穿孔穿过衬底104被暴露出(参见图10)。在其他实施例中，开口106可穿透过衬底104且不需要薄化步骤。
可以任何可接受方式形成开口106。在某些实施例中，将光刻胶(图中未示出)形成并图案化于衬底104上。可通过旋转涂布(spin coating)等来形成光刻胶并可将所述光刻胶暴露至光以进行图案化。光刻胶的图案对应于开口106的图案。所述图案化形成穿过光刻胶的开口以暴露出衬底104。可执行穿过光刻胶的蚀刻工艺(etch process)以形成开口106。可使用例如湿蚀刻(wet etching)或干蚀刻(dry etching)等任何可接受蚀刻方式。在某些实施例中，所述蚀刻可为各向异性的。在完成蚀刻之后，可例如使用氧等离子体等、通过可接受的灰化工艺(ashing process)或剥除工艺(stripping process)来移除光刻胶。所得结构绘示于图2中。
参照图3，以导电材料填充开口106，以形成穿孔110。在某些实施例中，可使用例如电镀(electroplating)、无电镀覆(electroless plating)等镀覆工艺(platingprocess)、以导电材料填充开口106。导电材料可包括金属，如铜、钛、钨、铝等。在以导电材料填充开口106以形成穿孔110之后，过量的导电材料可能外溢于开口106外并沿衬底104的上表面延伸(图3中未示出)。可执行平坦化工艺(planarization process)(例如，研磨工艺(grinding process)等)以移除导电材料的过量部分并使穿孔110的上表面与衬底104的表面实质上共面。所得结构绘示于图3中。
参照图4，在衬底104之上形成一层或多层重布线层(redistribution layer，RDL)112。通常，RDL 112提供导电图案，所述导电图案使得完成封装(completed package)能够具有与管芯118及120上随后将贴合至连接件115的连接件118C及120C的图案(参见图5A)不同的引脚输出触点图案(pin-out contact pattern)。RDL 112包括导电线114及通孔116，其中通孔116将上覆线(例如，上覆导电线114)连接至下伏导电特征(例如，穿孔110及/或导电线114)。导电线114可根据特定设计沿任何方向延伸。
可使用任何适合的工艺来形成RDL 112。举例来说，在某些实施例中，在衬底104上形成第一介电层。在某些实施例中，第一介电层是由可使用光刻(lithography)来图案化的聚合物形成，所述聚合物可为例如聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺、苯并环丁烯(benzocyclobutene，BCB)等感光性材料。在其他实施例中，第一介电层是由氮化物(例如，氮化硅)、氧化物(例如，氧化硅)、磷硅酸盐玻璃(PhosphoSilicate Glass，PSG)、硼硅酸盐玻璃(BoroSilicate Glass，BSG)、掺杂硼的磷硅酸盐玻璃(Boron-dopedPhosphoSilicate Glass，BPSG)等形成。可通过旋转涂布、层压(lamination)、化学气相沉积(chemical vapor deposition，CVD)等或其组合来形成第一介电层。接着将第一介电层图案化以形成暴露出穿孔110的开口。在其中第一介电层是由感光性材料形成的实施例中，可通过根据所需图案将第一介电层曝光并进行显影以移除非期望材料来执行所述图案化，由此暴露出穿孔110。也可使用其他方法(例如使用图案化掩模及蚀刻)将第一介电层图案化。
在第一介电层之上且在形成于所述第一介电层中的开口中形成晶种层(图中未示出)。在某些实施例中，晶种层为金属层，所述金属层可为单一层或包括由不同材料形成的多个子层的复合层。在某些实施例中，晶种层包括钛层及位于所述钛层之上的铜层。可使用例如物理气相沉积(physical vapor deposition，PVD)等来形成晶种层。接着根据所需重布线图案将掩模(图中未示出)形成并图案化于所述晶种层上。在某些实施例中，所述掩模是通过旋转涂布等形成并被暴露至光以进行图案化的光刻胶。所述图案化穿过掩模形成暴露出晶种层的开口。在掩模的开口中且在晶种层的暴露的部分上形成导电材料。可使用例如电镀、无电镀覆等镀覆工艺来形成所述导电材料。导电材料可包括金属，如铜、钛、钨、铝等。接着，移除光刻胶以及晶种层的上面未形成有导电材料的部分。可例如使用氧等离子体等、通过可接受的灰化工艺或剥除工艺来移除光刻胶。一旦光刻胶被移除，则例如使用可接受的蚀刻工艺(例如通过湿蚀刻或干蚀刻)移除晶种层的被暴露的部分。晶种层的其余部分与导电材料形成导电线114及通孔116。接着在第一介电层之上形成第二介电层以为后续的层提供更平的表面，且可使用与用于形成第一介电层的材料及工艺相似的材料及工艺来形成所述第二介电层。在某些实施例中，第二介电层是由聚合物、氮化物、氧化物等形成。在某些实施例中，第二介电层是通过旋转涂布工艺形成的PBO。如有必要，则可重复进行以上工艺以形成特定设计所可能需要的数目的RDL层。
根据某些实施例，在RDL 112之上形成连接件115。尽管在图4中被绘示成凸块，然而连接件115也可为焊料球、金属柱、受控塌陷芯片连接(controlled collapse chipconnection，C4)凸块、微凸块(micro bump)、由无电镀镍钯浸金技术(electrolessnickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸块、其组合(例如，贴合有焊料球的金属柱)等。连接件115可包含导电材料，例如焊料、铜、铝、金、镍、银、钯、锡等或其组合。在某些实施例中，连接件115包含共晶材料(eutectic material)且可包括例如焊料凸块或焊料球。焊料材料可为例如：铅系焊料(lead-based solder)或无铅焊料(lead-free solder)，例如铅系焊料的Pb-Sn成分；包含InSb的无铅焊料；锡、银、及铜(SAC)成分；以及具有共同的熔点并在电器中形成导电焊料连接的其他共晶材料。对于无铅焊料，可使用由例如(举例而言，SAC 105(Sn98.5％、Ag1.0％、Cu0.5％)、SAC 305、及SAC405)等不同成分形成的SAC焊料。例如焊料球等无铅连接件还可由SnCu化合物形成，而不使用银(Ag)。作为另外一种选择，无铅焊料连接件可包含锡及银、Sn-Ag，而不使用铜。连接件115可形成栅(grid)，例如球栅阵列封装(ball grid array，BGA)。在某些实施例中，可执行回焊工艺(reflow process)，以使连接件115的形状在某些实施例中为不完整球体(partial sphere)。作为另外一种选择，连接件115可包括其他形状。
连接件115还可包括例如非球形导电连接件。在某些实施例中，连接件115包括通过溅镀(sputtering)、印刷、电镀、无电镀覆、CVD等形成的金属柱(例如，铜柱)，所述金属柱上具有焊料材料或不具有焊料材料。金属柱可不含焊料且具有实质上垂直的侧壁或锥形的侧壁。
连接件115还可包括根据某些实施例形成并图案化于最上侧金属化图案之上的凸块下金属(under bump metallization，UBM)，由此形成与最上侧金属化层的电连接。UBM提供可在上面放置电连接件(例如，焊料球/凸块、导电柱等)的电连接(electricalconnection)。在实施例中，UBM包括扩散障壁层(diffusion barrier layer)、晶种层、或其组合。扩散障壁层可包含Ti、TiN、Ta、TaN、或其组合。晶种层可包含铜或铜合金。然而，也可包含其他金属，例如镍、钯、银、金、铝、其组合、及其多层形式。在实施例中，使用溅镀形成UBM。在其他实施例中，可使用电镀。
参照图5A，将管芯118及120结合至连接件115。根据某些示例性实施例，管芯118为逻辑管芯，例如中央处理器(Central Processing Unit，CPU)、应用处理器(Applicationprocessor，AP)、系统芯片(system on chip，SOC)、应用专用集成电路(ApplicationSpecific Integrated Circuit，ASIC)、或其中包括逻辑晶体管的其他类型的逻辑管芯。尽管示出三个管芯118，然而可将更少或更多的管芯118结合至连接件115。管芯118可具有相同结构及/或相同功能，或可具有不同结构及功能。
根据某些实施例，各管芯118可分别包括主体(main body)118A、内连线区118B、及连接件118C。主体118A可包括任何数目的管芯、衬底、晶体管、有源装置、无源装置等。内连线区118B可提供导电图案，所述导电图案使得主体118A能够具有与连接件118C的图案不同的引脚输出触点图案，从而使得能够更灵活地放置连接件118C。可将连接件118C放置于管芯118的底侧上，且可使用连接件118C将管芯118实体地连接至且电连接至连接件115。可通过内连线区118B将连接件118C电连接至主体118A。可使用与以上结合连接件115所述的方法相同或相似的方法来形成连接件118C。
根据某些示例性实施例的管芯120包括存储器管芯。举例来说，管芯120可为动态随机存取存储器(Dynamic Random Access Memory，DRAM)管芯、静态随机存取存储器(Static Random Access Memory，SRAM)管芯、高频宽存储器(High-Bandwidth Memory，HBM)管芯、微机电系统(Micro-Electro-Mechanical System，MEMS)管芯、混合存储数据集(Hybrid Memory Cube，HMC)管芯等。尽管示出三个管芯120，然而可结合更少或更多的管芯120。各管芯120可具有相同的结构及/或功能，或可具有不同的结构及功能。根据某些实施例，管芯120可包括主体120A、内连线区120B、及连接件120C。
在图5B中更详细地绘示了根据某些实施例的示例性管芯120。主体120A可包括多个堆叠存储器管芯120D。堆叠存储器管芯120D可均为相同的管芯，或者存储器管芯120可包括不同类型及/或结构的管芯。可通过连接件120E将存储器管芯120D连接至上覆管芯120D及/或下伏存储器管芯120D。在某些实施例中，主体120A可包括高频宽存储器(HBM)模块及/或混合存储数据集(HMC)模块，所述模块可包括与逻辑管芯120G连接的一个或多个存储器管芯120D。逻辑管芯120G可包括将内连线区120B的导电特征连接至上覆连接件120E的穿孔(图中未示出)。如由图5B所示，可将主体120A包封于模制材料120F中。模制材料120F可包括模制化合物(molding compound)、模制底部填充物(molding underfill)、环氧树脂(epoxy)、或树脂。
内连线区120B位于主体120A之下。内连线区120B可提供导电图案，所述导电图案使得主体120A能够具有与连接件120C的图案不同的引脚输出触点图案，从而使得能够更灵活地放置连接件120C。可将连接件120C放置于管芯120的底侧上，且可使用连接件120C将管芯120实体地连接至且电连接至连接件115。可通过内连线区120B将连接件120C电连接至逻辑管芯120G及/或堆叠存储器管芯120D。可使用与以上结合连接件115所述的方法相同或相似的方法来形成连接件120C。
图5A绘示其中管芯118与管芯120在平面图中相互交错的实施例。在某些实施例中，可使用管芯118及120的不同排列。举例来说，在某些实施例中，管芯118可在管芯118的任一侧上包括管芯120。
可使用任何适合的方法将管芯118及120结合至连接件115。根据某些实施例，可通过将连接件118C及120C结合至连接件115而将管芯118及120分别结合至连接件115。
参照图6，可在管芯118/120与RDL 112之间形成底部填充物123，且底部填充物123可环绕连接件115、118C、及/或120C。在贴合管芯118及120之后，可通过毛细流动工艺(capillary flow process)来形成底部填充物123，或者在贴合管芯118及120之前，可通过适合的沉积方法来形成底部填充物123。
接下来，将管芯118及120包封于模制材料122中。模制材料122填充管芯118与管芯120之间的间隙，且可接触连接件115、连接件118C、连接件120C、及/或RDL 112。模制材料122可包括模制化合物、模制底部填充物、环氧树脂、或树脂。模制材料122可为与管芯120的模制材料120F相同的材料，或可为不同材料。在形成之后，模制材料122的顶表面可高于管芯118及120的顶表面。
接下来，执行研磨步骤以薄化模制材料122，直至暴露出管芯118及120的顶表面。所得结构示出于图7中。
参照图8，将衬底126贴合至穿过模制材料122被暴露出的管芯118及120的表面。可使用粘合层124来贴合衬底126。在某些实施例中，粘合层124可包括管芯贴合膜(dieattach film，DAF)。
在后续加工期间，衬底126可为封装100提供结构性支撑。举例来说，如上所述，管芯118的顶表面及管芯120的顶表面穿过模制材料122被暴露出，此可能在封装100上造成外应力(extrinsic stress)且可能在加工期间(例如在测试或机上加工(on-boardprocessing)期间)对封装100的顶表面造成损坏。在后续加工期间，衬底126可有助于减轻对封装100的顶表面的损坏。在后续加工期间，衬底126也可有助于减轻封装100的翘曲，由此提高封装100的可靠性。此外，如以下将阐述，在后续加工中将翻转封装100，且在封装100的附加加工期间，衬底126可为封装100提供实体支撑。衬底126的存在可消除对单独的载体(例如，玻璃衬底)及剥离工艺的需要，此可有助于降低制造成本。
在某些示例性实施例中，衬底126可由硅形成。举例来说，衬底126可由实质上纯的硅形成。在其他实施例中，衬底126可包含提供刚性(rigidity)及/或热传导(thermalconductance)的任何适合的材料，从而使得衬底126可有助于均匀地消散来自封装100的热量并在附加加工期间为管芯118及120的顶表面提供结构支撑。在某些实施例中，衬底126可包含金属，例如Cu、Ni、或Al。在某些实施例中，衬底126可包含陶瓷材料。举例来说，在某些实施例中，衬底126可包含Al2O3。在某些实施例中，衬底126可包含聚合物材料。
参照图9，将封装100翻转，以使衬底126为底并为封装100提供实体支撑。剥离载体102，留下图9中所示结构。如图9中所绘示，在此加工阶段处，衬底104、RDL 112、及连接件115具有为约10μm至约1000μm(例如，约775μm)的组合厚度T1。管芯118及管芯120分别具有为约50μm至约1000μm(例如，760μm)的厚度T2。衬底126具有为约10μm至约1000μm(例如，约775μm)的厚度T3。衬底104具有为约10μm至约1000μm(例如，约775μm)的厚度T4。
接下来，参照图10，薄化衬底104，直至暴露出穿孔110。举例来说，可使用研磨工艺来薄化衬底104。在所述薄化之后，衬底104、RDL 112、及连接件115可具有为约5μm至约1000μm(例如，100μm)的组合厚度T5。所述薄化工艺可在顶表面上形成例如金属颗粒等金属残留物。因此，在所述薄化之后，可例如通过湿蚀刻执行清洗(cleaning)，以使金属残留物被移除。
参照图11，使用与以上结合连接件115所述的方法相同或相似的方法在衬底104上形成连接件129。在图11中绘示的实施例中，每一连接件129包括通过溅镀、印刷、电镀、无电镀覆、CVD等形成的金属柱128(例如，铜柱)。每一金属柱128具有在与和衬底104接触的表面相对的表面上形成的焊料130。金属柱128可具有实质上垂直的侧壁(例如，图11中绘示的实施例)，或在其他实施例中可具有锥形的侧壁。
接下来，如图12中所示，在衬底104之上施加保护膜132。保护膜132沿连接件129的侧壁延伸且具有足以完全覆盖连接件129的厚度。保护膜132可为胶带(例如，背侧研磨(backgrinding，BG)胶带(紫外光胶带(UV tape)或非紫外光胶带(non-UV tape)))，所述胶带可用于在后续平坦化工艺期间(参见图13至图14)保护衬底104的表面及连接件129的表面不被研磨碎屑损坏。可使用例如滚筒(roller)(图中未示出)来施加保护膜132。
参照图13，再次将封装100翻转，以使保护膜132为底并为封装100提供实体支撑。在所述翻转之后，衬底126位于封装100顶上。
接下来，参照图14，薄化衬底126。在某些实施例中，可使用研磨工艺来薄化衬底126。在所述薄化之后，衬底126可具有为约5μm至约1000μm(例如，50μm)的厚度T6。所述薄化工艺可能会在衬底126的顶表面上形成例如金属颗粒等金属残留物。因此，在所述薄化之后，可例如通过湿蚀刻执行清洗，以使金属残留物被移除。
参照图15，再次将封装100翻转，且可将衬底126贴合至暂时支撑框架134(例如，包括支撑胶带)。接下来，移除保护膜132，从而暴露出连接件129。接下来，将封装100单体化成独立的封装200。在某些实施例中，可通过锯切(sawing)等来将封装100单体化。可将封装100单体化成使得每一独立的封装200均包括管芯118及管芯120。在其他实施例中，可对每一封装200使用不同数目及/或配置的管芯118及120。
接下来，参照图16A，将封装200翻转并结合至衬底136。衬底136可由例如硅、锗、金刚石等半导体材料制成。在某些实施例中，也可使用例如硅锗、碳化硅、镓砷、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、这些的组合等化合物材料。另外，衬底136可为SOI衬底。通常，SOI衬底包括由例如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或其组合等半导体材料形成的层。在一个替代性实施例中，衬底136是基于例如玻璃纤维加强型树脂芯等绝缘芯。一种示例性芯材料为例如FR4等玻璃纤维树脂。所述芯材料的各种替代形式包括双马来酰亚胺三嗪(BT)树脂，或者作为另外一种选择，包括其他印刷电路板(PCB)材料或膜。可对衬底136使用例如味之素增层膜(ABF)等增层膜或其他层压体。
衬底136可包括有源装置及无源装置(图16B中未示出)。所属领域中的普通技术人员应认识到，可使用例如晶体管、电容器、电阻器、这些的组合等众多各种各样的装置来产生对半导体封装设计的结构性要求及功能性要求。可使用任何适合的方法来形成所述装置。
衬底136还可包括金属化层及通孔(图中未示出)以及与所述金属化层及通孔连接的结合垫142。可将金属化层形成于有源装置及无源装置之上并设计成连接各种装置以形成功能性电路系统。金属化层可由交替的介电质(例如，低介电常数介电材料(low-kdielectric material))层与导电材料(例如，铜)层形成且可使用任何适合的工艺(例如，沉积、镶嵌(damascene)、双镶嵌(dual damascene)等)来形成所述金属化层，其中通孔对各所述导电材料层进行内连。在某些实施例中，衬底136实质上不具有有源装置及无源装置。
衬底136可在衬底136的底表面上包括连接件146。可使用连接件146将衬底136实体地连接至且电连接至其他装置、封装、组件等。另外，可将一或多个表面装置144连接至衬底136。可使用表面装置144为封装200或整个封装提供附加功能性或编程。在实施例中，表面装置144可包括表面安装装置(surface mount device，SMD)或包括例如电阻器、电感器、电容器、跨接线(jumper)、这些的组合等无源装置的集成无源装置(integrated passivedevice，IPD)，所述无源装置需要连接至封装200或所述封装的其他部分并与其结合使用。可根据特定方式将表面装置144放置于衬底136的第一主表面、衬底136的相对主表面、或第一主表面与相对主表面二者上。
可使用结合垫142将封装200结合至衬底136。可使用例如以上结合连接件115所述的方法等任何适合的方法来形成结合垫142。结合垫142可具有与衬底136齐平的顶表面。在其他实施例中，结合垫142从衬底136突出。可使用结合垫142来连接至柱128及/或焊料130，由此将封装200结合至衬底136。
在某些实施例中，可在衬底136的表面上靠近连接件129(图16A中的金属柱128及焊料130)处形成底部填充物148。在某些实施例中，底部填充物148沿柱128的侧壁且沿衬底104的底表面延伸。在某些实施例中，底部填充物148进一步沿衬底104的侧壁、RDL 112的侧壁、及/或管芯118及120的侧壁延伸。在封装200贴合至衬底136之后，可通过毛细流动工艺来形成底部填充物148，或者在封装200贴合至衬底136之前，可通过适合的沉积方法来形成底部填充物148。
接下来，对衬底126的顶表面施加热界面材料140。热界面材料140可有助于将来自封装200的热量消散至后续施加的散热盖(heat dissipation lid)138，由此有助于在封装结构中维持较低温度。热界面材料140可包括例如具有良好导热系数(thermalconductivity)(其可介于约3瓦/米·度(W/m·K))至5W/m·K之间或大于5W/m·K)的聚合物等任何适合的导热材料。
接下来，贴合散热盖138。散热盖138除散热外还可为封装结构提供实体保护。散热盖138可具有例如介于约200W/m·K至约400W/m·K之间或高于400W/m·K的高导热系数，且可使用金属、金属合金、石墨烯、碳纳米管(carbon nanotube，CNT)等来形成散热盖138。在某些实施例中，利用粘合剂等将散热盖138贴合至衬底136，以使封装200排列于散热盖138的内腔内。在某些实施例中，可在散热盖138的内腔内放置一或多个表面装置144。在某些实施例中，可在衬底136上在散热盖138的周边外放置一或多个表面装置。
可存在其他实施例。参照图16A，其绘示其中在施加散热盖138之前衬底126已被移除的实施例。举例来说，在使用与以上结合图16A所论述的方法相同或相似的方法将封装200结合至衬底16B之后、且在某些实施例中在贴合散热盖138之前，移除衬底126。可选地在管芯118及120的被移除衬底126的表面上施加热界面材料140。接下来，使用与以上结合图16A所论述的方法相同或相似的方法来施加散热盖138。
如本文中所论述，根据某些实施例，提供一种衬底晶片上芯片(COWOS)封装。衬底可在COWOS封装中贴合至管芯的背侧。在制造期间，衬底可保护管芯且可减轻封装翘曲。这样一来，封装的可靠性可得到提高。在制造期间，衬底可用于为封装提供暂时实体支撑，由此减轻对单独的载体及载体剥离工艺的需要，此可有助于降低制造成本。
根据某些实施例提供一种方法。所述方法包括将第一管芯及第二管芯贴合至介插器。所述方法还包括将第一衬底贴合至所述第一管芯的第一表面及所述第二管芯的第一表面。所述第一衬底包含硅。所述第一管芯的所述第一表面与所述第一管芯的贴合至所述介插器的表面相对，且所述第二管芯的所述第一表面与所述第二管芯的贴合至所述介插器的表面相对。所述方法还包括将所述介插器结合至第二衬底。
在一些实施例中，进一步包括：对所述第一衬底的表面施加热界面材料；以及将散热盖贴合至所述第二衬底，所述第一衬底设置于所述散热盖的内腔中。
在一些实施例中，进一步包括将表面安装装置结合至所述第二衬底，其中在所述散热盖贴合至所述第二衬底之后，所述表面安装装置位于所述散热盖的所述内腔中。
在一些实施例中，所述第一管芯是逻辑管芯且所述第二管芯是存储器管芯。
在一些实施例中，所述第一衬底利用管芯贴合膜结合至所述第一管芯的所述第一表面及所述第二管芯的所述第一表面。
在一些实施例中，进一步包括：薄化所述介插器；其中在所述薄化期间，所述第一衬底位于所述介插器之下并为所述介插器提供实体支撑。
在一些实施例中，所述薄化暴露出所述介插器中所包括的穿孔。
在一些实施例中，进一步包括薄化所述第一衬底。
在一些实施例中，所述第一管芯包括第一存储器管芯及第二存储器管芯，所述第一存储器管芯通过连接件连接至所述第二存储器管芯。
在一些实施例中，进一步包括：在所述介插器之上形成多个电连接件，所述多个电连接件中的每一电连接件均电连接至所述介插器的穿孔；其中在所述形成所述多个电连接件期间，所述第一衬底对所述介插器进行实体支撑。
在一些实施例中，进一步包括在将所述介插器结合至所述第二衬底之前，移除所述第一衬底。
根据某些实施例提供一种方法。所述方法包括在第一衬底中形成多个穿孔。所述方法还包括将多个第一管芯及多个第二管芯贴合至所述第一衬底，并将所述多个第一管芯及所述多个第二管芯耦合至所述多个穿孔。所述方法还包括将所述多个第一管芯及所述多个第二管芯包封于模制材料中，其中所述多个第一管芯的顶表面及所述多个第二管芯的顶表面穿过所述模制材料被暴露出。所述方法还包括将第二衬底贴合至穿过所述模制材料被暴露出的所述多个第一管芯的所述顶表面及所述多个第二管芯的所述顶表面。所述方法还包括将所述第一衬底结合至第三衬底。
在一些实施例中，进一步包括将盖贴合至所述第三衬底，所述多个第一管芯的一个第一管芯及所述多个第二管芯的一个第二管芯设置于所述盖的腔中。
在一些实施例中，所述第二衬底设置于所述盖的所述腔内。
在一些实施例中，进一步包括：在贴合所述盖之前，从所述多个第一管芯的所述顶表面及所述多个第二管芯的所述顶表面移除所述第二衬底。
在一些实施例中，进一步包括在将所述第二衬底贴合至所述多个第一管芯的所述顶表面及所述多个第二管芯的所述顶表面之后，薄化所述第二衬底。
在一些实施例中，进一步包括将所述第一衬底单体化，其中在所述单体化之后，将所述多个第一管芯的一个第一管芯及所述多个第二管芯的一个第二管芯贴合至被结合至所述第三衬底的所述第一衬底的一部分。
在一些实施例中，在所述第一衬底之上形成多个电连接件，所述多个电连接件中的每一电连接件均电连接至所述第一衬底中的所述多个穿孔的一个穿孔；其中在所述形成所述多个电连接件期间，所述第二衬底对所述第一衬底进行实体支撑。
根据某些实施例提供一种装置。所述装置包括第一衬底及结合至所述第一衬底的介插器。第一管芯及第二管芯结合至所述介插器。模制材料沿所述第一管芯的侧壁及所述第二管芯的侧壁延伸，其中所述第一管芯的顶表面及所述第二管芯的顶表面穿过所述模制材料被暴露出。第二衬底贴合至穿过所述模制材料被暴露出的所述第一管芯的所述顶表面及所述第二管芯的所述顶表面。所述第二衬底包含硅。
在一些实施例中，进一步包括：散热盖，结合至所述第一衬底，其中所述介插器、所述第一管芯、所述第二管芯、及所述第二衬底分别设置于所述散热盖的内腔内。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (1)

1.一种衬底晶片上芯片结构的形成方法，其特征在于，包括：
将第一管芯及第二管芯贴合至介插器；
将第一衬底贴合至所述第一管芯的第一表面及所述第二管芯的第一表面，所述第一衬底包含硅，所述第一管芯的所述第一表面与所述第一管芯的贴合至所述介插器的表面相对，且所述第二管芯的所述第一表面与所述第二管芯的贴合至所述介插器的表面相对；以及
将所述介插器结合至第二衬底。
CN201710377159.9A 2016-12-30 2017-05-25 衬底晶片上芯片结构的形成方法 Pending CN108269767A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662441001P 2016-12-30 2016-12-30
US62/441,001 2016-12-30
US15/479,735 2017-04-05
US15/479,735 US10170457B2 (en) 2016-12-30 2017-04-05 COWOS structures and method of forming the same

Publications (1)

Publication Number Publication Date
CN108269767A true CN108269767A (zh) 2018-07-10

Family

ID=62711165

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710377159.9A Pending CN108269767A (zh) 2016-12-30 2017-05-25 衬底晶片上芯片结构的形成方法

Country Status (3)

Country Link
US (1) US10170457B2 (zh)
CN (1) CN108269767A (zh)
TW (1) TW201826403A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111834314A (zh) * 2019-04-23 2020-10-27 台湾积体电路制造股份有限公司 封装结构及其制造方法
CN113140534A (zh) * 2020-01-16 2021-07-20 台湾积体电路制造股份有限公司 封装结构和其制造方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727203B1 (en) * 2018-05-08 2020-07-28 Rockwell Collins, Inc. Die-in-die-cavity packaging
TWI697078B (zh) * 2018-08-03 2020-06-21 欣興電子股份有限公司 封裝基板結構與其接合方法
US10692795B2 (en) 2018-11-13 2020-06-23 International Business Machines Corporation Flip chip assembly of quantum computing devices
CN113035823A (zh) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 封装结构
US11424219B2 (en) * 2020-01-16 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US11114409B2 (en) * 2020-01-30 2021-09-07 Hewlett Packard Enterprise Development Lp Chip on wafer on substrate optoelectronic assembly and methods of assembly thereof
US11282825B2 (en) 2020-05-19 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US11776820B2 (en) * 2020-09-30 2023-10-03 Huawei Technologies Co., Ltd. Vertical interconnection structure and manufacturing method thereof, packaged chip, and chip packaging method
US11848246B2 (en) * 2021-03-24 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11862590B2 (en) 2021-04-14 2024-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of forming thereof
US20220367370A1 (en) * 2021-05-11 2022-11-17 Innolux Corporation Electronic device
US11908757B2 (en) * 2021-06-18 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Die corner removal for molding compound crack suppression in semiconductor die packaging and methods for forming the same
US20230290704A1 (en) * 2022-03-14 2023-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396403A (en) * 1993-07-06 1995-03-07 Hewlett-Packard Company Heat sink assembly with thermally-conductive plate for a plurality of integrated circuits on a substrate
TWI398943B (zh) * 2010-08-25 2013-06-11 Advanced Semiconductor Eng 半導體封裝結構及其製程
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111834314A (zh) * 2019-04-23 2020-10-27 台湾积体电路制造股份有限公司 封装结构及其制造方法
CN113140534A (zh) * 2020-01-16 2021-07-20 台湾积体电路制造股份有限公司 封装结构和其制造方法

Also Published As

Publication number Publication date
US20180190638A1 (en) 2018-07-05
US10170457B2 (en) 2019-01-01
TW201826403A (zh) 2018-07-16

Similar Documents

Publication Publication Date Title
CN108269767A (zh) 衬底晶片上芯片结构的形成方法
TWI669785B (zh) 半導體封裝體及其形成方法
TWI708363B (zh) 封裝、半導體封裝及封裝結構的形成方法
TWI653719B (zh) 半導體裝置及其形成方法
TWI683401B (zh) 半導體結構及其形成方法
US11594520B2 (en) Semiconductor package for thermal dissipation
KR101823225B1 (ko) 패키지 구조물 및 이의 형성 방법
TW202105626A (zh) 封裝結構及形成封裝結構的方法
TW202004926A (zh) 半導體結構及積體電路封裝的形成方法
TW201941390A (zh) 半導體封裝及其形成方法
CN110034026A (zh) 封装件结构和方法
CN109585404A (zh) 半导体封装及其形成方法
CN109786266A (zh) 半导体封装件及其形成方法
CN107644850A (zh) 半导体封装
TW202010084A (zh) 半導體封裝及其製造方法
CN105225967B (zh) 封装半导体器件的方法和封装的半导体器件
US11164855B2 (en) Package structure with a heat dissipating element and method of manufacturing the same
TW202015179A (zh) 積體電路封裝及其形成方法
KR102524244B1 (ko) 반도체 패키지들에서의 방열 및 그 형성 방법
CN110634750A (zh) 半导体装置及其制造方法
TW202129868A (zh) 記憶體裝置及其製造方法
US20230290747A1 (en) Heat dissipating features for laser drilling process
TW202401695A (zh) 半導體封裝及方法
TW202347650A (zh) 半導體封裝及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180710

WD01 Invention patent application deemed withdrawn after publication