TW201941390A - 半導體封裝及其形成方法 - Google Patents

半導體封裝及其形成方法 Download PDF

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TW201941390A
TW201941390A TW108105408A TW108105408A TW201941390A TW 201941390 A TW201941390 A TW 201941390A TW 108105408 A TW108105408 A TW 108105408A TW 108105408 A TW108105408 A TW 108105408A TW 201941390 A TW201941390 A TW 201941390A
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Taiwan
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dielectric layer
redistribution structure
package
metallization pattern
layer
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TW108105408A
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TWI710086B (zh
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蔡仲豪
余振華
王垂堂
吳凱強
林佳加
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台灣積體電路製造股份有限公司
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Abstract

一種裝置包括積體電路晶粒、模塑化合物以及第一重佈線結構。積體電路晶粒具有主動側及背側，背側與主動側相對。模塑化合物包封積體電路晶粒。第一重佈線結構上覆於積體電路晶粒及模塑化合物上。第一重佈線結構包括第一金屬化圖案及第一介電層。第一金屬化圖案電性耦合至積體電路晶粒的主動側。所述第一金屬化圖案的至少一部分形成電感器。

Description

半導體封裝及其形成方法
由於各種電子組件（例如，電晶體、二極體、電阻器、電容器等）積體密度持續提高，半導體行業經歷了快速發展。在很大程度上，積體密度提高起因於最小特徵尺寸（minimum feature size）的重複減小，此使得更多組件能夠被整合於給定區域中。隨著縮小電子裝置需求的增長，更小且更具創造性的半導體晶粒封裝技術的需求浮現。此種封裝系統的一個實例是疊層封裝（Package-on-Package，PoP）技術。在疊層封裝裝置中，頂部半導體封裝堆疊於底部半導體封裝的頂部上，以提供高積體程度及組件密度。疊層封裝技術一般而言能夠生產功能得到增強且在印刷電路板（printed circuit board，PCB）上佔用面積小的半導體裝置。
以下揭露內容提供用於實現本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例而不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複參考編號及/或字母。此種重複是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
電感器是一種被動電性組件，其可將能量儲存於藉由電流通過所述電感器而生成的磁場。電感器可被建構成由包繞在由介電材料或磁性材料形成的芯體周圍的導電材料形成的線圈。電感器的一個可量測的參數是電感器儲存磁能的能力，所述能力亦被稱為電感器的電感。另一個可量測的參數是電感器的品質因數（Quality factor，Q factor）。電感器的品質因數是電感器的效率的量度且可作為在給定頻率下電感器的感抗（inductive reactance）對電感器的電阻的比率來計算。
本文中所論述的實施例可在具體的上下文中論述，亦即具有組件（例如電感器、變壓器或其二者）的封裝結構（例如積體扇出型（integrated fan-out，InFO）封裝結構）被整合於重佈線結構中。被整合於重佈線結構中的組件可提供低成本及高效能的組件來改善射頻開關裝置的效能。射頻天線開關的改善的效能可包括改善的插入損耗（insertion loss）及改善的隔離性。舉例而言，電感器能夠消除互補金屬氧化物半導體（complementary metal oxide semiconductor，CMOS）裝置的寄生/耦合效應。另外，所揭露的實施例包括保護層來防止電感器的導電材料發生氧化。另外，所揭露的實施例包括將電感器的導電材料形成於重佈線結構的通孔溝槽（via trench）中以使電感器能夠達成較高的品質因數，且所揭露的實施例亦可改善變壓器的效能。此外，在一些實施例中，可將鄰近於組件的重佈線結構的介電材料移除（例如，氣隙鄰近於組件形成）以減小組件的寄生電容。包括氣隙的實施例可提高電感器的品質因數且亦可使電感器的自共振頻率（self resonate frequency）升高。相較於不具有電感器及/或變壓器的射頻開關裝置，包括耦合至射頻裝置開關的電感器的所揭露的實施例可使射頻開關裝置能夠具有較低的功率損耗及較高的隔離性。
此外，本揭露的教示內容適用於任何包括重佈線結構的封裝結構。其他實施例考慮到其他應用，藉由閱讀本揭露內容，此項技術中具有通常知識者將其應用在不同封裝類型或不同配置是顯而易見的。應注意，本文中所論述的實施例可能未必示出結構中可存在的每個組件或特徵。舉例而言，例如當對一個組件的論述足以表達實施例的各個態樣時，可自圖中省略多個所述組件。此外，本文中所論述的方法實施例可被論述成以特定次序執行；然而，其他方法實施例可以任何邏輯次序執行。
圖1、圖2、圖3、圖4、圖5、圖6、圖7、圖8、圖9、圖10、圖11、圖12、圖13、圖14A、圖15、圖16、圖17、圖18A-1、圖18A-2、圖18B-1、圖18B-2、圖18B-3、圖18B-4、圖19、圖20、圖21及圖22示出根據一些實施例的形成第一封裝結構的過程期間的中間步驟的剖視圖及平面圖。圖1示出載體基底100及形成於載體基底100上的離型層102。圖中分別示出了用於形成第一封裝及第二封裝的第一封裝區600及第二封裝區602。
載體基底100可為玻璃載體基底、陶瓷載體基底等。載體基底100可為晶圓，使得多個封裝可在載體基底100上同時形成。離型層102可由聚合物系材料形成，所述聚合物系材料可與載體基底100一起自在後續步驟中形成的上覆結構移除。在一些實施例中，離型層102為當受熱時會失去其黏合性質的環氧樹脂基熱離型材料，例如光熱轉換（light-to-heat-conversion，LTHC）離型塗層。在其他實施例中，離型層102可為當暴露至紫外（ultraviolet，UV）光時會失去其黏著性質的紫外膠。離型層102可以液體形態被分配並被固化，可為層疊至載體基底100上的疊層膜（laminate film）或可為類似材料。離型層102的頂表面可被整平且可具有高的共面程度（degree of coplanarity）。
在圖2中，形成介電層104及金屬化圖案106（有時被稱為重佈線層或重佈線）。在離型層102上形成介電層104。介電層104的底表面可接觸離型層102的頂表面。在一些實施例中，介電層104是由例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）等聚合物形成。在其他實施例中，介電層104是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）等；或者類似材料。介電層104可藉由任何可接受的沈積製程來形成，例如旋轉塗佈（spin coating）、化學氣相沈積（chemical vapor deposition，CVD）、層疊、類似製程或其組合。
在介電層104上形成金屬化圖案106。作為形成金屬化圖案106的實例，在介電層104之上形成晶種層（未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積（physical vapor deposition，PVD）等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露於光線以進行圖案化。光阻的圖案對應於金屬化圖案106。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆（例如，電鍍或無電鍍覆）等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程（ashing process）或剝除製程（stripping process）來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案106。
在圖3中，在金屬化圖案106及介電層104上形成介電層108。在一些實施例中，介電層108是由聚合物形成，所述聚合物可為可使用光微影罩幕進行圖案化的感光性材料（例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等）。在其他實施例中，介電層108是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或者類似材料。可藉由旋轉塗佈、層疊、化學氣相沈積、類似製程或其組合來形成介電層108。接著將介電層108圖案化以形成開口來暴露出金屬化圖案106的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層為感光性材料時將介電層108暴露至光線或者藉由使用例如非等向性蝕刻（anisotropic etch）進行蝕刻來進行。
介電層104及介電層108以及金屬化圖案106可被稱為背側重佈線結構110。在所示出的實施例中，背側重佈線結構110包括所述兩個介電層104及介電層108以及一個金屬化圖案106。在其他實施例中，背側重佈線結構110可包括任何數目的介電層、金屬化圖案及導通孔。可藉由重複進行形成金屬化圖案106及介電層108的製程而在背側重佈線結構110中形成一或多個額外金屬化圖案及介電層。在形成金屬化圖案期間可藉由在下伏介電層的開口中形成金屬化圖案的晶種層及導電材料來形成導通孔（未示出）。因此導通孔可與各種金屬化圖案進行內連及電性耦合。
在圖4中，形成電性連接件（例如，穿孔）112。電性連接件112將延伸穿過隨後形成的包封體130（參見圖7）且在下文中可被稱為穿孔112。作為實例，為形成電性連接件112，在背側重佈線結構110（例如，如圖所示的介電層108以及金屬化圖案106的被暴露出的部分）上形成晶種層。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光線以進行圖案化。光阻的圖案對應於穿孔。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電鍍覆）等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成電性連接件112。
在圖5中，藉由黏合劑116將積體電路晶粒114黏附至介電層108。儘管圖中示出在第一封裝區600及第二封裝區602中的每一者中黏附一個積體電路晶粒114，然而應理解，可在每一封裝區中黏附更多積體電路晶粒114。舉例而言，可在每一區中黏附兩個或三個積體電路晶粒114。積體電路晶粒114可為邏輯晶粒（例如中央處理單元、微控制器等）、記憶體晶粒（例如動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電源管理晶粒（例如，電源管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end，AFE）晶粒）、類似晶粒或其組合。另外，在一些實施例中，積體電路晶粒114可為不同大小（例如，不同高度及/或表面積），且在其他實施例中，積體電路晶粒114可為相同大小（例如，相同高度及/或表面積）。
在將積體電路晶粒114黏附至介電層108之前，可根據適用於在積體電路晶粒114中形成積體電路的製造製程來處理積體電路晶粒114。舉例而言，積體電路晶粒114各自包括半導體基底118，例如經摻雜或未經摻雜的矽、或絕緣層上半導體（semiconductor-on-insulator，SOI）基底的主動層。半導體基底可包含例如以下等其他半導體材料：鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或其組合。亦可使用例如多層式基底或梯度基底（gradient substrate）等其他基底。可在半導體基底118中及/或半導體基底118上形成例如電晶體、二極體、電容器、電阻器等裝置且可藉由例如位於半導體基底118上的一或多個介電層中的金屬化圖案形成的內連結構120來對各所述裝置進行內連以形成積體電路。
積體電路晶粒114更包括與外部連接的接墊122（例如鋁接墊）。接墊122位於可被稱為積體電路晶粒114的相應的主動側的位置上。積體電路晶粒114上及接墊122的部分上具有鈍化膜124。具有穿過鈍化膜124而到達接墊122的開口。在穿過鈍化膜124的開口中具有例如導電柱（例如包含例如銅等金屬）等晶粒連接件126，且晶粒連接件126機械地且電性地耦合至相應接墊122。可藉由例如鍍覆等來形成晶粒連接件126。晶粒連接件126電性耦合積體電路晶粒114的相應積體電路。
在積體電路晶粒114的主動側上、例如在鈍化膜124及晶粒連接件126上具有介電材料128。介電材料128橫向地包封晶粒連接件126，且介電材料128橫向地鄰接相應的積體電路晶粒114。介電材料128可為：聚合物，例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等；氮化物，例如氮化矽等；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等；類似材料或其組合，且可例如藉由旋轉塗佈、層疊、化學氣相沈積等來形成。
黏合劑116位於積體電路晶粒114的背側上且將積體電路晶粒114黏附至背側重佈線結構110（例如介電層108）。黏合劑116可為任何適合的黏合劑、環氧樹脂、晶粒貼合膜（die attach film，DAF）等。可將黏合劑116塗佈至積體電路晶粒114的背側，例如塗佈至相應的半導體晶圓的背側或可塗佈於載體基底100的表面之上。可例如藉由鋸切或切割而將積體電路晶粒114單體化，並使用例如拾取及放置工具（pick-and-place tool）藉由黏合劑116而將積體電路晶粒114黏附至介電層108。
在圖6中，在各個組件上形成包封體130。包封體130可為模製化合物、環氧樹脂等，且可藉由壓縮模製（compression molding）、轉移模製（transfer molding）等來塗佈。包封體130可形成於載體基底100之上以使得電性連接件112及/或積體電路晶粒114的晶粒連接件126被掩埋或被覆蓋。在一些實施例中，省略介電材料128且包封體130環繞晶粒連接件126並使晶粒連接件126鈍化。接著將包封體130固化。
在圖7中，對包封體130執行平坦化製程以暴露出電性連接件112及晶粒連接件126。平坦化製程亦可對介電材料128進行磨削。在平坦化製程之後，電性連接件112的頂表面、晶粒連接件126的頂表面、介電材料128的頂表面及包封體130的頂表面是共平面的。平坦化製程可為例如化學機械研磨（chemical-mechanical polish，CMP）、磨削製程等。在一些實施例中，舉例而言若已暴露出電性連接件112及晶粒連接件126，則可省略平坦化。
在圖8至圖13中，形成前側重佈線結構132。前側重佈線結構132包括積體組件150，例如電感器、變壓器或其二者（參見圖14A及圖15）。前側重佈線結構132包括介電層136及介電層140以及金屬化圖案138、接墊142A以及接墊142B。
可藉由在包封體130、電性連接件112及晶粒連接件126上沈積介電層136來再次形成前側重佈線結構132。在一些實施例中，介電層136是由聚合物形成，所述聚合物可為可使用光微影罩幕進行圖案化的感光性材料（例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等）。在其他實施例中，介電層136是由以下材料形成：氮化物，例如氮化矽；氧化物，例如氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃；或類似材料。可藉由旋轉塗佈、層疊、化學氣相沈積、類似製程或其組合來形成介電層136。
在圖9中，將介電層136圖案化。所述圖案化會形成開口以暴露出電性連接件112的一些部分及晶粒連接件126的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層136為感光性材料時將介電層136暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻來進行。若介電層136為感光性材料，則可在所述曝光之後將介電層136顯影。
在圖10中，在介電層136上形成具有通孔的金屬化圖案138。作為實例，為形成金屬化圖案138，在介電層136之上及穿過介電層136的開口中形成晶種層（未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光線以進行圖案化。光阻的圖案對應於金屬化圖案138。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電鍍覆）等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案138及通孔。所述通孔形成於穿過介電層136而到達例如電性連接件112及/或晶粒連接件126的開口中。
在圖11中，在介電層136及金屬化圖案138之上形成介電層140。用於形成介電層140的材料及製程可相似於介電層136，在本文中不再對其予以贅述。
在圖12中，接著將介電層140圖案化。所述圖案化會形成開口以暴露出金屬化圖案138的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在所述介電層為感光性材料時將介電層140暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻來進行。若介電層140為感光性材料，則可在所述曝光之後將介電層140顯影。
在圖13中，在介電層140及金屬化圖案138上形成接墊142A及接墊142B。接墊142A用於耦合至導電連接件144（參見圖14）且可被稱為凸塊下金屬（under bump metallurgy，UBM）。接墊142B是積體組件150（參見圖15及圖16）的一部分，且可被稱為組件的接墊。在所示出的實施例中，接墊142A及接墊142B是穿過貫穿介電層140而到達金屬化圖案138的開口形成的。作為實例，為形成接墊142A及接墊142B，在介電層140之上形成晶種層（未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光線以進行圖案化。光阻的圖案對應於接墊142A及接墊142B。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中以及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆（例如電鍍或無電鍍覆）等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成接墊142A及接墊142B。在其中接墊142A及接墊142B以不同的方式形成的實施例中，可利用更多光阻及圖案化步驟。
前側重佈線結構132被示出而作為實例。在前側重佈線結構132中可形成更多或更少的介電層及金屬化圖案。若欲形成更少的介電層及金屬化圖案，則可省略上述步驟及製程。若欲形成更多的介電層及金屬化圖案，則可重複上述步驟及製程。此項技術中具有通常知識者將易於理解哪些步驟及製程將被省略或重複進行。
在圖14A中，在接墊142A上形成導電連接件144而不在接墊142B上形成導電連接件144。在一些實施例中，在形成導電連接件144期間，由罩幕（未示出）覆蓋接墊142B。導電連接件144可為球柵陣列（ball grid array，BGA）連接件、焊球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、化學鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。導電連接件144可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中，藉由以下方式來形成導電連接件144：首先藉由例如蒸鍍、電鍍、印刷、焊料轉移（solder transfer）、植球（ball placement）等該些常用方法來形成焊料層。一旦已在所述結構上形成焊料層，則可執行回焊（reflow）以將所述材料造型成所期望的凸塊形狀。在另一實施例中，導電連接件144為藉由濺鍍、印刷、電鍍、無電鍍覆、化學氣相沈積等而形成的金屬柱（例如銅柱）。所述金屬柱可無焊料且具有實質上垂直的側壁。在一些實施例中，在導電連接件144的頂部上形成金屬頂蓋層（未示出）。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似材料或其組合，且可藉由鍍覆製程來形成。
如圖14A及圖15所示，第一封裝區600及第二封裝區602中的每一者中的前側重佈線結構132包括至少一個積體組件150。在此實施例中，積體組件150是電感器。圖15是第一封裝區600或第二封裝區602中的一者中的積體組件150的平面圖，其示出積體組件150，其中積體組件150在圖14A中的剖視圖是沿著圖15所示線A-A截取的。積體組件150由金屬化圖案138及通孔以及接墊142B形成。金屬化圖案138及通孔以及接墊142B形成多個同心環，其中外環包圍內環。所述各環具有斷點（break）以使外環能夠藉由橋接件152連接至內環，且所述多個環（有時稱為線圈）串聯連接至兩個埠155。
在所示出的實施例中，接墊142B在金屬化圖案138及通孔之上形成橋接件152，但是在其他實施例中，此種關係可顛倒。橋接件152可形成於接墊142B的上部部分（位於介電層140的頂表面上的線路部分）上，所述上部部分不包括延伸穿過介電層140的通孔部分。
圖14B-1、圖14B-2、圖14B-3、圖14B-4、圖14B-5、圖14B-6、圖14B-7及圖14B-8示出開關電路的實施例的示例性示意圖，所述開關電路包括耦合至開關電路的開關的電感器/變壓器。在實施例中，積體電路晶粒114包括射頻裝置開關157（圖14B-7），積體組件150經由晶粒連接件126耦合至射頻裝置開關157。被整合於前側重佈線結構132中的積體組件150可提供低成本及高效能的積體組件150來改善射頻裝置開關157的效能。射頻裝置開關157的改善的效能可包括改善的插入損耗及改善的隔離性。舉例而言，積體組件150能夠消除互補金屬氧化物半導體裝置的寄生/耦合效應。另外，積體組件150的導電材料被形成為包括前側重佈線結構的通孔溝槽，此使得能夠將較粗的導體用於電感器的環，此進而能夠提高電感器的效能（例如，使品質因數較高）。
圖14B-1示出示例性開關電路且圖14B-2示出圖14B-1中電路的傳送（Tx）模式及接收（Rx）模式的操作，其中圖14B-1中的頂部電路示出傳送模式且底部電路示出接收模式。
圖14B-3示出示例性開關電路且圖14B-4示出圖14B-3中電路的傳送模式及接收模式的操作，其中圖14B-4中的頂部電路示出傳送模式且底部電路示出接收模式。
圖14B-5示出示例性開關電路且圖14B-6示出圖14B-5中電路的傳送模式及接收模式的操作，其中圖14B-6中的頂部電路示出傳送模式且底部電路示出接收模式。
對於圖14B-1、圖14B-3及圖14B-5中的電路中的每一者，在傳送模式中，電晶體157-1及電晶體157-1’導通且電晶體157-2及電晶體157-2’斷開。對於接收模式中的該些電路，電晶體157-1及電晶體157-1’斷開且電晶體157-2及電晶體157-2’導通。該些配置示出於圖14B-2、圖14B-4及圖14B-6中。
圖14B-7及圖14B-8示出具有變壓器配置而非前面實例的電感器配置的開關電路。對於圖14B-7及圖14B-8，在傳送模式中，射頻裝置開關157導通，且在接收模式中，射頻裝置開關157斷開。
儘管圖14及圖15示出雙匝式電感器（即，具有兩個環的電感器），然而應理解，在每一第一封裝區600及第二封裝區602的前側重佈線結構132中可形成具有更多個匝的電感器。舉例而言，可在每一第一封裝區600及第二封裝區602中形成三匝式或四匝式電感器。
圖16是第一封裝區600或第二封裝區602中的一者的平面圖，其示出區中的多個積體組件150。此平面圖省略了前側重佈線結構132的介電層且亦省略了前側重佈線結構132中的其他金屬化圖案。圖14A中的剖視圖是沿著圖16的線A-A截取，其中平面圖16僅示出一個積體電路晶粒114。儘管圖16示出五個積體組件150，然而在其他實施例中，根據積體電路及/或封裝的設計需要而定，可存在更多或更少的積體組件150。另外，在一些實施例中，積體組件150中的一或多者亦可為變壓器（參見，例如圖18A-1、圖18A-2、圖18B-1、圖18B-2、圖18B-3及圖18B-4）。
在圖17中，在前側重佈線結構132、接墊142A、接墊142B之上以及鄰接及環繞導電連接件144形成絕緣的保護層146。保護層146可防止接墊142B發生氧化且可在後續回焊期間為導電連接件144提供橫向支撐。在實施例中，保護層146是非導電材料，例如環氧樹脂、樹脂、聚醯亞胺、聚苯並噁唑、苯並環丁烯、矽酮、丙烯酸酯、添加或未添加矽石基填料或玻璃填料的聚合物、類似材料或其組合。在一些實施例中，保護層146包括液體模塑化合物（liquid molding compound，LMC），所述液體模塑化合物在被塗佈時是凝膠型液體。保護層146在被塗佈時可為液體或固體。作為另外一種選擇，保護層146可包含其他絕緣材料及/或包封材料。保護層146在一些實施例中是使用晶圓級模塑製程被塗佈的。保護層146可被形成為使頂表面位於導電連接件144的頂點之上，與導電連接件144的頂點實質上齊平或位於導電連接件144的頂點下面。保護層146可使用例如壓縮模塑、轉移模塑或其他方法來進行模塑。
接下來，在一些實施例中，使用固化製程將保護層146固化。所述固化製程可包括使用退火製程或其他加熱製程將保護層146加熱至預定溫度達預定時間區段。固化製程亦可包括紫外線曝光製程、紅外（infrared，IR）能量曝光製程、其組合或其與加熱製程的組合。作為另外一種選擇，可使用其他方法將保護層146固化。在一些實施例中，不包括固化製程。
在其中保護層146不是聚合物的實施例中，因其他保護層材料較聚合物廉價，故保護積體組件150不發生氧化的成本降低。
在一些實施例中，積體組件150可包括變壓器、電感器或其二者。圖18A-1是第一封裝區600或第二封裝區602中的一者的平面圖，其示出多個積體組件150，其中積體組件中的一者是電感器150A且另一組件是變壓器150B。此平面圖省略了前側重佈線結構132的介電層且亦省略了前側重佈線結構132中的其他金屬化圖案。圖18B-1中的剖視圖是沿著圖18A-1的線B-B截取的。儘管圖18A-1示出一個電感器150A及一個變壓器150B，然而在其他實施例中，根據積體電路及/或封裝的設計需要而定，可存在更多或更少的電感器150A及更多或更少的變壓器150B。
圖18A-2是第一封裝區600或第二封裝區602中的一者的平面圖，其示出多個積體組件150，其中所述兩個積體組件皆是變壓器。此平面圖省略了前側重佈線結構132的介電層且亦省略了前側重佈線結構132中的其他金屬化圖案。圖18B-2中的剖視圖是沿著圖18A-2的線D-D截取的。圖18B-3及圖18B-4中的剖視圖是沿著圖18A-2的線C-C的不同配置。儘管圖18A-2示出變壓器150A’及一個變壓器150B’，然而在其他實施例中，根據積體電路及/或封裝的設計需要而定，可存在更多或更少的變壓器且可包括電感器。
圖18B-1、圖18B-2、圖18B-3及圖18B-4示出與以上在圖17中所闡述者相似的中間處理階段，且在本文中不再對此中間處理階段予以贅述。在該些實施例中，變壓器及/或電感器由電感器150A、變壓器150B、變壓器150A’或變壓器150B’形成，其中重佈線結構的金屬化圖案及接墊形成變壓器及/或電感器的線圈。圖18B-3中的實施例與其他實施例相較在前側重佈線結構132中包括更多層階的金屬化圖案及介電層。但是其他實施例亦可包括與圖中所示不同數目的層。
本揭露的任意實施例可包括重佈線結構，所述重佈線結構包括一或多個電感器、一或多個變壓器或其組合。
圖19至圖22使用圖17中的實施例作為實例示出另外的操作及步驟，但該些步驟亦可對圖18B-1至18B-4的實施例執行。
在圖19中，執行載體基底剝離（carrier substrate de-bonding）以將載體基底100自背側重佈線結構110（例如，介電層104）分離（剝離）。藉此在第一封裝區600及第二封裝區602中的每一者中形成第一封裝200。根據一些實施例，所述剝離包括在離型層102上投射例如雷射光或紫外光等光，以使得離型層102在所述光線的熱量作用下分解，且可移除載體基底100。接著將所述結構翻轉並放置於膠帶176上。
在圖20中，穿過介電層104形成開口178以暴露出金屬化圖案106的一些部分。可例如使用雷射鑽孔（laser drilling）、蝕刻等來形成開口178。
圖21及圖22示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖。所述封裝結構可被稱為疊層封裝結構。
在圖21中，將第二封裝300貼合至第一封裝200。第二封裝300包括基底302及耦合至基底302的一或多個堆疊的晶粒308A及晶粒308B。儘管圖中示出晶粒308A及晶粒308B的單個堆疊，然而在其他實施例中，可並排地設置多個堆疊的晶粒308A及晶粒308B，所述多個堆疊的晶粒308A及晶粒308B耦合至基底302的同一表面。基底302可由例如矽、鍺、金剛石等半導體材料製成。在一些實施例中，亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷化鎵（gallium arsenic phosphide）、磷化鎵銦、其組合及類似材料等化合物材料。另外，基底302可為絕緣層上矽（SOI）基底。一般而言，絕緣層上矽基底包括例如磊晶矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料的層。在一個替代性實施例中，基底302是基於例如經玻璃纖維強化的樹脂芯體等絕緣芯體。一種示例性芯體材料為玻璃纖維樹脂（例如FR4）。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪（bismaleimide-triazine，BT）樹脂，或者作為另一選擇，為其他印刷電路板材料或膜。可對基底302使用例如味之素增層膜（Ajinomoto build-up film，ABF）等增層膜或其他疊層。
基底302可包括主動裝置及被動裝置（未示出）。如此項技術中具有通常知識者將理解，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生第二封裝300的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
基底302亦可包括金屬化層（未示出）及穿孔306。金屬化層可形成於主動裝置及被動裝置之上並被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交錯的介電質（例如低介電常數（low-k）介電材料）層與導電材料（例如銅）層形成且可藉由任何適合的製程（例如沈積、鑲嵌、雙鑲嵌等）來形成，其中由通孔對各層導電材料進行內連。在一些實施例中，基底302實質上無主動裝置及被動裝置。
基底302可具有位於基底302的第一側上的結合墊303以耦合至堆疊晶粒308，並具有位於基底302的第二側上的結合墊304以耦合至導電連接件314，基底302的第二側與第一側相對。在一些實施例中，藉由在基底302的第一側及第二側上的介電層（未示出）中形成凹槽（未示出）來形成結合墊303及結合墊304。所述凹槽可被形成為使得結合墊303及結合墊304能夠嵌置於介電層中。在其他實施例中，由於可在介電層上形成結合墊303及結合墊304，因此省略所述凹槽。在一些實施例中，結合墊303及結合墊304包括由銅、鈦、鎳、金、鈀、類似材料或其組合製成的薄晶種層（未示出）。可在所述薄晶種層之上沈積結合墊303及結合墊304的導電材料。可藉由電化學鍍覆製程（electro-chemical plating process）、無電鍍覆製程、化學氣相沈積、原子層沉積（ALD）、物理氣相沈積、類似製程或其組合來形成所述導電材料。在實施例中，結合墊303及結合墊304的導電材料為銅、鎢、鋁、銀、金、類似材料或其組合。
在實施例中，結合墊303及結合墊304為包含三個導電材料層（例如鈦層、銅層、及鎳層）的凸塊下金屬。然而，此項技術中具有通常知識者將認識到，有諸多適合的材料及層的排列（例如為鉻/鉻-銅合金/銅/金的排列、為鈦/鈦鎢/銅的排列、或為銅/鎳/金的排列）適合於形成結合墊303及結合墊304。可用於結合墊303及結合墊304的任何適合的材料或材料層全部包含於當前申請案的範圍內。在一些實施例中，穿孔306延伸穿過基底302且將至少一個結合墊303耦合至至少一個結合墊304。
在所示實施例中，堆疊晶粒308是藉由導線結合件310耦合至基底302的，但是亦可使用其他連接件（例如導電凸塊）。在實施例中，堆疊的晶粒308A及晶粒308B為堆疊的記憶體晶粒。舉例而言，堆疊的晶粒308A及晶粒308B可為記憶體晶粒，例如低功率（low-power，LP）雙倍資料速率（double data rate，DDR）記憶體模組，例如LPDDR1、LPDDR2、LPDDR3、LPDD4或類似的記憶體模組。
可藉由模製材料312來包封堆疊的晶粒308A及晶粒308B及導線結合件310。可例如使用壓縮模製將模製材料312模製於堆疊的晶粒308A及晶粒308B及導線結合件310上。在一些實施例中，模製材料312為模製化合物、聚合物、環氧樹脂、氧化矽填充材料、類似材料或其組合。可執行固化步驟以固化模製材料312，其中所述固化可為熱固化、紫外固化、類似固化或其組合。
在一些實施例中，將堆疊的晶粒308A及晶粒308B及導線結合件310掩埋於模製材料312中，且在模製材料312固化之後，執行平坦化步驟（例如磨削）以移除模製材料312的過量部分並為第二封裝300提供實質上平坦的表面。
在形成第二封裝300之後，藉由導電連接件314、結合墊304及金屬化圖案106將第二封裝300機械地及電性地結合至第一封裝200。在一些實施例中，可藉由導線結合件310、結合墊303及304、穿孔306、導電連接件314及電性連接件112將堆疊的晶粒308A及晶粒308B耦合至積體電路晶粒114。
儘管導電連接件314與導電連接件144無需為相同的，然而導電連接件314可相似於上述導電連接件144且本文中不再對其予以贅述。導電連接件314可在開口178中設置於基底302的與堆疊的晶粒308A及晶粒308B相對的側上。在一些實施例中，在基底302的與堆疊的晶粒308A及晶粒308B相對的側上亦可形成阻焊劑（未單獨標記）。導電連接件314可在阻焊劑中的開口中被設置成電性地且機械地耦合至基底302中的導電特徵（例如，結合墊304）。阻焊劑可用於保護基底302的一些區域不受外部損壞。
在一些實施例中，在對導電連接件314進行結合之前，以例如免清洗焊劑（no-clean flux）等焊劑（未示出）塗佈導電連接件314。可將導電連接件314浸入焊劑中或可將焊劑射出至導電連接件314上。在另一實施例中，可將焊劑塗佈至金屬化圖案106的表面。
在一些實施例中，在導電連接件314被回焊之前在導電連接件314上可形成有可選擇性的環氧樹脂焊劑（未示出），其中所述環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分將在第二封裝300貼合至第一封裝200之後剩餘。
可在第一封裝200與第二封裝300之間且環繞導電連接件314形成底部填充物（未示出）。底部填充物可減小應力並保護由對導電連接件314進行回焊而形成的接頭。底部填充物可在貼合第一封裝200之後藉由毛細流動製程（capillary flow process）來形成或者可在貼合第一封裝200之前藉由適合的沈積方法來形成。在其中形成環氧樹脂焊劑的實施例中，環氧樹脂焊劑可充當底部填充物。
第二封裝300與第一封裝200之間的結合可為焊料結合。在實施例中，藉由回焊製程將第二封裝300結合至第一封裝200。在此回焊製程期間，導電連接件314接觸結合墊304及金屬化圖案106以將第二封裝300實體地且電性地耦合至第一封裝200。在結合製程之後，可在金屬化圖案106與導電連接件314的介面處且亦在導電連接件314與結合墊304（未示出）之間的介面處形成中介金屬化合物（intermetallic compound，IMC）（未示出）。
藉由沿切割道區（例如，在第一封裝區600與第二封裝區602之間）進行鋸切來執行單體化製程。所述鋸切使第一封裝區600自第二封裝區602單體化。所得的被單體化的第一封裝200及第二封裝300來自第一封裝區600或第二封裝區602中的一者。在一些實施例中，單體化製程是在將第二封裝300貼合至第一封裝200之後執行的。在其他實施例（未示出）中，單體化製程是在將第二封裝300貼合至第一封裝200之前執行的，例如在剝離載體基底100且形成開口178之後執行。
在圖22中，使用導電連接件144將第一封裝200安裝至封裝基底400。封裝基底400可由例如矽、鍺、金剛石等半導體材料製成。作為另外一種選擇，亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化砷化鎵、磷化鎵銦、其組合等化合物材料。另外，封裝基底400可為絕緣層上矽基底。一般而言，絕緣層上矽基底包括例如磊晶矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺或其組合等半導體材料的層。在一個替代性實施例中，封裝基底400是基於例如被玻璃纖維強化的樹脂芯體等絕緣芯體。一種示例性芯體材料為玻璃纖維樹脂（例如玻璃纖維樹脂）。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪樹脂，或者作為另外一種選擇，為其他印刷電路板材料或膜。可對封裝基底400使用例如味之素增層膜等增層膜或其他疊層。
封裝基底400可包括主動裝置及被動裝置（未示出）。如此項技術中具有通常知識者將認識到，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生封裝結構的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。
封裝基底400亦可包括金屬化層及通孔（未示出）以及位於所述金屬化層及通孔之上的結合墊402。金屬化層可在主動裝置及被動裝置之上形成並被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交錯的介電質（例如低介電常數介電材料）層與導電材料（例如銅）層形成且可藉由任何適合的製程（例如沈積、鑲嵌、雙鑲嵌等）來形成，其中由通孔對各層導電材料進行內連。在一些實施例中，封裝基底400實質上無主動裝置及被動裝置。
在一些實施例中，將導電連接件144回焊以將第一封裝200貼合至結合墊402。導電連接件144將封裝基底400（包括封裝基底400中的金屬化層）電性地及/或實體地耦合至第一封裝200。在一些實施例中，可將被動裝置（例如，表面安裝裝置（surface mount device，SMD），未示出）在安裝於封裝基底400之前貼合至第一封裝200（例如，結合至結合墊402）。在該些實施例中，可將被動裝置結合至第一封裝200的與導電連接件144相同的表面。
在對導電連接件144進行回焊之前導電連接件144上可形成有環氧樹脂焊劑（未示出），其中環氧樹脂焊劑的環氧樹脂部分中的至少一些環氧樹脂部分將在第一封裝200貼合至封裝基底400之後剩餘。此一剩餘的環氧樹脂部分可充當底部填充物以減小應力並保護由對導電連接件144進行回焊而形成的接頭。在一些實施例中，可在第一封裝200與封裝基底400之間且環繞導電連接件144形成底部填充物（未示出）。可在貼合第一封裝200之後藉由毛細流動製程來形成底部填充物或者可在貼合第一封裝200之前藉由適合的沈積方法來形成所述底部填充物。
圖23至圖26示出根據一些實施例的另一封裝結構的剖視圖。圖23至圖26中的實施例相似於圖1至圖22所示實施例，只是此實施例包括積體天線，所述積體天線包括貼片式天線及可選的輻射天線。所述貼片式天線包括一或多條訊號線（在本文中亦被稱為饋送線）、接地元件及一或多個輻射元件。在本文中將不再對關於此實施例的與前述實施例相似的詳細說明予以贅述。
圖23示出與以上在圖19中所述者相似的中間處理階段，且在本文中不再對此中間處理階段予以贅述。在圖23中，背側重佈線結構110包括金屬化圖案106，金屬化圖案106可為貼片式天線的接地元件及饋送線（feed line）。另外，在此實施例中可省略及/或移除背側重佈線結構上的介電層104。
在一些實施例中，每一第一封裝區600及第二封裝區602中的封裝結構202皆包括延伸穿過包封體130的輻射天線216。在一些實施例中，輻射天線216是偶極天線（dipole antenna）。輻射天線216包括延伸穿過包封體130的導電特徵。該些導電特徵可與電性連接件112藉由與電性連接件112相同的製程同時形成。輻射天線216藉由前側重佈線結構132中的金屬化圖案電性連接至相應的積體電路晶粒114。輻射天線的形狀及配置被選擇成使得能夠向封裝202外部的其他裝置（未示出）發送無線訊號以及自封裝202外部的其他裝置接收無線訊號。在其他實施例中，可省略輻射天線。
圖24示出對圖23的結構進行的進一步處理。在圖24中，在介電層104（若存在）之上形成介電層210。在一些實施例中，介電層210包含耗散因數（dissipation factor，DF）相對低的材料以達成具有適當效率的貼片式天線。舉例而言，介電層210的耗散因數可小於約0.01或者在一些實施例中甚至小於約0.001。另外，介電層210的介電常數值可處於自約3至約4的範圍內，在實施例中，介電層210的厚度與貼片式天線214（參見圖25）的操作頻率相關。舉例而言，介電層210的厚度可與貼片式天線214的操作頻率成反比。在實施例中，當貼片式天線214具有至少60吉赫茲的操作頻率時，介電層210的厚度可處於約200微米至約300微米的範圍內。介電層210可使用任意適合的製程（例如疊層製程）形成。在其他實施例中，亦可使用其他沈積製程（例如，物理氣相沈積、化學氣相沈積、旋塗技術等）。在包括輻射天線216的實施例中，包封體130亦可由耗散因數低的材料形成。
在圖25中，在介電層210之上形成貼片式天線214的輻射元件212。在俯視圖中，輻射元件212可具有矩形形狀且與接地元件及金屬化圖案106重疊，但是在其他實施例中亦涵蓋其他形狀。輻射元件212可包含任意適合的導電材料（例如銅），但是在其他實施例中亦可使用其他導電材料。輻射元件212可藉由黏合劑（未示出）黏附於介電層210的表面上。在一些實施例中，黏合劑可為環氧樹脂，在輻射元件212黏附於介電層210上之前塗佈至輻射元件212。接著可（例如，藉由拾取及放置工具）將輻射元件212放置於介電層210上，且可（例如，藉由加熱）活化黏合劑以將輻射元件212黏附於介電層210上。在其他實施例中，不包括黏合劑且輻射元件212直接黏附至介電層210。在其他實施例中，使用不同方法在介電層210上形成輻射元件212，例如藉由以下步驟：沈積晶種層；在晶種層之上形成圖案化罩幕以界定輻射元件212的圖案；在被圖案化的罩幕的開口中鍍覆輻射元件；以及移除被圖案化的罩幕及晶種層的過量部分。亦可對輻射元件212進行其他沈積製程。
輻射元件212電性耦合至下伏的接地元件及金屬化圖案106以用於傳送及接收無線訊號。由此，貼片式天線214（包括接地元件及金屬化圖案106、介電層210的一些部分及輻射元件212）形成。貼片式天線214中的每一者整合在與積體電路晶粒114及積體組件150相同的半導體封裝中。黏合劑116和介電層108在實體上分離且有助於將積體電路晶粒114中的每一者與相應的貼片式天線214隔離以提高貼片式天線214的效率。
在圖26中，藉由沿切割道區（例如，在第一封裝區600與第二封裝區602之間）進行鋸切來執行單體化製程。所述鋸切使第一封裝區600自第二封裝區602單體化。所得的被單體化的封裝202來自第一封裝區600或第二封裝區602中的一者。
在圖26之後，可對封裝202進行進一步處理，例如，如以上在圖22所示前一實施例中所述將封裝202安裝至封裝基底400，且在本文中不再對其予以贅述。
圖27示出根據一些實施例的被單體化的封裝結構的剖視圖。此實施例相似於圖1至圖22中所示的實施例，只是此實施例省略了電性連接件112且可不包括第二封裝300。在本文中將不再對關於此實施例的與前述實施例相似的詳細說明予以贅述。
此實施例可藉由圖1至圖18中所述的相似的處理來形成（只是省略了電性連接件112及背側重佈線結構110），且在本文中不再對其予以贅述。封裝結構可以晶圓規模相似地形成且接著在形成保護層146之後被單體化。
圖28示出根據一些實施例的另一封裝結構的剖視圖。此實施例相似於圖1至圖22所示實施例，只是此實施例利用保護層146僅部分地覆蓋晶圓規模結構。藉由利用保護層146僅覆蓋接墊142B，封裝結構的成本可降低。在本文中將不再對關於此實施例的與前述實施例相似的詳細說明予以贅述。
圖28示出與以上在圖18中所述者相似的中間處理階段，且在本文中不再對此中間處理階段予以贅述。在圖28中，保護層146僅被形成為覆蓋接墊142B而不覆蓋整個前側重佈線結構132。此實施例仍會對積體組件150提供防氧化保護且與圖1至圖22的實施例相較亦會節省成本。
在圖28之後，可如以上參考圖19至圖22所述進一步處理封裝結構且在本文中不再對其予以贅述。
圖29至圖34示出根據一些實施例的另一封裝結構的剖視圖。圖29至圖34中的實施例相似於圖28所示實施例，只是此實施例在前側重佈線結構132的與積體組件150鄰近的介電材料中包括開口158（例如，氣隙）。位於與積體組件150鄰近的介電材料中的這些開口158可減小電感器的寄生電容。包括開口/氣隙的實施例可提高積體組件150的品質因數且亦可使積體組件150的自共振頻率升高。在本文中將不再對關於此實施例的與前述實施例相似的詳細說明予以贅述。
圖29示出與以上在圖8中所述者相似的中間處理階段，且在本文中不再對此中間處理階段予以贅述。
在圖30中，將介電層136圖案化。所述圖案化會形成開口154以暴露出電性連接件112的一些部分及晶粒連接件126的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層136為感光性材料時將介電層136暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻來進行。若介電層136為感光性材料，則可在所述曝光之後將介電層136顯影。
此圖案化步驟相似於以上在圖9中所述的圖案化步驟，但是在圖30所示實施例中存在附加的開口154，附加的開口154將用於在積體組件150周圍形成氣隙。
圖31及圖32示出與以上在圖10及圖11中所述者相似的中間處理階段，且在本文中不再對該些中間處理階段予以贅述。在此實施例中，由於在介電層136中形成了附加的開口154且在該些開口154中不形成金屬化圖案或通孔，因此在介電層140中存在凹槽156。
在圖33中，接著將介電層140圖案化。所述圖案化會形成暴露出金屬化圖案138的一些部分的開口且形成暴露出包封體130的開口158。此相同的圖案化製程亦對位於凹槽156下面的下伏的介電層136進行圖案化以形成開口158。開口158自介電層140的頂表面延伸至包封體130。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層為感光性材料時將介電層140暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻來進行。若介電層140為感光性材料，則可在所述曝光之後將介電層140顯影。
在圖34中，形成保護層146以覆蓋接墊142B。與圖28的實施例相似，保護層146僅被形成為覆蓋接墊142B而不覆蓋整個前側重佈線結構132。此實施例仍對積體組件150提供防氧化保護且與圖1至圖22的實施例相較亦會節省成本。
在圖34之後，可如以上參考圖19至圖22所述進一步處理封裝結構且在本文中不再對其予以贅述。
圖35至圖37示出根據一些實施例的另一封裝結構的剖視圖。圖35至圖37中的實施例相似於圖19至圖22所示實施例，只是在此實施例中，省略了保護層146且前側重佈線結構132包括另一介電層160以覆蓋接墊142B。在本文中將不再對關於此實施例的與前述實施例相似的詳細說明予以贅述。
圖35示出與以上在圖13中所述者相似的中間處理階段，且在本文中不再對此中間處理階段予以贅述。
在圖35中，在介電層140上形成金屬化圖案161以及通孔。可形成接墊142B作為金屬化圖案161的一部分。作為實例，為形成金屬化圖案161，在介電層140之上且在穿過介電層140的開口中形成晶種層（未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積等來形成晶種層。接著在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露於光線以進行圖案化。光阻的圖案對應於金屬化圖案161。所述圖案化會形成穿過光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的被暴露出的部分上形成導電材料。可藉由鍍覆（例如，電鍍或無電鍍覆）等來形成所述導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程（例如藉由濕式蝕刻或乾式蝕刻）來移除晶種層的被暴露出的部分。晶種層的剩餘部分與導電材料形成金屬化圖案161及通孔。所述通孔形成於穿過介電層140而到達例如金屬化圖案138的開口中。
在圖36中，在介電層140及金屬化圖案161之上形成介電層160。用於形成介電層160的材料及製程可相似於介電層140，在本文中不再對其予以贅述。
此外，在圖36中，接著將介電層160圖案化。所述圖案化會形成開口以暴露出金屬化圖案161的一些部分。所述圖案化可藉由可接受的製程來進行，例如藉由在介電層為感光性材料時將介電層160暴露至光線或者藉由使用例如非等向性蝕刻進行蝕刻來進行。若介電層160為感光性材料，則可在所述曝光之後將介電層160顯影。
圖37示出對圖36所示結構進行的進一步處理。此一處理過程相似於以上在圖13及圖14A中所述者，且在本文中不再對其進行贅述。在此實施例中，接墊162在功能上相似於接墊142A且導電連接件164在功能上相似於導電連接件144。
圖38示出根據一些實施例的另一封裝結構的剖視圖。圖38中的實施例相似於圖35至圖37所示實施例，只是在此實施例中，積體組件150在金屬化圖案138處不包括通孔而是僅包括金屬化圖案138。在本文中將不再對關於此實施例的與前述實施例相似的詳細說明予以贅述。
本發明實施例可達成諸多優點。本文中所論述的實施例包括使組件（例如電感器、變壓器或其二者）整合於重佈線結構中的封裝結構（例如積體扇出型封裝結構）。被整合於重佈線結構中的組件可提供低成本及高效能的組件來改善射頻開關裝置的效能。射頻天線開關的改善的效能可包括改善的插入損耗及改善的隔離性。舉例而言，電感器能夠消除互補金屬氧化物半導體裝置的寄生/耦合效應。另外，所揭露的實施例包括保護層來防止電感器的導電材料發生氧化。另外，所揭露的實施例包括將電感器的導電材料形成於重佈線結構的通孔溝槽中以使電感器能夠達成較高的品質因數且所揭露的實施例亦可改善變壓器的效能。此外，在一些實施例中，可將與組件相鄰近的重佈線結構的介電材料移除（例如，與組件相鄰近地形成氣隙）以減小組件的寄生電容。包括氣隙的實施例可提高電感器的品質因數且亦可使電感器的自共振頻率升高。相較於不具有電感器及/或變壓器的射頻開關裝置，包括耦合至射頻裝置開關的電感器的所揭露的實施例可使射頻開關裝置能夠具有較低的功率損耗及較高的隔離性。
本發明實施例是一種半導體封裝，半導體封裝包括積體電路晶粒、模塑化合物以及第一重佈線結構。積體電路晶粒具有主動側及背側。背側與主動側相對。模塑化合物包封積體電路晶粒。第一重佈線結構上覆於積體電路晶粒及模塑化合物上。第一重佈線結構包括第一金屬化圖案及第一介電層。第一金屬化圖案電性耦合至積體電路晶粒的主動側。第一金屬化圖案的至少一部分形成電感器。
本發明實施例可包括以下特徵中的一或多者。半導體封裝更包括導電連接件以及保護層。導電連接件在第一重佈線結構上。導電連接件電性耦合至第一金屬化圖案。保護層在第一重佈線結構上且鄰近導電連接件。保護層在電感器上且接觸電感器。在一些實施例中，保護層接觸並環繞導電連接件。在一些實施例中，保護層在整個第一重佈線結構上延伸。在一些實施例中，保護層具有與第一介電層不同的材料成分。在一些實施例中，第一重佈線結構的第一金屬化圖案的至少一部分形成變壓器。半導體封裝更包括第一穿孔。第一穿孔延伸穿過模塑化合物。第一穿孔電性耦合至第一重佈線結構的第一金屬化圖案。半導體封裝更包括第二重佈線結構。第二重佈線結構在積體電路晶粒下。第二重佈線結構包括第二金屬化圖案及第二介電層。第二金屬化圖案電性耦合至穿孔。第二金屬化圖案的至少一部分形成天線。半導體封裝更包括第二穿孔。第二穿孔延伸穿過模塑化合物。第二穿孔電性耦合至第一重佈線結構的第一金屬化圖案。第二穿孔是天線的一部分。半導體封裝更包括第一開口。第一開口延伸穿過第一介電層。第一開口鄰近第一重佈線結構中的電感器。
本發明實施例是一種形成半導體封裝的方法，方法包括以下步驟。使用模塑化合物包封積體電路晶粒。在積體電路晶粒及模塑化合物上形成第一介電層。在第一介電層中形成第一導通孔。第一導通孔電性耦合至積體電路晶粒的第一晶粒連接件。在第一介電層中形成第二導通孔。第二導通孔鄰近積體電路晶粒而在模塑化合物上。在第一介電層上形成第一金屬化圖案。在第一介電層、第一導通孔、第二導通孔及第一金屬化圖案上形成第二介電層。在第二介電層中形成第三導通孔。第三導通孔電性耦合至第一金屬化圖案，其中第一導通孔、第二導通孔、第一金屬化圖案及第三導通孔形成電感器或變壓器。在第三導通孔及第二介電層上形成絕緣層。絕緣層覆蓋第三導通孔。
本發明實施例可包括以下特徵中的一或多者。形成半導體封裝的方法更包括以下步驟。在第二介電層中形成凸塊下金屬。形成在凸塊下金屬上且電性耦合至凸塊下金屬的導電連接件。在形成半導體封裝的方法中，絕緣層接觸凸塊下金屬及導電連接件。在形成半導體封裝的方法中，絕緣層具有與第二介電層不同的材料成分。形成半導體封裝的方法更包括以下步驟。形成穿過第一介電層及第二介電層的開口。開口在第二導通孔與第三導通孔之間。形成半導體封裝的方法更包括以下步驟。在第一介電層、第一導通孔及第二導通孔上形成第三介電層。第二介電層在第三介電層上。第一金屬化圖案及第三導通孔直接上覆於第二導通孔上。形成半導體封裝的方法更包括以下步驟。在包封積體電路晶粒前，形成第一重佈線結構。第一重佈線結構包括第二金屬化圖案及第三介電層。在包封積體電路晶粒前，在第一重佈線結構的第二金屬化圖案上形成電性耦合至第一重佈線結構的第二金屬化圖案的第一電性連接件。模塑化合物包封第一電性連接件。積體電路晶粒及模塑化合物在第一重佈線結構上。第一電性連接件延伸穿過模塑化合物且電性耦合至第一金屬化圖案。
本發明實施例是一種形成半導體封裝的方法，方法包括以下步驟。形成第一封裝。第一封裝的形成包括以下步驟。在載體基底上形成電性連接件。使用黏著層將第一晶粒的背側貼合至載體基底。第一晶粒鄰近電性連接件。使用模塑化合物包封第一晶粒及電性連接件。在第一晶粒、模塑化合物及電性連接件上形成第一重佈線結構。電性連接件電性耦合至第一重佈線結構。第一重佈線結構包括第一積體組件。第一積體組件是電感器或變壓器。移除載體基底。
本發明實施例可包括以下特徵中的一或多者。形成半導體封裝的方法更包括以下步驟。使用第一組導電連接件將第二封裝結合至第一封裝。第二封裝靠近第一晶粒的背側。第二封裝包括一或多個晶粒。另外在形成半導體封裝的方法中，形成第一封裝更包括以下步驟。在形成電性連接件前，在載體基上形成第二重佈線結構。電性連接件電性耦合至第二重佈線結構，其中移除載體基底暴露出第二重佈線結構。在移除載體基底後，在被暴露出的第二重佈線結構上形成介電層。在介電層上形成導電元件，第二重佈線結構、介電層及導電元件形成貼片式天線。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各個態樣。熟習此項技術者應知，他們可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本揭露的精神及範圍，而且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
100‧‧‧載體基底
102‧‧‧離型層
104、136、140、160、210‧‧‧介電層
106‧‧‧金屬化圖案
108‧‧‧介電層
110‧‧‧背側重佈線結構
112‧‧‧電性連接件
114‧‧‧積體電路晶粒
116‧‧‧黏合劑
118‧‧‧半導體基底
120‧‧‧內連結構
122、142A、142B、162‧‧‧接墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
132‧‧‧前側重佈線結構
138‧‧‧金屬化圖案
144‧‧‧導電連接件
146‧‧‧保護層
150‧‧‧積體組件
150A‧‧‧電感器
150A’、150B、150B’‧‧‧變壓器
152‧‧‧橋接器
154‧‧‧開口
155‧‧‧埠
156‧‧‧凹槽
157‧‧‧射頻裝置開關
157-1、157-1’、157-2、157-2’‧‧‧電晶體
158、178‧‧‧開口
161‧‧‧金屬化圖案
164、314‧‧‧導電連接件
176‧‧‧膠帶
200‧‧‧第一封裝
202‧‧‧封裝
212‧‧‧輻射元件
214‧‧‧貼片式天線
216‧‧‧輻射天線
300‧‧‧第二封裝
302‧‧‧基底
303、304、402‧‧‧結合墊
306‧‧‧穿孔
308A、308B‧‧‧晶粒
310‧‧‧導線結合件
312‧‧‧模製材料
400‧‧‧封裝基底
600‧‧‧第一封裝區
602‧‧‧第二封裝區
A-A、B-B、C-C、D-D‧‧‧線
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1、圖2、圖3、圖4、圖5、圖6、圖7、圖8、圖9、圖10、圖11、圖12、圖13、圖14A、圖15、圖16、圖17、圖18A-1、圖18A-2、圖18B-1、圖18B-2、圖18B-3、圖18B-4、圖19、圖20、圖21及圖22示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖及平面圖。
圖14B-1、圖14B-2、圖14B-3、圖14B-4、圖14B-5、圖14B-6、圖14B-7及圖14B-8示出根據一些實施例的開關電路的示例性示意圖，其中電感器/變壓器耦合至開關電路的開關。
圖23、圖24、圖25及圖26示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖。
圖27示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖。
圖28示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖。
圖29、圖30、圖31、圖32、圖33及圖34示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖。
圖35、圖36及圖37示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖。
圖38示出根據一些實施例的形成封裝結構的過程期間的中間步驟的剖視圖。

Claims (20)

  1. 一種半導體封裝，包括： 積體電路晶粒，具有主動側及背側，所述背側與所述主動側相對； 模塑化合物，包封所述積體電路晶粒；以及 第一重佈線結構，上覆於所述積體電路晶粒及所述模塑化合物上，所述第一重佈線結構包括第一金屬化圖案及第一介電層，所述第一金屬化圖案電性耦合至所述積體電路晶粒的所述主動側，所述第一金屬化圖案的至少部分形成電感器。
  2. 如申請專利範圍第1項所述的裝置，更包括： 導電連接件，在所述第一重佈線結構上，所述導電連接件電性耦合至所述第一金屬化圖案；以及 保護層，在所述第一重佈線結構上且鄰近所述導電連接件，所述保護層在所述電感器上且接觸所述電感器。
  3. 如申請專利範圍第2項所述的裝置，其中所述保護層接觸並環繞所述導電連接件。
  4. 如申請專利範圍第2項所述的裝置，其中所述保護層在整個所述第一重佈線結構上延伸。
  5. 如申請專利範圍第2項所述的裝置，其中所述保護層具有的材料成分與所述第一介電層不同。
  6. 如申請專利範圍第1項所述的裝置，其中所述第一重佈線結構的所述第一金屬化圖案的至少一部分形成變壓器。
  7. 如申請專利範圍第1項所述的裝置，更包括： 第一穿孔，延伸穿過所述模塑化合物，所述第一穿孔電性耦合至所述第一重佈線結構的所述第一金屬化圖案。
  8. 如申請專利範圍第7項所述的裝置，更包括： 第二重佈線結構，在所述積體電路晶粒下，所述第二重佈線結構包括第二金屬化圖案及第二介電層，所述第二金屬化圖案電性耦合至所述穿孔，所述第二金屬化圖案的至少一部分形成天線。
  9. 如申請專利範圍第7項所述的裝置，更包括： 第二穿孔，延伸穿過所述模塑化合物，所述第二穿孔電性耦合至所述第一重佈線結構的所述第一金屬化圖案，所述第二穿孔是天線的一部分。
  10. 如申請專利範圍第1項所述的裝置，更包括： 第一開口，延伸穿過所述第一介電層，所述第一開口鄰近所述第一重佈線結構中的所述電感器。
  11. 一種形成半導體封裝的方法，包括： 使用模塑化合物包封積體電路晶粒； 在所述積體電路晶粒及所述模塑化合物上形成第一介電層； 在所述第一介電層中形成第一導通孔，所述第一導通孔電性耦合至所述積體電路晶粒的第一晶粒連接件； 在所述第一介電層中形成第二導通孔，所述第二導通孔鄰近所述積體電路晶粒而在所述模塑化合物上； 在所述第一介電層上形成第一金屬化圖案； 在所述第一介電層、所述第一導通孔、所述第二導通孔及所述第一金屬化圖案上形成第二介電層； 在所述第二介電層中形成第三導通孔，所述第三導通孔電性耦合至所述第一金屬化圖案，其中所述第一導通孔、所述第二導通孔、所述第一金屬化圖案及所述第三導通孔形成電感器或變壓器；以及 在所述第三導通孔及所述第二介電層上形成絕緣層，所述絕緣層覆蓋所述第三導通孔。
  12. 如申請專利範圍第11項所述的方法，更包括： 在所述第二介電層中形成凸塊下金屬；以及 形成在所述凸塊下金屬上且電性耦合至所述凸塊下金屬的導電連接件。
  13. 如申請專利範圍第12項所述的方法，其中所述絕緣層接觸所述凸塊下金屬及所述導電連接件。
  14. 如申請專利範圍第12項所述的方法，其中所述絕緣層具有的材料成分與所述第二介電層不同。
  15. 如申請專利範圍第11項所述的方法，更包括： 形成穿過所述第一介電層及所述第二介電層的開口，所述開口在所述第二導通孔與所述第三導通孔之間。
  16. 如申請專利範圍第11項所述的方法，更包括： 在所述第一介電層、所述第一導通孔及所述第二導通孔上形成第三介電層，所述第二介電層在所述第三介電層上，所述第一金屬化圖案及所述第三導通孔直接上覆於所述第二導通孔上。
  17. 如申請專利範圍第11項所述的方法，更包括： 在包封所述積體電路晶粒前，形成第一重佈線結構，所述第一重佈線結構包括第二金屬化圖案及第三介電層；以及 在包封所述積體電路晶粒前，在所述第一重佈線結構的所述第二金屬化圖案上形成電性耦合至所述第一重佈線結構的所述第二金屬化圖案的第一電性連接件，所述模塑化合物包封所述第一電性連接件，所述積體電路晶粒及所述模塑化合物位於所述第一重佈線結構上，所述第一電性連接件延伸穿過所述模塑化合物且電性耦合至所述第一金屬化圖案。
  18. 一種形成半導體封裝的方法，包括： 形成第一封裝，包括： 在載體基底上形成電性連接件； 使用黏著層將第一晶粒的背側貼合至所述載體基底，所述第一晶粒鄰近所述電性連接件； 使用模塑化合物包封所述第一晶粒及所述電性連接件； 在所述第一晶粒、所述模塑化合物及所述電性連接件上形成第一重佈線結構，所述電性連接件電性耦合至所述第一重佈線結構，所述第一重佈線結構包括第一積體組件，所述第一積體組件是電感器或變壓器；以及 移除所述載體基底。
  19. 如申請專利範圍第18項所述的方法，更包括： 使用第一組導電連接件將第二封裝結合至所述第一封裝，所述第二封裝靠近所述第一晶粒的所述背側，所述第二封裝包括一或多個晶粒。
  20. 如申請專利範圍第18項所述的方法，其中形成所述第一封裝更包括： 在形成所述電性連接件前，在所述載體基底上形成第二重佈線結構，所述電性連接件電性耦合至所述第二重佈線結構，其中移除所述載體基底暴露出所述第二重佈線結構； 在移除所述載體基底後，在被暴露出的所述第二重佈線結構上形成介電層；以及 在所述介電層上形成導電元件，所述第二重佈線結構、所述介電層及所述導電元件形成貼片式天線。
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