TWI760725B - 半導體裝置和製造半導體裝置的方法 - Google Patents

半導體裝置和製造半導體裝置的方法 Download PDF

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TWI760725B
TWI760725B TW109112397A TW109112397A TWI760725B TW I760725 B TWI760725 B TW I760725B TW 109112397 A TW109112397 A TW 109112397A TW 109112397 A TW109112397 A TW 109112397A TW I760725 B TWI760725 B TW I760725B
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dielectric
section
conductor
conductive
terminal
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TW109112397A
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TW202114092A (zh
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金權泰
韓意書
新及補
李泰勇
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美商艾馬克科技公司
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Abstract

在一個實例中，一種半導體裝置可以包括：（a）電子裝置，所述電子裝置包括裝置頂部側、與所述裝置頂部側相對的裝置底部側，以及在所述裝置頂部側與所述裝置底部側之間的裝置側壁；（b）第一導體，所述第一導體包括在所述裝置側壁上的第一導體側區段、在所述裝置頂部側上並且耦合到所述第一導體側區段的第一導體頂部區段，以及耦合到所述第一導體側區段的第一導體底部區段；以及（c）保護材料，所述保護材料覆蓋所述第一導體和所述電子裝置。所述第一導體頂部區段的下表面可以高於所述裝置頂部側，並且所述第一導體底部區段的上表面可以低於所述裝置頂部側。本文中也揭示內容其它實例和相關方法。

Description

半導體裝置和製造半導體裝置的方法
本揭示內容總體上涉及電子裝置，並且更明確地說涉及半導體裝置和製造半導體裝置的方法。
先前的半導體封裝件和形成半導體封裝件的方法不夠好，例如，使得成本過高、可靠性降低、性能相對較低或封裝尺寸過大。通過將常規和傳統方法與本揭示內容進行比較並且參考附圖，本領域的技術人員將清楚此類方法的其它局限性和缺點。
根據本發明的一態樣，一種半導體裝置，其包括：電子裝置，所述電子裝置包括：裝置頂部側，所述裝置頂部側包括裝置第一端子；裝置底部側，所述裝置底部側與所述裝置頂部側相對；以及裝置第一側壁，所述裝置第一側壁在所述裝置頂部側與所述裝置底部側之間；以及基板，所述基板包括：介電材料，所述介電材料包括：介電質頂部區段，所述介電質頂部區段在所述裝置頂部側之上，其中所述介電質頂部區段包括在所述裝置第一端子之上的介電質第一開口；介電質側區段，所述介電質側區段在所述裝置第一側壁之上並且與所述介電質頂部區段相連；以及介電質底部區段，所述介電質底部區段包括與所述裝置底部側大致上共平面並且與所述介電質側區段相連的下表面；以及第一導電材料，所述第一導電材料包括：第一導電頂部區段，所述第一導電頂部區段在所述介電質頂部區段之上並且穿過所述介電質第一開口耦合到所述裝置第一端子；第一導電側區段，所述第一導電側區段在所述介電質側區段之上並且與所述第一導電頂部區段相連；以及第一導電底部區段，所述第一導電底部區段在所述介電質底部區段之上並且與所述第一導電側區段相連。
根據本發明的另一態樣，一種半導體裝置，其包括：電子裝置，所述電子裝置包括：裝置頂部側；裝置底部側，所述裝置底部側與所述裝置頂部側相對；以及裝置側壁，所述裝置側壁在所述裝置頂部側與所述裝置底部側之間；第一導體，所述第一導體包括：第一導體側區段，所述第一導體側區段在所述裝置側壁上；第一導體頂部區段，所述第一導體頂部區段在所述裝置頂部側上並且耦合到所述第一導體側區段；以及第一導體底部區段，所述第一導體底部區段耦合到所述第一導體側區段；以及保護材料，所述保護材料覆蓋所述第一導體和所述電子裝置；其中：所述第一導體頂部區段的下表面高於所述裝置頂部側；並且所述第一導體底部區段的上表面低於所述裝置頂部側。
根據本發明的又另一態樣，一種方法，其包括：提供電子裝置，所述電子裝置包括：裝置頂部側，所述裝置頂部側包括裝置第一端子；裝置底部側，所述裝置底部側與所述裝置頂部側相對；以及裝置第一側壁，所述裝置第一側壁在所述裝置頂部側與所述裝置底部側之間；以及提供介電質，所述介電質包括：介電質頂部區段，所述介電質頂部區段在所述裝置頂部側之上，其中所述介電質頂部區段包括在所述裝置第一端子之上的介電質第一開口；介電質側區段，所述介電質側區段在所述裝置第一側壁之上並且與所述介電質頂部區段相連；以及介電質底部區段，所述介電質底部區段與所述介電質側區段相連；其中：所述介電質底部區段的下表面與所述裝置底部側大致上共平面；並且所述介電質底部區段的上表面低於所述介電質頂部區段的上表面。
在一個實例中，一種半導體裝置可以包括：（a）電子裝置，所述電子裝置包括包含裝置第一端子的裝置頂部側、與所述裝置頂部側相對的裝置底部側，以及在所述裝置頂部側與所述裝置底部側之間的裝置第一側壁；以及（b）基板。所述基板可以包括介電材料，所述介電材料包括：（a）介電質頂部區段，所述介電質頂部區段在所述裝置頂部側之上，其中所述介電質頂部區段包括在所述裝置第一端子之上的介電質第一開口；（b）介電質側區段，所述介電質側區段在所述裝置第一側壁之上並且與所述介電質頂部區段相連；以及（c）介電質底部區段，所述介電質底部區段包括與所述裝置底部側大致上共平面並且與所述介電質側區段相連的下表面。所述基板還可以包括第一導電材料，所述第一導電材料包括：（a）第一導電頂部區段，所述第一導電頂部區段在所述介電質頂部區段之上並且穿過所述介電質第一開口耦合到所述裝置第一端子；（b）第一導電側區段，所述第一導電側區段在所述介電質側區段之上並且與所述第一導電頂部區段相連；以及（c）第一導電底部區段，所述第一導電底部區段在所述介電質底部區段之上並且與所述第一導電側區段相連。
在一個實例中，一種半導體裝置可以包括：（a）電子裝置，所述電子裝置包括裝置頂部側、與所述裝置頂部側相對的裝置底部側，以及在所述裝置頂部側與所述裝置底部側之間的裝置側壁；（b）第一導體，所述第一導體包括在所述裝置側壁上的第一導體側區段、在所述裝置頂部側上並且耦合到所述第一導體側區段的第一導體頂部區段，以及耦合到所述第一導體側區段的第一導體底部區段；以及（c）保護材料，所述保護材料覆蓋所述第一導體和所述電子裝置。所述第一導體頂部區段的下表面可以高於所述裝置頂部側，並且所述第一導體底部區段的上表面可以低於所述裝置頂部側。
在一個實例中，一種方法可以包括：（a）提供電子裝置，所述電子裝置包括包含裝置第一端子的裝置頂部側、與所述裝置頂部側相對的裝置底部側，以及在所述裝置頂部側與所述裝置底部側之間的裝置第一側壁；以及（b）提供包括在所述裝置頂部側之上的介電質頂部區段的介電質，其中所述介電質頂部區段包括在所述裝置第一端子之上的介電質第一開口、在所述裝置第一側壁之上並且與所述介電質頂部區段相連的介電質側區段，以及與所述介電質側區段相連的介電質底部區段。所述介電質底部區段的下表面可與所述裝置底部側大致上共平面。所述介電質底部區段的上表面可以低於所述介電質頂部區段的上表面。
本揭示內容中包含其它實例。在圖式、請求項和/或本揭示內容的描述中可以找到此類實例。
圖1示出示例半導體裝置100的橫截面圖。在圖1中示出的實例中，半導體裝置100可以包括電子裝置110、電子構件130、基板120和140、互連件150和170以及囊封物160。
電子裝置110可以包括端子111。端子111可以形成在電子裝置110的頂表面上。基板120可以包括介電結構121和導電結構122。導電結構122可電連接到電子裝置110的端子111。
電子構件130可以包括端子131。端子131可以形成在電子構件130的底表面上。基板140可以包括介電結構141和導電結構142。導電結構142可以電連接到電子構件130的端子131。基板140可以形成在電子構件130的底表面上。
互連件150可以由導電材料形成並且可以電連接導電結構142和導電結構122。互連件170可以由導電材料形成並且可以形成在基板140的底表面上。互連件170可電連接到導電結構142。囊封物160可插入於基板120的頂表面與基板140的底表面之間。
基板120和140、互連件150和170以及囊封物160可以包括或被稱作半導體封裝件101，它可以為電子裝置110和電子構件130提供保護以免受外部構件及/或環境暴露影響。另外，半導體封裝件101可提供外部電構件與端子111和131之間的電耦合。
圖2A到2H示出製造半導體裝置100的示例方法的橫截面圖。
圖2A示出在早期製造階段的半導體裝置100的橫截面圖。在圖2A中示出的實例中，電子裝置110可以安裝在載體10的頂表面10a上。此處，可暴露載體10的頂表面10a的一部分。載體10的實例可以包括矽、低等級矽、玻璃、碳化矽、藍寶石、石英、陶瓷、金屬氧化物、金屬等。
電子裝置110的裝置底部側110b可以例如在裝置底部側110b與頂表面10a之間使用黏合劑而緊固到載體10的頂表面10a上。在一些實例中，黏合劑可為液相環氧黏合劑、黏合膜或黏合帶。
在一些實例中，電子裝置110可以包括或被稱作電子構件、半導體晶粒或半導體封裝件。電子裝置110可以包括例如半導體材料，如矽（Si）。電子裝置110可以包括設置在其裝置頂部側110a上的多個端子111。電子裝置110可以包括被動電子電路和/或主動電子電路，如電晶體。電子裝置110可以具有在約75 μm到約775 μm範圍內的厚度。載體10可以在以下製造製程中促進電子裝置110的處置並且可以保護電子裝置110。
在一些實例中，端子111可以包括或被稱作晶粒墊。端子111可以包括例如導電材料，如金屬材料、鋁、銅、鋁合金或銅合金。
圖2B示出在後期製造階段的半導體裝置100的橫截面圖。在圖2B中示出的實例中，可以形成大致上均勻厚度的介電結構121用來遮蓋載體10的頂表面10a和電子裝置110的暴露表面。介電結構121包括在裝置頂部側110a之上的大致上水平的介電質頂部區段121、在載體10或裝置底部平面110p之上延伸的大致上水平的介電質底部區段121b，以及在裝置側壁110c之上的大致上垂直的介電質側區段121c。裝置底部平面110p可由裝置底部側110b限定。介電質底部區段121b的上表面可以由介電質頂部區段121a暴露。介電質底部區段121b的下表面可以與裝置底部側110b大致上共平面。介電質底部區段121b的上表面可以低於介電質頂部區段121a的上表面，或低於介電質頂部區段121a的下表面。介電質頂部區段121a和介電質底部區段121b可各自與介電質側區段121c連接或相連。介電質121可以與載體10和電子裝置110保形的方式施加或形成，以便獲取或符合電子裝置110和載體10的輪廓或組合形狀。
介電結構121可以具有在5 μm到10 μm範圍內的厚度。在一些實例中，介電結構121可以包括或被稱作介電質、介電層、介電材料、非導電材料或絕緣體。介電結構121可以包括例如絕緣材料，如聚合物、聚醯亞胺（PI）、苯並環丁烯（BCB）、聚苯並噁唑（PBO）、雙馬來醯亞胺三嗪（BT）、模製材料、酚醛樹脂、環氧樹脂、矽酮或丙烯酸酯聚合物。形成介電結構121的實例可以包括使用旋塗、噴塗、印刷、物理氣相沉積（PVD）、化學氣相沉積（CVD）、金屬有機化學氣相沉積（MOCVD）、原子層沉積（ALD）、低壓化學氣相沉積（LPCVD）、電漿增強化學氣相沉積（PECVD）、薄片層壓或蒸發。
圖2C示出在後期製造階段的半導體裝置100的橫截面圖。在圖2C中示出的實例中，暴露端子111的開口121x可通過圖案化介電結構121形成。暴露載體10的頂表面10a的一部分的開口121y也可在此階段形成。例如，在形成暴露介電結構121的對應於開口121x和開口121y的區的遮罩圖案之後，可例如通過蝕刻去除介電結構121的此類暴露區，由此形成開口121x和開口121y。光阻劑可用作遮罩圖案。
在一些實例中，開口121x和121y可以包括或被稱作孔洞或通孔。開口121x可以具有比端子111小的周長。相應地，介電結構121可覆蓋端子111的外部周邊的部分或保持在端子111的外部周邊的部分之上。開口121y可以具有在約10 μm到約100 μm範圍內的平面尺寸。
圖2D示出在後期製造階段的半導體裝置100的橫截面圖。在圖2D中示出的實例中，可以形成覆蓋開口121x、開口121y和介電結構121的暴露表面的導電結構122。
導電結構122可以包括或被稱作一個或多個導電材料、導體或導電層、圖案或跡線，如導體122x、122y和122z。在本實例中，導體122x、122y和122z可以由單個導電層形成，此導電層可通過一個或多個導電子層限定，例如，由在晶種子層之上的主要子層限定。導體122x、122y或122z可以彼此類似，並且可以包括鄰近於電子裝置110的相應側的相應導體頂部區段、導體側區段122c或導體底部區段122b。導體122x和122y在電子裝置110的裝置頂部側110a之上延伸，並且可以分別具有連接到通過相應開口121x暴露的相應端子111的第一端子部分。導體122x也具有通過介電結構121的相應開口121y暴露和/或延伸的第二端子部分。導體122x的第一和第二端子部分彼此通過導體122x的導電路徑連接。導體122x在介電結構121上並且包括在介電質頂部區段121a和裝置頂部側110a之上大致上水平延伸的導體頂部區段122a、在介電質側區段121c和裝置側壁110c之上大致上垂直延伸的導體側區段122c，以及在介電質底部區段121b之上和在載體10之上大致上水平延伸超過電子裝置110的周邊的導體底部區段122b。導體頂部區段122a和導體底部區段122b可各自與導體側區段122c連接或相連。在一些實例中，導體側區段122c可大致上正交於導體頂部區段122a和導體底部區段122b。在一些實例中，導體頂部區段122a和導體底部區段122b大致上不與彼此重疊。在一些實例中，與導體頂部區段122a的下表面相比，導體底部區段122b的上表面可能更接近於裝置底部平面110p。在一些實例中，導體頂部區段122a的下表面可以高於裝置頂部側110a，並且導體底部區段122b的上表面可以大致上平行於導體頂部區段122a的下表面但低於裝置頂部側110a。
導體122z同樣延伸並且具有在電子裝置110的裝置頂部側110a之上的第一端子部分，但如本實例中所示出，導體122z不必連接到電子裝置110或任何端子111。導體122z也具有通過介電結構121的相應開口121y暴露和/或延伸的第二端子部分。導體122z的第一和第二端子部分通過導體122z的導電路徑彼此連接，其中此類導電路徑在介電結構121上，並且在電子裝置110的裝置頂部側110a之上大致上水平地延伸，在電子裝置110的裝置側壁110c之上大致上垂直地延伸，並且在載體10之上大致上水平地延伸到超過電子裝置110的周邊。
儘管為簡單起見用單個導電結構122和單個介電結構121說明本實例，但此類元件可分別表示可彼此交替堆疊的一個或多個導電結構或層和/或一個或多個介電結構或層。在相同或其它實例中，導電結構122的一個或多個部分可以具有或可以形成有彼此堆疊的一個或多個導電材料的一個或多個層。
導電結構122可以具有在約3 μm到約10 μm範圍內的厚度。在一些實例中，導電結構122可以包括導電材料，例如鈦（Ti）、鈦-鎢（TiW）、銅（Cu）或者Ti、TiW或Cu的合金。
形成導電結構122的實例可以包括使用物理氣相沉積（PVD）、化學氣相沉積（CVD）、原子層沉積（ALD）、電漿氣相沉積、無電鍍覆或電解鍍覆。在一些實例中，PVD可以包括或被稱作濺射。
導電結構122的導體122x、122y或122z，或它們相應的導體頂部區段122a、導體側區段122c或導體底部區段122b可同時或者以與載體10和電子裝置110保形的方式施加或形成，以便獲取或符合介電質121、電子裝置110或載體10的輪廓或組合形狀。
圖2E示出在後期製造階段的半導體裝置100的橫截面圖。在圖2E中示出的實例中，電子構件130可安裝在導電結構122上，在電子構件130的底部側130b上具有基板140和內部互連件150。電子構件130可以包括或者被稱作電子裝置、半導體晶粒、半導體封裝件和/或插入件。電子構件130可以包括例如半導體材料，如矽（Si）。電子構件130可包括設置在其底部側130b上的多個端子131。電子構件130可以包括被動電子電路和/或主動電子電路，如電晶體。電子構件130可以具有在約75 μm到約775 μm範圍內的厚度。
另外可在電子構件130的底部側130b上設置基板140和互連件150。基板140可以包括覆蓋電子構件130的底部側130b並暴露端子131的介電結構141，以及電連接到通過介電結構141暴露的端子131的導電結構142。在一些實例中，基板140、介電結構141和/或導電結構142可類似於基板120、介電結構121和/或導電結構122。導電結構142可以具有在電子構件130的底部側130b之上延伸的多個導體、圖案或跡線。例如，構件導體142x、142y和142z中的每一個可以具有與對應互連件150耦合的相應第一端子部分、耦合到通過介電結構141暴露的電子構件130的對應端子131的相應第二端子部分，以及將導體142x、142y和142z中的每一個的對應第一及第二端子部分連接在一起的相應導電路徑。在本實例中，相應互連件150同時將導體142x耦合到導體122x、將導體142y耦合到導體122y，並且將導體142z耦合到導體122z。例如，互連件1501耦合到導體頂部區段122a，並且通過構件導體142x耦合到構件端子1311。另外，構件端子1311通過互連件1501、導體頂部區段122a和介電質開口121x耦合到裝置端子1111。在本實例中，構件介電結構141位於構件底部側130b上，從而使構件端子1311暴露，並且導體142x在構件介電結構141之上從構件端子1311側向地延伸，使得構件端子1311相對於互連件1501側向地偏移。此外，內部互連件1501沿著導體頂部區段122a耦合，使得它相對於裝置端子1111側向地偏移。在一些實例中，內部互連件150可通過相應端子（如形成於此類相應導體上的襯墊和/或凸點下金屬化（UBM））耦合到導電結構142的相應導體和/或導電結構122的相應導體。
連同介電結構141一起構成基板140的導電結構142可為用於重新分佈電子構件130的端子131的電連接的佈線。導電結構142可以具有在約3 μm到約10 μm範圍內的厚度，並且介電結構141可以具有在約5 μm到約10 μm範圍內的厚度。
介電結構141可以包括或被稱作例如一個或多個介電層、非導電材料或絕緣體。介電結構141可以包括例如絕緣材料，如聚合物、聚醯亞胺（PI）、苯並環丁烯（BCB）、聚苯並噁唑（PBO）、雙馬來醯亞胺三嗪（BT）、模製材料、酚醛樹脂、環氧樹脂、矽酮或丙烯酸酯聚合物。形成介電結構141的實例可以包括使用旋塗、噴塗、印刷、物理氣相沉積（PVD）、化學氣相沉積（CVD）、金屬有機化學氣相沉積（MOCVD）、原子層沉積（ALD）、低壓化學氣相沉積（LPCVD）、電漿增強化學氣相沉積（PECVD）、薄片層壓或蒸發。另外，可以通過蝕刻其中形成電子構件130的端子131的部分來暴露介電結構141。
在一些實例中，導電結構142可以包括導電材料，例如鈦（Ti）、鈦-鎢（TiW）、銅（Cu），或Ti、TiW或Cu的合金。形成導電結構142的實例可以包括使用物理氣相沉積（PVD）、化學氣相沉積（CVD）、原子層沉積（ALD）、電漿氣相沉積、無電鍍覆或電解鍍覆。在一些實例中，PVD可以包括或被稱作濺射。另外，可以使用遮罩圖案來圖案化導電結構142以提供分別電連接到端子131的多個圖案。
互連件150可以電連接到導電結構142的底表面142b。互連件150可以設定成同樣尺寸。互連件150可以包括錫（Sn）、銀（Ag）、鉛（Pb）、銅（Cu）、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。在一些實例中，互連件150可包括焊料球，和/或具有被焊料覆蓋的固體金屬芯的金屬芯球。在一些實例中，互連件150可以包括金屬柱，如銅柱，所述金屬柱可放置或形成於導電結構142上，並且所述金屬柱可以具有焊料尖端或末端。互連件150可以具有在約5 μm到約100 μm範圍內的尺寸。
形成互連件150的實例包含使用球降（ball drop）製程、網版印刷製程或電鍍製程。在一些實例中，包括焊料的導電材料可以使用焊料球降製程形成於導電結構142的底表面上。此處，導電結構142的底表面142b可設置成面朝上。可以使用回焊製程將電子構件130和基板140加熱到預定溫度，並且互連件150的形狀在回焊期間可以變化。
在一些實例中，可以使用大規模回焊製程、熱壓製程或雷射接合製程將具有基板140和互連件150的電子構件130電連接到基板120的導電結構122。互連件150可以插入於導電結構122與導電結構142之間用來電連接基板120和基板140。互連件150可以通過基板120和基板140在電子裝置110與電子構件130之間傳送電流或信號。另外，一個或多個互連件150可以連接到未電連接到電子裝置110的導體，如導體122z。在一些實例中，互連件150可通過基板140和基板120將電子構件130電連接到電子裝置110。在相同或其它實例中，一個或多個互連件150可將電子構件130電連接到導電結構122的導體，所述導體延伸超過電子裝置110的周邊並且通過介電結構121的開口121y來暴露。
在一些實例中，可以用作半導體裝置100的部分的基板中的一個或多個（如基板140或120）可為重新分佈層（“RDL”）基板。RDL基板可以包括（a）可以在將與RDL基板電耦合的電子裝置之上逐層形成或（b）可以在可以在將電子裝置和RDL基板耦合在一起之後完全去除或至少部分地去除的載體之上逐層形成的一個或多個導電重新分佈層和一個或多個介電層。RDL基板可以在圓形晶圓上以晶圓級製程逐層製造為晶圓級基板，和/或在矩形或方形面板載體上以面板級製程逐層製造為面板級基板。RDL基板可以以加成堆積製程形成，此加成堆積製程可以包含一個或多個介電層與限定相應導電重新分佈圖案或跡線的一個或多個導電層交替堆疊，所述導電重新分佈圖案或跡線被配置成共同（a）將電跡線扇出電子裝置的佔用空間外，和/或（b）將電跡線扇入電子裝置的佔用空間內。可以使用電鍍製程或無電鍍覆製程等鍍覆製程來形成導電圖案。導電圖案可以包括導電材料，例如銅或其它可鍍覆金屬。可以使用光圖案化製程，例如光微影製程和用於形成光微影遮罩的光阻劑材料來製作導電圖案的位置。RDL基板的介電層可以利用可以包含光微影遮罩的光圖案化製程來圖案化，通過所述光微影遮罩，光暴露於光圖案期望的特徵，如介電層中的通孔。介電層可以由聚醯亞胺（PI）、苯並環丁烯（BCB）或聚苯並噁唑（PBO）等可光限定（photo-definable）的有機介電材料製成。此類介電材料可以以液體形式旋塗或以其它方式塗覆，而不是以預先形成的膜的形式附接。為了允許期望的光限定特徵適當地形成，此類可光限定的介電材料可以省略結構增強劑，或者可以是無填料的，並且沒有可能會干擾來自光圖案化製程的光的股線、織造物或其它顆粒。在一些實例中，無填料介電材料的此類無填料特性可以使得所得的介電層的厚度減小。儘管上文描述的可光限定的介電材料可以是有機材料，但是在其它實例中，RDL基板的介電材料可以包括一個或多個無機介電層。一個或多個無機介電層的一些實例可以包括氮化矽（Si 3 N 4 ）、氧化矽（SiO 2 ）和/或SiON。所述一個或多個無機介電層可以不是通過使用光限定的有機介電材料而是通過使用氧化或氮化製程生長無機介電層來形成。此類無機介電層可以是無填料的，並且沒有股線、織造物或其它不同的無機顆粒。在一些實例中，RDL基板可以省略永久性芯結構或載體，例如包括雙馬來醯亞胺三嗪（BT）或FR4的介電材料，並且這些類型的RDL基板可以被稱為無芯基板。本揭示內容中的其它基板也可以包括RDL基板。
在一些實例中，可以用作半導體裝置100的部分的基板中的一個或多個基板，如基板140，可為預先形成的基板。預先形成的基板可以在附接到電子裝置上之前製造並且可以包括在相應導電層之間的介電層。導電層可以包括銅並且可以使用電鍍製程形成。介電層可以是可以以預先形成的膜的形式而不是以液體的形式附接的相對較厚的不可光限定層，並且可以包含具有用於剛性和/或結構性支撐的股線、織造物和/或其它無機顆粒等填料的樹脂。由於介電層是不可光限定的，因此可以通過使用鑽孔或雷射來形成通孔或開口等特徵。在一些實例中，介電層可以包括預浸材料或味之素堆積膜（ABF）。預先形成的基板可以包含永久性芯結構或載體，例如包括雙馬來醯亞胺三嗪（BT）或FR4的介電材料，並且介電層和導電層可以形成於永久性芯結構上。在其它實例中，預先形成的基板可以是省略永久性芯結構的無芯基板，並且介電層和導電層可以形成於犧牲載體上，此犧牲載體在形成介電層和導電層之後並且在附接到電子裝置之前被去除。預先形成的基板可以被稱為印刷電路板（PCB）或層壓基板。此類預先形成的基板可以通過半加成製程或改進的半加成製程來形成。本揭示內容中的其它基板也可以包括預先形成的基板。
圖2F示出在後期製造階段的半導體裝置100的橫截面圖。在圖2F所示出的實例中，可以形成覆蓋基板120的頂部、半導體構件130和基板140的底部、電子裝置110以及互連件150的囊封物160。至少部分地通過囊封物160形成電子裝置110的包含裝置側壁110c的側壁的邊界。可提供囊封物160來完全填充基板120與基板140之間的區域。
在一些實例中，囊封物160可以包括非導電材料、樹脂、聚合物複合材料、具有填料的聚合物、環氧樹脂、環氧樹脂、具有如二氧化矽或其它無機材料的填料的環氧丙烯酸酯、矽酮樹脂或浸樹脂B態預浸膜。
形成囊封物160的實例可以包括壓縮模製、轉移模製、液體囊封物模製、真空層壓、膏印刷或膜輔助模製。在一些實例中，囊封物160可以包括或被稱作保護材料或模製化合物。囊封物160可斷開基板120、基板140以及互連件150彼此的電連接，借此保護基板120、基板140以及互連件150免受外部周邊的影響。
圖2G示出在後期製造階段的半導體裝置100的橫截面圖。在2G中示出的實例中，黏附到電子裝置110的裝置底部側110b的載體10可以被去除，使得電子裝置110的裝置底部側110b和基板120的底表面被暴露。當去除載體10時，可暴露形成於載體10的頂表面10a上的介電結構121的底表面121b。另外，如果去除載體10，則形成於載體10的頂表面10a上的導電結構122也可通過介電結構121的開口121y來暴露。未電連接到電子裝置110的導電結構122的導體，如導體122z，也可通過開口121y來暴露。
可通過一般研磨或化學蝕刻去除載體10。或者，載體10也可通過使用UV輻射或雷射的剝離製程來去除。
圖2H示出在後期製造階段的半導體裝置100的橫截面圖。在圖2H中示出的實例中，可在通過開口121y暴露的導電結構122上設置互連件170。
互連件170可電連接到導電結構122的底表面。在一些實例中，互連件170可通過導電結構122電連接到電子裝置110。在一些實例中，互連件170可通過導電結構122、互連件150以及導電結構142電連接到電子構件130。互連件170可被稱作外部互連件，允許從半導體裝置100到外部裝置或構件（如印刷電路板或基板）的外部連接。
互連件170可以包括錫（Sn）、銀（Ag）、鉛（Pb）、銅（Cu）、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。形成互連件170的實例包含使用球降製程、網版印刷製程或電鍍製程。在一些實例中，包括焊料的導電材料可以使用焊料球降製程形成於導電結構122的底表面122b上。導電結構122的底表面122b可以在這個階段設置成面朝上。可以使用回焊製程將半導體裝置100加熱到預定溫度，並且互連件170的形狀在回焊製程期間可以變化。電互連件170可以包括或被稱作導電球（如焊料球）、導電柱（如銅柱），或具有形成於銅柱上的焊料蓋的導電柱。互連件170可以具有在約60 μm到約150 μm範圍內的尺寸。
互連件170可允許針對和/或來自半導體裝置100的一個或多個構件的外部存取，所述一個或多個構件如電子裝置110和/或電子構件130。
例如，在鄰近於電子裝置110的側壁110c的第一路徑中，在基板120底部上的互連件1701通過包含導體122x（包含導體底部區段122b、導體側區段122c以及導體頂部區段122a）的配線(route)、通過互連件1501以及通過構件導體142x耦合到電子構件130的構件端子1311。同樣，在本實例中，在基板120底部上的互連件1701也沿著第一路徑的至少一部分，通過包含導體122x（包含導體底部區段122b、鄰近於側壁110c的導體側區段122c，以及導體頂部區段122a）的配線耦合到電子裝置130的裝置端子1111。
類似地，在鄰近於電子裝置110的側壁110d的第二路徑中，在基板120的底部上的互連件1702通過包含導體122z（和其相應的導體頂部區段122a、導體側區段122c以及導體底部區段122c）的配線、通過互連件1502以及通過構件導體142z耦合到電子構件130的構件端子1312。
在分割成單個單元之後，半導體裝置100呈現其最終形式。此類分割可例如通過進行鋸割以限定半導體裝置100的側壁來實現。在一些實例中，此類分割可限定半導體裝置100的不同構件的共平面部分。例如，電子構件130的構件側壁130c可以與囊封物160的側壁大致上共平面。在一些實例中，在圖2H中示出為介電質底部區段121b的外端或側壁的基板120的側壁由囊封物160的側壁暴露並且與所述側壁大致上共平面。在一些實例中，如圖2H中所示出，導體底部區段122b的外部導體端點並不由囊封物160暴露，而是被所述囊封物覆蓋。與導電底部區段122b的任何其它點相比，導體底部區段122b的此類端點可能最接近囊封物160的側壁。可能存在導體底部區段122b的外端可以進一步延伸並且因此以與囊封物160的側壁共平面的形式暴露的其它實例。
通過上文對於互連導電結構122和142的不同導體所描述的佈置，可以實現半導體裝置100的若干信號路徑。例如，包含導體122x和142x的路徑允許電子裝置110和電子構件130彼此電連接並電連接到對應互連件170，從而斷開半導體裝置100的外部連接。包含導體122y和142y的路徑允許在電子裝置110與電子構件130之間的直接內部連接。包含導體122z和142z的路徑允許電子裝置130電連接到對應的互連件170，使得在電子裝置100之上跨越但電力地繞過電子裝置100，從而斷開半導體裝置100的連接。相應地，可以在不需要額外形成專用垂直通孔的情況下，實現頂部電子裝置130與外部互連件170之間的電耦合，所述通孔原本必須從電子裝置130與外部互連件170之間的囊封物160頂部完全延伸到底部。
本揭示內容包含對某些實例的引用，然而，本領域的技術人員應理解的是，在不脫離本揭示內容的範圍的情況下，可以作出各種改變並且可以取代等同物。另外，在不脫離本揭示內容的範圍的情況下可以對揭示內容的實例作出修改。因此，並不希望本揭示內容受限於所揭示內容的實例，而是希望本揭示內容將包含落入所附請求項的範圍內的所有實例。
10:載體 10a:頂表面 100:半導體裝置 101:半導體封裝件 110:電子裝置 110a:裝置頂部側 110b:裝置底部側 110c:裝置側壁 110d:側壁 110p:裝置底部平面 111:端子 120:基板 121:介電結構 121a:介電質頂部區段 121b:介電質底部區段 121c:介電質側區段 121x:開口 121y:開口 122:導電結構 122a:導體頂部區段 122b:導體底部區段 122c:導體側區段 122x:導體 122y:導體 122z:導體 130:電子構件 130b:底部側 130c:構件側壁 131:端子 140:基板 141:介電結構 142:導電結構 142b:底表面 142x:導體 142y:導體 142z:導體 150:互連件 160:囊封物 170:互連件 1111:裝置端子 1311:構件端子 1312:構件端子 1501:互連件 1502:互連件 1701:互連件 1702:互連件
[圖1]示出示例半導體裝置的橫截面圖。
[圖2A到2H]示出製造示例半導體裝置的示例方法的橫截面圖。
以下論述提供半導體裝置和製造半導體裝置的方法的各種實例。此類實例是非限制性的，並且所附請求項的範圍不應限於揭示內容的特定實例。在下文論述中，術語“實例”和“例如”是非限制性的。
圖式說明了一般的構造方式，並且可能會省略熟知特徵和技術的描述和細節以免不必要地混淆本揭示內容。另外，圖式中的元件未必按比例繪製。例如，圖式中的一些元件的尺寸可能相對於其它元件放大，以便提高對本揭示內容中論述的實例的理解。不同圖式中的相同附圖標記表示相同的元件。
術語“或”表示由“或”連接的列表中的專案中的任何一個或多個專案。作為實例，“x或y”表示三元素集合{(x), (y), (x, y)}中的任何元素。作為另一實例，“x、y或z”表示七元素集合{(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}中的任何元素。
術語“包括”和/或“包含”為“開放”術語，並且指定所陳述特徵的存在，但並不排除一個或多個其它特徵的存在或添加。
在本文中可以使用術語“第一”、“第二”等來描述各種元件，並且這些元件不應受這些術語的限制。這些術語僅用於區分一個元件與另一個元件。因此，例如，在不脫離本揭示內容的教導的情況下，本揭示內容中論述的第一元件可以被稱為第二元件。
除非另外指定，否則術語“耦合”可以用於描述彼此直接接觸的兩個元件或描述通過一個或多個其它元件間接連接的兩個元件。例如，如果元件A耦合到元件B，則元件A可以直接接觸元件B或通過插入元件C間接連接到元件B。類似地，術語“在……之上”或“在……上”可以用於描述彼此直接接觸的兩個元件或描述通過一個或多個其它元件間接連接的兩個元件。
100:半導體裝置
101:半導體封裝件
110:電子裝置
110c:裝置側壁
110d:側壁
110p:裝置底部平面
111:端子
120:基板
121:介電結構
121a:介電質頂部區段
121b:介電質底部區段
121c:介電質側區段
122:導電結構
122a:導體頂部區段
122b:導體底部區段
122c:導體側區段
122x:導體
122y:導體
122z:導體
130:電子構件
130c:構件側壁
131:端子
140:基板
141:介電結構
142:導電結構
142x:導體
142y:導體
142z:導體
150:互連件
160:囊封物
170:互連件

Claims (21)

  1. 一種半導體裝置，其包括：電子裝置，所述電子裝置包括：裝置頂部側，所述裝置頂部側包括裝置第一端子；裝置底部側，所述裝置底部側與所述裝置頂部側相對；以及裝置第一側壁，所述裝置第一側壁在所述裝置頂部側與所述裝置底部側之間；以及基板，所述基板包括：介電材料，所述介電材料包括：介電質頂部區段，所述介電質頂部區段在所述裝置頂部側之上，其中所述介電質頂部區段包括在所述裝置第一端子之上的介電質第一開口；介電質側區段，所述介電質側區段在所述裝置第一側壁之上並且與所述介電質頂部區段相連；以及介電質底部區段，所述介電質底部區段包括與所述裝置底部側大致上共平面並且與所述介電質側區段相連的下表面；以及第一導電材料，所述第一導電材料包括：第一導電頂部區段，所述第一導電頂部區段在所述介電質頂部區段之上並且穿過所述介電質第一開口耦合到所述裝置第一端子；第一導電側區段，所述第一導電側區段在所述介電質側區段之上並且與所述第一導電頂部區段相連；以及第一導電底部區段，所述第一導電底部區段在所述介電質底部區 段之上並且與所述第一導電側區段相連。
  2. 根據請求項1所述的半導體裝置，其中：所述裝置底部側限定裝置底部平面；以及與所述第一導電頂部區段的下表面相比，所述第一導電底部區段的上表面更接近於所述裝置底部平面。
  3. 根據請求項1所述的半導體裝置，其中：所述第一導電側區段大致上正交於所述第一導電頂部區段和所述第一導電底部區段；並且所述第一導電頂部區段和所述第一導電底部區段大致上不與彼此重疊。
  4. 根據請求項1所述的半導體裝置，其進一步包括：囊封物，所述囊封物在所述基板之上，形成所述裝置第一側壁的邊界，並且包括囊封物第一側壁；其中：所述介電質底部區段包括由所述囊封物第一側壁暴露並且與所述囊封物第一側壁大致上共平面的介電質第一末端；並且所述第一導電底部區段包括被所述囊封物第一側壁覆蓋的第一導電端點，與所述第一導電底部區段的任何其它點相比，所述第一導電端點更接近於所述囊封物第一側壁。
  5. 根據請求項1所述的半導體裝置，其進一步包括：電子構件，所述電子構件包括：構件底部側；構件第一端子，所述構件第一端子在所述構件底部側上；以及構件側壁；以及 第一內部互連件，所述第一內部互連件在所述第一導電頂部區段之上並且耦合到所述構件第一端子。
  6. 根據請求項5所述的半導體裝置，其中：所述電子構件包括：構件介電材料，所述構件介電材料在所述構件底部側之上並且暴露所述構件第一端子；以及構件導電材料，所述構件導電材料在所述構件介電材料之上，從所述構件第一端子側向地延伸，並且將所述構件第一端子耦合到所述第一內部互連件。
  7. 根據請求項5所述的半導體裝置，其進一步包括：囊封物，所述囊封物在所述構件底部側與所述基板之間延伸，形成所述裝置第一側壁和所述第一內部互連件的邊界，並且包括囊封物第一側壁；其中所述囊封物第一側壁與所述構件側壁和所述介電材料的側壁大致上共平面。
  8. 根據請求項5所述的半導體裝置，其中：所述構件第一端子穿過所述介電質第一開口通過所述第一內部互連件和所述第一導電頂部區段耦合到所述裝置第一端子。
  9. 根據請求項8所述的半導體裝置，其中：所述第一內部互連件從所述構件第一端子和所述裝置第一端子側向地偏移。
  10. 根據請求項5所述的半導體裝置，其進一步包括：第一外部互連件，所述第一外部互連件在所述基板的底部上；其中所述構件第一端子通過所述第一內部互連件、所述基板的所述第一導電頂部區段、所述第一導電側區段以及所述第一導電底部區段耦合到所述第一外部互連件。
  11. 根據請求項10所述的半導體裝置，其中：所述構件第一端子穿過所述介電質第一開口通過所述第一內部互連件和所述第一導電頂部區段耦合到所述裝置第一端子。
  12. 根據請求項1所述的半導體裝置，其中：所述電子裝置包括：裝置第二側壁，所述裝置第二側壁在所述裝置頂部側與所述裝置底部側之間；所述介電質側區段在所述裝置第二側壁之上延伸；所述基板包括第二導電材料，所述第二導電材料包括：第二導電頂部區段，所述第二導電頂部區段在所述介電質頂部區段之上；第二導電側區段，所述第二導電側區段在所述介電質側區段之上、在所述裝置第二側壁之上並且與所述第二導電頂部區段相連；以及第二導電底部區段，所述第二導電底部區段在所述介電質底部區段之上並且與所述第二導電側區段相連。
  13. 根據請求項12所述的半導體裝置，其進一步包括：電子構件，所述電子構件包括：構件底部側；構件第一端子，所述構件第一端子在所述構件底部側上；構件第二端子，所述構件第二端子在所述構件底部側上；以及構件側壁；第一內部互連件，所述第一內部互連件耦合到所述構件第一端子；第二內部互連件，所述第二內部互連件耦合到所述構件第二端子；第一外部互連件，所述第一外部互連件在所述基板的底部上；以及 第二外部互連件，所述第二外部互連件在所述基板的底部上；其中：所述構件第一端子穿過所述介電質第一開口通過所述第一內部互連件和所述第一導電頂部區段耦合到所述裝置第一端子；所述構件第二端子通過所述第二內部互連件、所述第二導電頂部區段、所述第二導電側區段以及所述第二導電底部區段耦合到所述第二外部互連件。
  14. 一種半導體裝置，其包括：半導體裝置頂側；半導體裝置底側，所述半導體裝置底側與所述半導體裝置頂側相對；以及半導體裝置側壁，所述半導體裝置側壁在所述半導體裝置頂側與所述半導體裝置底側之間；電子裝置，所述電子裝置包括：電子裝置頂部側；電子裝置底部側，所述電子裝置底部側與所述電子裝置頂部側相對；以及電子裝置側壁，所述電子裝置側壁在所述電子裝置頂部側與所述電子裝置底部側之間；介電層，所述介電層與所述電子裝置頂部側、所述電子裝置側壁以及所述電子裝置底部側保形，其中所述介電層包括：介電層第一上表面，所述介電層第一上表面在所述電子裝置頂部側上方；以及介電層第二上表面，所述介電層第二上表面在所述所述半導體裝置底側上方，其中，在所述介電層第一上表面和所述半導體裝置底側之間的距離是大 於所述介電層第二上表面和所述半導體裝置底側之間的距離；第一導體，所述第一導體沿著所述介電層第一上表面和所述介電層第二上表面延伸；以及保護材料，所述保護材料覆蓋所述第一導體和所述電子裝置。
  15. 根據請求項14所述的半導體裝置，其進一步包括：第一介電開口，所述第一介電開口在所述介電層第二上表面中；以及外部互連件，所述外部互連件經由在所述介電層第二上表面中的所述第一介電開口耦合到所述第一導體；電子構件，所述電子構件包括：構件底部側；以及構件第一端子，所述構件第一端子在所述構件底部側上；以及第一內部互連件，所述第一內部互連件耦合到所述構件第一端子和所述第一導體；其中所述構件第一端子通過所述第一導體耦合到所述外部互連件；並且其中所述保護材料囊封所述第一內部互連件並且接觸所述構件底部側。
  16. 根據請求項15所述的半導體裝置，其中：所述電子裝置包括在所述電子裝置頂部側上的電子裝置第一端子；並且所述構件第一端子通過所述第一內部互連件和所述第一導體耦合到所述電子裝置第一端子。
  17. 根據請求項15所述的半導體裝置，其中：所述保護材料包括保護性側壁；所述電子構件包括構件側壁；並且所述半導體裝置側壁包括所述介電層的側壁、所述構件側壁以及所述保護 性側。
  18. 根據請求項14所述的半導體裝置，其中所述電子裝置底部側由在所述半導體裝置底側處的所述介電層來暴露。
  19. 一種製造半導體裝置的方法，其包括：提供電子裝置，所述電子裝置包括：裝置頂部側，所述裝置頂部側包括裝置第一端子；裝置底部側，所述裝置底部側與所述裝置頂部側相對；以及裝置第一側壁，所述裝置第一側壁在所述裝置頂部側與所述裝置底部側之間；以及提供介電質，所述介電質包括：介電質頂部區段，所述介電質頂部區段在所述裝置頂部側之上，其中所述介電質頂部區段包括在所述裝置第一端子之上的介電質第一開口；介電質側區段，所述介電質側區段在所述裝置第一側壁之上並且與所述介電質頂部區段相連；以及介電質底部區段，所述介電質底部區段與所述介電質側區段相連；其中：所述介電質底部區段的下表面與所述裝置底部側大致上共平面；並且所述介電質底部區段的上表面低於所述介電質頂部區段的上表面。
  20. 根據請求項19所述的方法，其進一步包括：提供導體，所述導體包括：導體頂部區段，所述導體頂部區段在所述介電質頂部區段之上；導體側區段，所述導體側區段在所述介電質側區段之上並且與所述導體頂部區段相連；以及 導體底部區段，所述導體底部區段在所述介電質底部區段之上並且與所述導體側區段相連；提供電子構件，所述電子構件包括：構件底部側；以及構件第一端子，所述構件第一端子在所述構件底部側上；耦合第一內部互連件與所述構件第一端子和所述導體頂部區段；以及通過所述介電質底部區段耦合外部互連件與所述導體底部區段；其中：提供所述介電質包括：提供與所述電子裝置的輪廓保形的所述介電質；提供所述導體包括：提供與所述介電質和所述電子裝置的輪廓保形的所述導體；以及提供穿過所述介電質第一開口並且耦合到所述裝置第一端子的所述導體頂部區段的一部分；並且耦合所述外部互連件包括：通過所述第一內部互連件、所述導體頂部區段、所述導體側區段以及所述導體底部區段耦合所述構件第一端子與所述外部互連件。
  21. 根據請求項19所述的方法，其進一步包括：提供導體，所述導體包括：導體頂部區段，所述導體頂部區段在所述介電質頂部區段之上；導體側區段，所述導體側區段在所述介電質側區段之上並且與所述導體頂部區段相連；以及導體底部區段，所述導體底部區段在所述介電質底部區段之上並且與 所述導體側區段相連；以及在所述導體、所述介電質以及所述電子裝置之上提供囊封物；其中：提供所述介電質包括：提供與所述電子裝置的輪廓保形的所述介電質；提供所述導體包括：提供與所述介電質和所述電子裝置的輪廓保形的所述導體；以及提供穿過所述介電質第一開口並且耦合到所述裝置第一端子的所述導體頂部區段的一部分；並且提供所述囊封物包括：提供與所述導體頂部區段、所述導體側區段以及所述導體底部區段保形的所述囊封物的底部。
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