TW202121608A - 半導體裝置及製造半導體裝置的方法 - Google Patents

半導體裝置及製造半導體裝置的方法 Download PDF

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TW202121608A
TW202121608A TW109120620A TW109120620A TW202121608A TW 202121608 A TW202121608 A TW 202121608A TW 109120620 A TW109120620 A TW 109120620A TW 109120620 A TW109120620 A TW 109120620A TW 202121608 A TW202121608 A TW 202121608A
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substrate
cavity
electronic component
redistribution structure
redistribution
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TW109120620A
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林基泰
金傑雲
周名佳
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新加坡商安靠科技新加坡控股私人有限公司
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Publication of TW202121608A publication Critical patent/TW202121608A/zh

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Abstract

在一個實例中，一種半導體結構包括：重新分佈結構，所述重新分佈結構包括導電結構；腔基板，所述腔基板位於所述重新分佈結構的頂側上並且具有腔和接觸所述重新分佈結構的柱；電子組件，所述電子組件位於所述重新分佈結構的頂表面上和所述腔中，其中所述電子組件與所述導電結構電耦合；以及囊封件，所述囊封件位於所述腔中和所述重新分佈結構的所述頂側上，所述囊封件接觸所述電子組件的側面、所述腔的側面以及所述柱的側面。本文還公開了其它實例和相關方法。

Description

半導體裝置及製造半導體裝置的方法
本公開總體上涉及電子裝置，並且更具體地涉及半導體裝置及用於製造半導體裝置的方法。
現有半導體封裝件和用於形成半導體封裝件的方法存在不足之處，例如造成成本過多、可靠性降低、性能相對較低或封裝件尺寸太大。對於本領域的技術人員來說，通過將常規和傳統方法與本公開進行比較並且參考附圖，此類方法的另外的局限性和缺點將變得明顯。
在一個具體實例中，本發明提供一種半導體結構，其包括：重新分佈結構，所述重新分佈結構包括導電結構；腔基板，所述腔基板位於所述重新分佈結構的頂側上並且具有腔和與所述重新分佈結構接觸的柱；電子組件，所述電子組件位於所述重新分佈結構的頂表面上和所述腔中，其中所述電子組件與所述導電結構電耦合；以及囊封件，所述囊封件位於所述腔中和所述重新分佈結構的所述頂側上，所述囊封件接觸所述電子組件的側面、所述腔的側面以及所述柱的側面。
在另一個具體實例中，本發明提供一種用於製造半導體結構的方法，所述方法包括：提供具有腔和基板互連件的腔基板；將具有組件互連件的電子組件放置在所述腔基板的所述腔中；在所述腔基板的頂側上在所述腔中提供囊封件，所述囊封件接觸所述電子組件的側面、所述基板互連件和所述組件互連件；以及在所述腔基板的所述頂側上提供重新分佈結構，其中所述重新分佈結構具有與所述基板互連件耦合的導電結構。
在另一個具體實例中，本發明提供一種半導體結構，其包括：第一半導體裝置，所述第一半導體裝置包括：重新分佈結構，所述重新分佈結構包括導電結構；第一基板，所述第一基板位於所述重新分佈結構的頂側上並且具有腔和接觸所述重新分佈結構的柱；電子組件，所述電子組件位於所述重新分佈結構的頂表面上和所述腔中，其中所述電子組件通過組件互連件與所述導電結構電耦合；以及囊封件，所述囊封件位於所述腔中和所述重新分佈結構的所述頂側上，所述囊封件形成所述電子組件和所述柱的側面的邊界；以及第二半導體裝置，所述第二半導體裝置位於所述第一半導體裝置的頂側上，其中所述第二半導體裝置與所述第一基板的頂側上的基板焊盤電耦合。
以下討論提供了半導體裝置及製造半導體裝置的方法的各種實例。此類實例是非限制性的，並且所附權利要求的範圍不應限於所公開的特定實例。在以下討論中，術語“實例”和“例如”是非限制性的。
附圖展示了一般的構造方式，並且可以省略公知特徵和技術的描述和細節，以避免不必要地模糊本公開。另外，附圖中的元件不一定按比例繪製。例如，圖中元件中的一些元件的尺寸可能相對於其它元件而被放大以有助於改善對本公開所討論的實例的理解。不同附圖中的相同附圖標記指示相同的元件。
術語“或”意味著由“或”連接的列表中的項目的任何一個或多個項目。作為實例，“x或y”意味著三元素集合{(x), (y), (x, y)}中的任何元素。作為另一個實例，“x、y或z”意味著七元素集合{(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}中的任何元素。
術語“包括（comprises）”、“包括（comprising）”、“包含（includes）”和/或“包含（including）”是“開放式”術語並且指定存在所陳述的特徵，但不排除存在或增加一個或多個其它特徵。在本文中可以使用術語“第一”、“第二”等來描述各種元件，並且這些元件不應受這些術語的限制。這些術語僅是用來將一個元件與另一個元件進行區分。因此，例如，在不背離本公開的教導的情況下，本公開中所討論的第一元件可以被稱為第二元件。
除非另外指明，否則術語“耦合”可以用於描述彼此直接接觸的兩個元件或描述通過一個或多個其它元件間接連接的兩個元件。例如，如果元件A耦合到元件B，則元件A可以直接接觸元件B或通過中間元件C間接連接到元件B。類似地，術語“之上”或“上”可以用於描述彼此直接接觸的兩個元件或描述通過一個或多個其它元件間接連接的兩個元件。如共面、平面、垂直、豎直、水平等幾何描述性術語不僅涵蓋此類確切術語，還涵蓋此類術語的例如，在製造公差範圍內的基本上近似情況。
在一個實例中，一種半導體結構包括：重新分佈結構，所述重新分佈結構包括導電結構；腔基板，所述腔基板位於所述重新分佈結構的頂側上並且具有腔和接觸所述重新分佈結構的柱；電子組件，所述電子組件位於所述重新分佈結構的頂表面上和所述腔中，其中所述電子組件與所述導電結構電耦合；以及囊封件，所述囊封件位於所述腔中和所述重新分佈結構的所述頂側上，所述囊封件接觸所述電子組件的側面、所述腔的側面以及所述柱的側面。
在另一個實例中，一種用於製造半導體結構的方法包括提供具有腔和基板互連件的腔基板；將具有組件互連件的電子組件放置在所述腔基板的所述腔中；在所述腔基板的頂側上在所述腔中提供囊封件，所述囊封件接觸所述電子組件的側面、所述基板互連件和所述組件互連件；以及在所述腔基板的所述頂側上提供重新分佈結構，其中所述重新分佈結構具有與所述基板互連件耦合的導電結構。
在另外的實例中，一種半導體結構包括：第一半導體裝置，所述第一半導體裝置包括：重新分佈結構，所述重新分佈結構包括導電結構；第一基板，所述第一基板位於所述重新分佈結構的頂側上並且具有腔和接觸所述重新分佈結構的柱；電子組件，所述電子組件位於所述重新分佈結構的頂表面上和所述腔中，其中所述電子組件通過組件互連件與所述導電結構電耦合；以及囊封件，所述囊封件位於所述腔中和所述重新分佈結構的所述頂側上，所述囊封件形成所述電子組件和所述柱的側面的邊界。半導體結構還包括第二半導體裝置，所述第二半導體裝置位於所述第一半導體裝置的頂側上，其中所述第二半導體裝置與所述第一基板的頂側上的基板焊盤電耦合。
本公開中包含其它實例。此類實例可以存在於本公開的附圖中、權利要求中和/或說明書中。
圖1示出了示例半導體裝置的橫截面視圖。在圖1所示的實例中，半導體裝置100可以包括基板110、電子組件120、囊封件130、重新分佈結構140和外部互連件150。
基板110可以包括絕緣層111、導電襯墊112和113、導電路徑114、介電層115和116以及基板互連件117。電子組件120可以包括組件互連件122。重新分佈結構140可以包括介電結構141和143以及導電結構142和144。
基板110、囊封件130、重新分佈結構140和外部互連件150可以包括或被稱為半導體封裝件101或封裝件101，並且半導體封裝件101可以為電子組件120提供保護以免受到外部元件和/或環境曝露的影響。另外，半導體封裝件101可以提供外部組件與電子組件120之間的電耦合。
在一些實例中，電子組件120的頂側可以與囊封件130的頂側共面。在一些實例中，共面可以意指在製造公差內，電子組件的頂側總體上可以與囊封件130的頂側位於同一平面內。例如，電子組件120的頂側可以稍微凸出到囊封件130的頂側上方，或者電子組件120的頂側可以相對於囊封件130的頂側稍微凹陷，同時在此類公差內保持共面。應注意，這些僅僅是描述電子組件的頂側與囊封件130的頂側之間的關係的實例，並且本公開的範圍不限於這些方面。
在一些實例中，重新分佈結構140可以包括導電結構142或144，並且基板110可以包括位於重新分佈結構140的頂側上的腔基板，所述腔基板具有填充有囊封件130的腔119和接觸重新分佈結構140的柱117。電子組件120可以位於重新分佈結構140的頂表面上和腔119中，其中電子組件120與導電結構142或144電耦合。囊封件可以位於腔119中和重新分佈結構140的頂側上，所述囊封件接觸電子組件120的側面、腔119的側面以及柱117的側面。
圖2A到2G示出了用於製造示例半導體裝置100的示例方法的橫截面視圖。圖3A到3C示出了用於形成圖2A所示的基板110的示例方法的透視圖。圖4A和4B示出了用於形成圖2B所示的電子組件120的示例方法的透視圖。
圖2A示出了處於早期製造階段的半導體裝置100的橫截面視圖。圖3A到圖3C示出了用於形成基板110的示例方法的透視圖。
在圖2A所示的實例中，載體10可以是基本上平面的板。在一些實例中，載體10可以包括或被稱為板、晶片、面板或條帶。在一些實例中，載體10可以包括例如但不限於鋼、不銹鋼、鋁、銅、陶瓷、玻璃、半導體或晶片。載體10的厚度可以在大約1毫米（mm）到大約1.5 mm的範圍並且寬度內可以在大約200 mm到大約320 mm的範圍內。
載體10可以用於將基板110附接到電子組件120的整合方式來處理多個組件，從而形成囊封件130並且形成重新分佈結構140。載體10通常可以應用於本公開所公開的不同實例。電子組件120可以具有組件互連件122並且可以放置在腔基板110的腔119中。可以在腔基板110的頂側上在腔119中提供囊封件130，其中囊封件130可以接觸電子組件120的側面、基板互連件117的側面和組件互連件122的側面。然後，可以在腔基板110的頂側上提供重新分佈結構140。重新分佈結構140可以具有與基板互連件117耦合的導電結構144或144。
可以在載體10的表面上提供臨時接合層11。可以使用如以下等塗覆製程在載體10的表面上提供臨時接合層11：旋塗、刮刀、鑄造、刷塗、噴塗、狹縫式塗覆（slot die coating）、簾幕式塗覆（curtain coating）、斜板式塗覆（slide coating）或邊緣刮刀式塗覆（knife over edge coating）；印刷製程，如絲網印刷、移印製程、凹版印刷、柔性版塗覆或膠版印刷；噴墨印刷製程；或黏合膜或膠帶的直接附接。臨時接合層11可以包括或被稱為臨時黏合膜或臨時膠帶。臨時接合層11可以是例如但不限於可熱釋放膜或紫外線（UV）可釋放膜，其接合強度可能被弱化，或者可以通過加熱或UV照射來去除。在一些實例中，臨時接合層11可以具有弱化的結合強度或者可以通過物理和/或化學外力去除。臨時接合層11的厚度可以在大約50微米（μm）到大約100 μm的範圍內。臨時接合層11可以在形成重新分佈結構140之後使載體10分離，這將在稍後描述。臨時接合層11通常可以應用於本公開所公開的不同實例。
可以將具有基板互連件117和界定腔119的基板110附接到臨時接合層11。基板110可以包括絕緣層111、導電襯墊112和113、導電路徑114、介電層115和116以及基板互連件117。在一些實例中，可以省略導電襯墊112和113、導電路徑114或介電層115和116中的至少一個。另外，基板110可以包括延伸通過頂表面110b與底表面110a之間的區域的腔119。
在一些實例中，基板110可以包括或被稱為印刷電路板（PCB）、腔基板、印刷佈線板、多層基板、通孔基板、剛性基板、柔性基板、玻璃環氧樹脂基板、聚醯亞胺基板、聚酯基板、模製塑料基板、陶瓷基板、蝕刻箔製程基板、加成製程基板、堆積基板或預模製引線框。在一些實例中，可以提供具有腔119和基板互連件117的腔基板110。
在一些實例中，絕緣層111可以具有基本上平面的頂表面111b和底表面111a。在一些實例中，絕緣層111可以包括或被稱為介電層或芯層。在一些實例中，絕緣層111可以包括環氧樹脂、酚樹脂、玻璃環氧樹脂、聚醯亞胺、聚酯、環氧模製化合物或矽樹脂或陶瓷。在一些實例中，絕緣層111的厚度可以在大約10 μm到大約500 μm的範圍內。絕緣層111可以將基板110保持在基本上平面的狀態或者可以限制彎曲，並且還可以在基板110的導體之間提供絕緣。
可以在絕緣層111的底表面111a上形成導電襯墊112，並且可以在絕緣層111的頂表面111b上形成導電襯墊113。導電襯墊112和113可以以具有行和/或列的矩陣配置形成於絕緣層111的底表面111a和頂表面111b上。在一些實例中，導電襯墊112或113可以包括或被稱為導體、導電材料、基板焊盤、導電焊盤、基板襯墊、引線襯墊、連接襯墊、微襯墊、跡線或凸點下金屬（UBM）。在一些實例中，基板焊盤112和基板襯墊113可以包括銅、鐵、鎳、金、銀、鈀或錫。在一些實例中，基板焊盤112和基板襯墊113的厚度、寬度和空間可以在大約50 μm到大約500 μm的範圍內。
在一些實例中，導電路徑114可以電連接基板焊盤112和基板襯墊113，同時延伸通過絕緣層111。在一些實例中，導電路徑114可以包括或被稱為導體、導電材料、導電通孔、電路圖案或導電桿。在一些實例中，導電路徑114可以包括銅、鐵、鎳、金、銀、鈀或錫。在一些實例中，導電路徑114的厚度可以在大約10 μm到大約500 μm的範圍內。
如圖2A和圖2B所示，介電層115可以大致覆蓋基板焊盤112的部分和絕緣層111的底表面111a，並且介電層116可以大致覆蓋基板襯墊113的部分和絕緣層111的頂表面111b。在一些實例中，介電層115和116可以包括或被稱為電介質、介電材料、介電層、絕緣層、焊接遮罩或阻焊劑。在一些實例中，可以通過介電層115曝露基板焊盤112的要連接到另一個半導體裝置的部分。另外，可以透過介電層116曝露基板襯墊113的要連接到基板互連件117的部分。在一些實例中，介電層115和116可以包括聚合物、聚醯亞胺（PI）、苯並環丁烯（BCB）、聚苯並惡唑（PBO）、雙馬來醯亞胺三嗪（BT）、模製材料、酚樹脂、環氧樹脂、矽樹脂或丙烯酸酯聚合物。在一些實例中，介電層115和116的厚度可以在大約10 μm到大約100 μm的範圍內。介電層115可以用於保護接近基板110的底表面110a的導體，並且介電層116可以用於保護接近基板110的頂表面110b的導體。
圖2A和圖3A示出了用於在基板110X上形成或提供基板互連件117的示例方法。基板110X可以用於一次製造大量具有大量基板互連件117和大量腔119的單獨基板110。
在圖2A和圖3A所示的實例中，基板110，包含絕緣層111、基板焊盤112、基板襯墊113、導電路徑114和介電層115和116可以具有電連接到基板襯墊113的基板互連件117。
可以在基板襯墊113的頂表面上形成基板互連件117。與基板襯墊113相似，可以以具有行或列的矩陣配置形成基板互連件117。基板互連件117可以形成為從基板襯墊113向上延伸。在一些實例中，基板互連件117的高度可以在大約0.1 mm到大約0.5 mm的範圍內並且寬度可以在大約0.2 mm到大約1 mm的範圍內。
在一些實例中，可以藉由但不限於電鍍、化學鍍、濺射、PVD、CVD、MOCVD、ALD、LPCVD或PECVD形成基板互連件117。在一些實例中，基板互連件117可以包括銅、金、銀、鈀、鎳或焊料。基板互連件117可以包括或被稱為柱、樁、欄、通孔、豎直引線、凸點或導電路徑。在一些實例中，基板互連件117可以將稍後要描述的重新分佈結構140電連接或機械連接到基板110。
圖2A和圖3B示出了用於在基板110X上形成腔119的示例方法。在圖2A和圖3B所示的實例中，可以在基板110X上形成延伸穿透基板110X的頂表面110b和底表面110a的腔119。可以以具有行或列的矩陣配置形成腔119。可以以矩形形狀或與電子組件120相對應的形狀形成腔119。可以在基板110X上中在包含層111和介電層115和116的區域中形成腔119。可以在基板110X的頂表面110b上定位基板互連件117，以便在腔119周圍在行方向和/列方向上間隔開。在一些實例中，腔119的大小可以在大約1 mm到大約10 mm的範圍內。
圖2A和3C示出了用於將基板110X單切成各自具有腔119的單獨基板110的實例方法。在一些實例中，可以使用金剛石刀片或雷射光束將基板110X單切成單獨基板110。可以通過臨時接合層11將單獨基板110中的具有一個腔119的每個單獨基板的底表面110a附接到圖2A所示的載體10。基板110可以具有大致定位於其中心的腔119或可以是矩形環。另外，在行方向或列方向上彼此間隔開的基板互連件117可以定位於腔119的在基板110的頂表面上形成的相應側之外。
圖2B示出了處於後期製造階段的半導體裝置100的橫截面視圖。圖4A和圖4B示出了用於形成或提供電子組件120的示例方法的透視圖。在圖2B所示的實例中，可以將具有組件互連件122的電子組件120附接到載體10的臨時接合層11。可以在電子組件120的頂表面上提供大量端子121，並且組件互連件122可以分別電連接到大量端子121。端子121可以是電子組件120的輸入/輸出端子並且可以包括或被稱為晶粒襯墊或接合襯墊。在一些實例中，端子121的寬度可以在大約50 μm到大約500 μm的範圍內。
圖4A示出了用於形成要電連接到電子組件120的端子121的組件互連件122的示例方法。在圖2B和圖4A所示的實例中，可以製備具有電子組件120的晶片120X，並且可以在晶片120X的頂表面上形成組件互連件122以電連接到電子組件120的端子121。可以分別在端子121的頂表面上形成組件互連件122。另外，可以在晶片120X的製造期間形成組件互連件122。
與端子121相似，可以以具有行或列的矩陣配置形成組件互連件122。組件互連件122可以形成為從端子121向上延伸。在一些實例中，組件互連件122的高度可以在大約20 μm到大約150 μm的範圍內並且寬度可以在大約0.05 mm到大約1 mm的範圍內。在製造晶片120X期間形成組件互連件122，並且組件互連件122的大小和寬度可以小於基板互連件117的大小和寬度。
在一些實例中，可以通過但不限於電鍍、化學鍍、濺射、PVD、CVD、MOCVD、ALD、LPCVD或PECVD形成組件互連件122。在一些實例中，組件互連件122可以包括銅、金、銀、鈀、鎳或焊料。組件互連件122可以包括或被稱為柱、樁、欄、凸點或導電路徑。在一些實例中，組件互連件122可以將稍後要描述的重新分佈結構140電連接或機械連接到電子組件120。
圖4B示出了用於將具有組件互連件122的晶片120X單切成單獨的電子組件120的示例方法。在圖2B和圖4B所示的實例中，可以將具有組件互連件122的晶片120X單切成單獨的電子組件120。在一些實例中，可以使用金剛石刀片或雷射光束將晶片120X劃分為單獨的電子組件120。
可以通過臨時接合層11將具有組件互連件122的電子組件120中的每個電子組件的底表面120a附接到圖2B所示的載體10。可以在基板110的腔119內定位電子組件120。電子組件120的大小可以小於腔119的大小。電子組件120的側表面可以與基板110間隔開。
電子組件120可以包括或被稱為半導體晶粒、半導體晶片或半導體封裝件，如晶片級封裝件（chip-scale package）。在一些實例中，電子組件120可以包括特殊應用積體電路、邏輯晶粒、微控制單元、記憶體、數位信號處理器、網絡處理器、電源管理單元、音頻處理器、射頻（RF）電路或無線基頻系統上晶片處理器中的至少一個。電子組件120的厚度可以在大約50 μm到大約780 μm的範圍內。電子組件120的大小可以在大約3 mm到大約10 mm的範圍內。
圖2C示出了處於後期製造階段的半導體裝置100的橫截面視圖。在圖2C所示的實例中，囊封件130可以形成為完全覆蓋基板110和電子組件120。在一些實例中，囊封件130可以接觸基板110的頂表面110b，可以填充腔119，並且接觸基板互連件117的側表面和頂表面。在一些實例中，囊封件130可以接觸電子組件120的側表面或者可以接觸組件互連件122的側表面和頂表面兩者。
在一些實例中，囊封件130可以包括或被稱為環氧模製化合物、環氧樹脂、保護性電介質或密封劑。另外，在一些實例中，囊封件130可以包括或被稱為模製部件、密封部件、囊封部件、保護部件或封裝主體。在一些實例中，囊封件130可以包括但不限於有機樹脂、無機填料、固化劑、催化劑、耦合劑、著色劑或阻燃劑。囊封件130可以透過各種製程中的任何製程而形成。在一些實例中，囊封件130可以通過但不限於壓縮模製、傳遞模製、液相囊封件模製、真空層壓、膏印刷或膜輔助模製形成。囊封件130的厚度可以在大約0.1 mm到大約1 mm的範圍內。囊封件130可以形成為覆蓋基板110和電子組件120以保護基板110和電子組件120免受外部元件和/或環境曝露的影響。
圖2D示出了處於後期製造階段的半導體裝置100的橫截面視圖。在圖2D所示的實例中，可以去除囊封件130的上部部分以曝露基板互連件117的頂表面117b和位於囊封件130的頂表面130b處的組件互連件122的頂表面122b。可以通過研磨或化學蝕刻來去除囊封件130。還可以去除基板互連件117的上部部分和組件互連件122的上部部分。囊封件130的頂表面130b可以與基板互連件117的頂表面117b和組件互連件122的頂表面122b共面。其上部部分去除的囊封件130的厚度可以在大約10 μm到大約100 μm的範圍內。
圖2E示出了處於後期製造階段的半導體裝置100的橫截面視圖。在圖2E所示的實例中，可以在囊封件130的頂表面130b、基板互連件117的頂表面117b和組件互連件122的頂表面122b上形成重新分佈結構140。在一些實例中，重新分佈結構140可以類似於基板110，或者可以包括或被稱為基板。重新分佈結構140可以包括按順序形成的第一介電結構141、第一導電結構142、第二介電結構143和第二導電結構144。在重新分佈結構140中，第一電介質結構141可以首先形成為覆蓋囊封件130的頂表面130b、基板互連件117的頂表面117b和組件互連件122的頂表面122b到基本上均勻的厚度。另外，可以在第一介電結構141中形成孔洞141X和141Y以曝露基板互連件117的頂表面117b和組件互連件122的頂表面122b。
第一介電結構141或第二介電結構143可以包括或被稱為電介質、介電材料、介電層、鈍化層、絕緣層或保護層。在一些實例中，第一介電結構141或第二介電結構143可以包括但不限於電絕緣材料，如聚合物、聚醯亞胺（PI）、苯並環丁烯（BCB）、聚苯並惡唑（PBO）、雙馬來醯亞胺三嗪（BT）、模製材料、酚樹脂、環氧樹脂、矽樹脂或丙烯酸酯聚合物。另外，在一些實例中，可以通過各種製程中的任何製程來形成第一介電結構141或第二介電結構143。在一些實例中，可以通過旋塗、噴塗、印刷、PVD、CVD、MOCVD、ALD、LPCVD或PECVD形成第一介電結構141或第二介電結構143。第一介電結構（即，鈍化層）141或第二介電結構143的厚度可以在約1 μm到大約20 μm的範圍內。
在一些實例中，可以在第一介電結構141的頂表面上形成遮罩圖案，並且然後可以藉由蝕刻去除第一介電結構141的區域，從而形成孔洞141X和141Y。孔洞141X和141Y可以包括或被稱為開口或孔。第一介電結構141可以透過孔洞141X曝露基板互連件117的頂表面117b並且可以透過孔洞141Y曝露組件互連件122的頂表面122b。在一些實例中，可以使用光阻作為遮罩圖案。透過孔洞141X和141Y曝露的基板互連件117的頂表面117b和組件互連件122的頂表面122b可以具有圓形、矩形或多邊形形狀。
重新分佈結構140可以具有第一導電結構142，所述第一導電結構形成為覆蓋第一介電結構141的頂表面以及基板互連件117的頂表面117b和組件互連件122的頂表面122b，這些頂表面藉由孔洞141X和141Y而被曝露。
第一導電結構142可以由大量導體、跡線或圖案形成，並且可以使相應導體與基板互連件117的頂表面117b或者組件互連件122的頂表面122b（如透過孔洞141X和141Y所曝露）接觸。導體或第一導電結構142可以藉由基板互連件117電連接到基板110，或者藉由組件互連件122電連接到電子組件120。第一導電結構142可以包括導體142X，所述導體使基板互連件117的頂表面117b與組件互連件122的頂表面122b電連接。導體142X可以從電子組件120之上的點延伸到基板110之上的點並且可以將電子組件120和基板110彼此電連接。
在一些實例中，第一導電結構142或第二導電結構144可以包括或被稱為導體、導電材料、導電層、重新分佈層（RDL）、佈線圖案、跡線圖案或電路圖案。在一些實例中，導體142X可以包括或被稱為扇出路徑，其在電子組件120的佔用空間內延伸並且延伸超過所述佔用空間。在一些實例中，第一導電結構142或第二導電結構144可以由各種導電材料中的任何導電材料製成，所述各種導電材料包含例如銅、金、銀或等同物。第一導電結構142或第二導電結構可以藉由各種製程中的任何製程形成，所述各種製程包含例如濺射、化學鍍、電鍍、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物。第一導電結構142可以形成為用於覆蓋第一介電結構141的頂表面、基板互連件117的頂表面117b和組件互連件122的頂表面122b的預定厚度，所述頂表面藉由孔洞141X和141Y曝露，並且所述第一導電結構可以藉由遮罩圖案來圖案化以限定大量導體。第一導電結構142的厚度可以在大約5 μm到大約50 μm的範圍內。
重新分佈結構140可以具有第二介電結構143，所述第二介電結構形成為覆蓋第一介電結構141和第一導電結構142到基本上均勻的厚度。可以在第二介電結構143中形成曝露第一導電結構142的頂表面142b的孔洞143X。第二介電結構143還可以藉由孔洞143X曝露導體142X的頂表面。第二介電結構143可以類似於第一介電結構141並且可以類似地形成為第一介電結構141。
重新分佈結構140可以具有第二導電結構144，所述第二導電結構形成為覆蓋第一導電結構142的藉由孔洞143X所曝露的頂表面142b。第二導電結構144可以由大量導體、跡線或圖案形成，並且可以使相應導體與第一導電結構142的如孔洞143X曝露的頂表面142b接觸。第二導電結構144可以形成為部分覆蓋第二介電結構143的頂表面。第二導電結構144可以藉由第一導電結構142電連接到基板互連件117和/或組件互連件122。第二導電結構144可以包括或被稱為導體、導電材料、導電層、導電襯墊、微襯墊、接合襯墊、導電桿或凸點下金屬（UBM）。第二導電結構144可以類似於第一導電結構142並且可以類似地形成為第一導電結構142。作為實例，示出了包括兩個介電結構141和143以及兩個導電結構142和144的重新分佈結構140，但是重新分佈結構140可以包括少於或多於介電結構141和143或導電結構142和144。
在本發明的實例中，基板140呈現為重新分佈層（“RDL”）基板。RDL基板可以包括（a）可以在RDL基板要電耦合到的電子裝置之上逐層形成的，或者（b）可以在可以在將電子裝置和RDL基板耦合在一起之後完全去除或至少部分地去除的載體之上逐層形成的一個或多個導電重新分佈層和一個或多個介電層。RDL基板可以在圓形晶片上以晶片級製程逐層製造為晶片級基板，和/或在矩形或方形面板載體上以面板級製程逐層製造為面板級基板。RDL基板可以以可以包含與限定相應的導電重新分佈圖案或跡線的一個或多個導電層交替堆疊的一個或多個介電層的添加劑堆積製程形成，所述導電重新分佈圖案或跡線被配置成共同（a）將電跡線扇出電子裝置的佔用空間外，和/或（b）將電跡線扇入電子裝置的佔用空間內。可以使用鍍覆製程，例如電鍍製程或化學鍍製程來形成導電圖案。導電圖案可以包括導電材料，例如銅或其它可鍍覆金屬。可以使用光圖案化製程，例如光學微影製程和用於形成光學微影遮罩的光阻材料來製作導電圖案的位置。可以利用可以包含光學微影遮罩的光圖案化製程來圖案化RDL基板的介電層，光通過所述光學微影遮罩曝露到光圖案期望的特徵，如介電層中的通孔中。介電層可以由光可限定的有機介電材料，例如聚醯亞胺（PI）、苯並環丁烯（BCB）或聚苯並惡唑（PBO）製成。此類介電材料可以以液體形式旋塗或以其它方式塗覆，而不是以預形成的膜的形式附接。為了允許適當地形成期望的光限定的特徵，此類光可限定的介電材料可以省略結構增強劑，或者可以是不含填料的，沒有可能會干擾來自光圖案化製程的光的線、織物或其它顆粒。在一些實例中，不含填料的介電材料的此類不含填料的特性可以允許減小所得的介電層的厚度。儘管上文描述的光可限定的介電材料可以是有機材料，但是在其它實例中，RDL基板的介電材料可以包括一個或多個無機介電層。一個或多個無機介電層的一些實例可以包括氮化矽（Si3 N4 ）、氧化矽（SiO2 ）和/或SiON。所述一個或多個無機介電層可以通過使用氧化或氮化製程而不是使用光限定的有機介電材料來增長無機介電層形成。此類無機介電層可以是不含填料的，沒有線、織物或其它不同的無機顆粒。在一些實例中，RDL基板可以省略永久性芯結構或載體，例如包括雙馬來醯亞胺三嗪（BT）或FR4的介電材料，並且這些類型的RDL基板可以被稱為無核心基板。本公開中的其它基板也可以包括RDL基板。
在一些實例中，基板140可以是預形成的基板。預形成的基板可以在附接到電子裝置之前製造並且可以包括位於相應的導電層之間的介電層。導電層可以包括銅並且可以使用電鍍製程形成。介電層可以是可以以預形成的膜的形式而不是以液體的形式附接的相對較厚的非光可限定層，並且可以包含用於剛性和/或結構性支撐的具有如線、織物和/或其它無機顆粒等填料的樹脂。由於介電層是非光可限定的，因此可以通過使用鑽孔或雷射來形成如通孔或開口等特徵。在一些實例中，介電層可以包括預浸材料或味之素增層膜（ABF）。預形成的基板可以包含永久性核心結構或載體，例如包括雙馬來醯亞胺三嗪（BT）或FR4的介電材料，並且介電層和導電層可以形成於永久性核心結構上。在其它實例中，預形成的基板可以是省略永久性核心結構的無核心基板，並且介電層和導電層可以形成於在形成介電層和導電層之後並且在附接到電子裝置之前被去除的犧牲載體上。預形成的基板可以被稱為印刷電路板（PCB）或層壓基板。此類預形成的基板可以通過半加成法製程或經改進的半加成法製程形成。本公開中的其它基板也可以包括預形成的基板。
圖2F示出了處於後期製造階段的半導體裝置100的橫截面視圖。在圖2F所示的實例中，可以從基板110的底表面110a、電子組件120的底表面120a和囊封件130的底表面130a去除載體10。在臨時接合層11附接到載體10的狀態下，可以從基板110、電子組件120和囊封件130去除載體10。在一些實例中，可以通過提供熱、光、化學溶液或物理外力來去除或弱化臨時接合層11的黏附性。因此，可以曝露基板110的底表面110a、電子組件120的底表面120a和囊封件130的底表面130a。另外，還可以曝露基板焊盤112的底表面112a。
圖2G示出了處於後期製造階段的半導體裝置100的橫截面視圖。在圖2G所示的實例中，可以在第二導電結構144的頂表面144b上提供外部互連件150。外部互連件150可以電連接到第二導電結構144的頂表面144b。外部互連件150可以通過重新分佈結構140和基板互連件117電連接到基板110，或者通過重新分佈結構140和組件互連件122電連接到電子組件120。另外，外部互連件150可以通過重新分佈結構140的導體142X電連接到基板110和電子組件120兩者。
在一些實例中，外部互連件150可以包括錫（Sn）、銀（Ag）、鉛（Pb）、銅（Cu）、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。外部互連件150可以通過例如球落、絲網印刷或電鍍形成。例如，外部互連件150可以通過球落在重新分佈結構140的第二導電結構144的頂表面144b上形成含有焊料的導電材料，然後執行回流製程來形成。外部互連件150可以包括或被稱為如焊球等導電球、如銅柱等導電柱，或具有在銅柱上形成的焊帽的導電桿。外部互連件150的大小可以在大約0.1 mm到大約0.5 mm的範圍內。另外，已完成的半導體裝置100可以翻轉，並且外部互連件150可以定位於半導體裝置100的基板100的底表面100y上。在一些實例中，外部互連件150可以包括或被稱為半導體裝置100的外部輸入/輸出端子。
現在參考圖5，示出了示例性半導體裝置300的橫截面視圖。在圖5所示的實例中，半導體裝置300可以包括第一半導體裝置100和第二半導體裝置200。第一半導體裝置100可以與圖1所示的半導體裝置100相同。第二半導體裝置200可以包括基板210、電子組件220、囊封件230和互連件240。第一半導體裝置100可以包括重新分佈結構140、第一基板110，所述重新分佈結構包括導電結構142或144，所述第一基板位於重新分佈結構140的頂側並且具有腔119和接觸重新分佈結構140的柱。電子組件120可以位於重新分佈結構140的頂表面上和腔119中，其中電子組件120可以通過組件互連件122與導電結構142或144電耦合。囊封件130可以位於腔119中和重新分佈結構140的頂側上，所述囊封件形成電子組件120和柱117的側面的邊界。
第二半導體裝置200可以位於第一半導體裝置100的頂側上，其中第二半導體裝置200可以在第一半導體裝置100的頂側上與基板焊盤112電耦合。參考第二半導體裝置200，基板210可以包括介電層212和214以及導電層211、213和215。電子組件220可以包括端子221和內部互連件222。基板210、囊封件230和互連件240可以包括或被稱為半導體封裝件202並且可以為電子組件220提供保護以免受到外部元件或環境曝露的影響。另外，半導體封裝件202可以提供外部組件與電子組件220之間的電耦合。
圖6A和6B示出了用於製造示例半導體裝置的示例方法的橫截面視圖。圖6A示出了處於早期製造階段的半導體裝置300的橫截面視圖。
在圖6A所示的實例中，可以製備半導體裝置100。用於製造圖6A所示的第一半導體裝置100的示例方法可以類似於製造圖2A到2G、圖3A到3C和圖4A和4B所示的半導體裝置100的示例方法。
在圖6A和圖6B所示的實例中，可以將第二半導體裝置200的互連件240電連接到第一半導體裝置100的基板焊盤112的頂表面112a。第二半導體裝置200可以堆疊在第一半導體裝置100上。
在一些實例中，拾放設備（未示出）可以拾取第二半導體裝置200以將第二半導體裝置200放置在第一半導體裝置100的基板焊盤112的頂表面112a上。隨後，第二半導體裝置200可以通過質量回流、熱壓縮或雷射輔助接合來電連接到第一半導體裝置100。
在第二半導體裝置200的基板210中，可以在介電層212和214內提供具有大量導體、跡線或圖案的導電結構211、213和215。基板210示出為包括三個導電結構211、213和215以及兩個介電層212和214，但是基板210的導電層和介電層的數量可以更少或更多。基板210可以類似於重新分佈結構120或基板110並且可以類似地形成。基板210可以包括或被稱為重新分佈結構、中介件或印刷電路板。
在一些實例中，可以使用黏合劑將電子組件220的非主動區域黏接到基板210的頂表面，並且電子組件220的主動區域中的端子221可以通過呈例如引線形式的內部互連件222電連接到基板210的導電層215。在一些實例中，電子組件220的主動區域可以定位於其底表面處並且可以通過呈例如導電凸點或導電桿形式的內部互連件222以倒裝配置連接到基板210的導電結構215。電子組件220可以類似於電子組件120並且可以類似地形成為電子組件120。電子組件220可以通過內部互連件222和基板210電連接到互連件240。
囊封件230可以形成為覆蓋基板210的頂表面210a和電子組件220兩者。囊封件230可以類似於囊封件130並且可以類似地形成為囊封件130。
互連件240可以電連接到基板210的導電結構211。導電結構211可以類似於第二導電結構144並且可以類似地形成為第二導電結構144。互連件240可以類似於互連件150並且可以類似地形成為互連件150。互連件240可以使基板210和基板110彼此電連接。互連件240可以通過基板210電連接到電子組件220。互連件240可以通過基板110和重新分佈結構140電連接到電子組件120。互連件240可以使第一半導體裝置100和第二半導體裝置200彼此電連接。電子組件220可以通過基板210、互連件240、基板110、基板互連件117和重新分佈結構140電連接到互連件150。
本公開包含對某些實施例的引用。然而，所屬技術領域中具有通常知識者應理解的是，在不脫離本公開的範圍的情況下，可以作出各種改變並且可以取代等同物。另外，在不脫離本公開的範圍的情況下，可以對所公開的實施例進行修改。因此，本公開旨在並不受限於所公開的實例，而是本公開將包含落入所附申請專利範圍的範疇內的所有實施例。
10:載體 11:臨時接合層 100:半導體裝置/第一半導體裝置 100y:底表面 101:半導體封裝件 110:基板 110a:底表面 110b:頂表面 110X:基板 111:絕緣層 111a:底表面 111b:頂表面 112:基板焊盤 112a:底表面 113:基板襯墊 114:導電路徑 115:介電層 116:介電層 117:基板互連件 117b:頂表面 119:腔 120:電子組件 120a:底表面 120X:晶片 121:端子 122:組件互連件 122b:頂表面 130:囊封件 130a:底表面 130b:頂表面 140:重新分佈結構 141:介電結構 141X:孔洞 141Y:孔洞 142:導電結構 142b:頂表面 142X:導體 143:介電結構 143X:孔洞 144:導電結構 144b:頂表面 150:外部互連件 200:第二半導體裝置 202:半導體封裝件 210:基板 210a:頂表面 211:導電層/導電結構 212:介電層 213:導電層/導電結構 214:介電層 215:導電層/導電結構 220:電子組件 221:端子 222:內部互連件 230:囊封件 240:互連件 300:半導體裝置
[圖1]示出了示例半導體裝置的橫截面視圖。
[圖2A]到[圖2G]示出了用於製造示例半導體裝置的示例方法的橫截面視圖。
[圖3A]到[圖3C]示出了用於形成基板的示例方法的透視圖。
[圖4A]和[圖4B]示出了用於形成電子組件的示例方法的透視圖。
[圖5]示出了示例半導體裝置的橫截面視圖。
[圖6A]和[圖6B]示出了用於製造示例半導體裝置的示例方法的橫截面視圖。
100:半導體裝置/第一半導體裝置
101:半導體封裝件
110:基板
111:絕緣層
112:導電襯墊
113:導電襯墊
114:導電路徑
115:介電層
116:介電層
117:基板互連件
119:腔
120:電子組件
121:端子
122:組件互連件
130:囊封件
140:重新分佈結構
141:介電結構
142:導電結構
143:介電結構
144:導電結構
150:外部互連件

Claims (20)

  1. 一種半導體結構，其包括： 重新分佈結構，所述重新分佈結構包括導電結構； 腔基板，所述腔基板位於所述重新分佈結構的頂側上並且具有腔和與所述重新分佈結構接觸的柱； 電子組件，所述電子組件位於所述重新分佈結構的頂表面上和所述腔中，其中所述電子組件與所述導電結構電耦合；以及 囊封件，所述囊封件位於所述腔中和所述重新分佈結構的所述頂側上，所述囊封件接觸所述電子組件的側面、所述腔的側面以及所述柱的側面。
  2. 根據請求項1所述的半導體結構，其中： 所述重新分佈結構的所述頂側與所述腔基板的底側之間的第一距離不同於所述重新分佈結構的所述頂側與所述電子組件的底側之間的第二距離。
  3. 根據請求項1所述的半導體結構，其中所述腔基板在至少兩個側面上形成電子裝置的邊界。
  4. 根據請求項1所述的半導體結構，其中所述囊封件位於所述腔基板與所述重新分佈結構之間。
  5. 根據請求項4所述的半導體結構，其中所述囊封件位於所述電子組件與所述重新分佈結構之間。
  6. 根據請求項1所述的半導體結構，其進一步包括組件互連件，所述組件互連件將所述電子裝置與所述重新分佈結構的所述導電結構耦合，其中所述組件互連件的寬度小於所述柱的寬度。
  7. 根據請求項1所述的半導體結構，其中所述囊封件的頂側與所述電子組件的頂側共面。
  8. 根據請求項1所述的半導體結構，其中所述重新分佈結構包括重新分佈層基板。
  9. 根據請求項1所述的半導體結構，其中所述重新分佈結構包括重新分佈層基板，並且所述腔基板包括預形成的基板。
  10. 根據請求項1所述的半導體結構，其中所述腔基板的厚度大於所述重新分佈結構的厚度。
  11. 一種用於製造半導體結構的方法，所述方法包括： 提供具有腔和基板互連件的腔基板； 將具有組件互連件的電子組件放置在所述腔基板的所述腔中； 在所述腔基板的頂側上在所述腔中提供囊封件，所述囊封件接觸所述電子組件的側面、所述基板互連件和所述組件互連件；以及 在所述腔基板的所述頂側上提供重新分佈結構，其中所述重新分佈結構具有與所述基板互連件耦合的導電結構。
  12. 根據請求項11所述的方法，其進一步包括在提供所述重新分佈結構之前研磨所述囊封件和所述基板互連件的一部分。
  13. 根據請求項12所述的方法，其中所述研磨包含研磨所述組件互連件的一部分。
  14. 根據請求項11所述的方法，其中提供所述重新分佈結構包括： 在所述囊封件、所述腔基板和所述電子組件之上形成所述重新分佈結構的介電層；並且然後 在所述介電層之上形成所述重新分佈結構的導電層，所述導電層通過所述介電層耦合到所述腔基板和所述電子組件。
  15. 一種半導體結構，其包括： 第一半導體裝置，所述第一半導體裝置包括： 重新分佈結構，所述重新分佈結構包括導電結構； 第一基板，所述第一基板位於所述重新分佈結構的頂側上並且具有腔和接觸所述重新分佈結構的柱； 電子組件，所述電子組件位於所述重新分佈結構的頂表面上和所述腔中，其中所述電子組件通過組件互連件與所述導電結構電耦合；以及 囊封件，所述囊封件位於所述腔中和所述重新分佈結構的所述頂側上，所述囊封件形成所述電子組件和所述柱的側面的邊界；以及 第二半導體裝置，所述第二半導體裝置位於所述第一半導體裝置的頂側上，其中所述第二半導體裝置與所述第一基板的頂側上的基板焊盤電耦合。
  16. 根據請求項15所述的半導體結構，其中所述第二半導體裝置包括第二基板、第二電子組件以及第二囊封件，所述第二電子組件位於所述第二基板的頂側上，所述第二囊封件位於所述第二基板的所述頂側上，所述第二囊封件接觸所述第二電子組件的側面。
  17. 根據請求項15所述的半導體結構，其中所述重新分佈結構包括重新分佈層基板，並且所述第一基板包括預形成的基板。
  18. 根據請求項15所述的半導體結構，其中所述第一半導體裝置的所述柱包括導電桿，所述導電桿與所述重新分佈結構的所述導電結構和所述基板焊盤電耦合。
  19. 根據請求項15所述的半導體結構，其中所述第一基板在至少兩個側面上形成電子裝置的邊界。
  20. 根據請求項15所述的半導體結構，其中所述囊封件位於所述電子組件與所述重新分佈結構之間並且位於所述第一基板與所述重新分佈結構之間。
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