CN112310033A - 半导体装置及制造半导体装置的方法 - Google Patents

半导体装置及制造半导体装置的方法 Download PDF

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Publication number
CN112310033A
CN112310033A CN202010736607.1A CN202010736607A CN112310033A CN 112310033 A CN112310033 A CN 112310033A CN 202010736607 A CN202010736607 A CN 202010736607A CN 112310033 A CN112310033 A CN 112310033A
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substrate
cavity
electronic component
redistribution
redistribution structure
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林基泰
金杰云
周名佳
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Anrely Technology Singapore Holdings Pte Ltd
Amkor Technology Singapore Holding Pte Ltd
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Anrely Technology Singapore Holdings Pte Ltd
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Publication of CN112310033A publication Critical patent/CN112310033A/zh
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Abstract

半导体装置及制造半导体装置的方法。在一个实例中，一种半导体结构包括：重新分布结构，所述重新分布结构包括导电结构；腔衬底，所述腔衬底位于所述重新分布结构的顶侧上并且具有腔和接触所述重新分布结构的柱；电子组件，所述电子组件位于所述重新分布结构的顶表面上和所述腔中，其中所述电子组件与所述导电结构电耦合；以及包封件，所述包封件位于所述腔中和所述重新分布结构的所述顶侧上，所述包封件接触所述电子组件的侧面、所述腔的侧面以及所述柱的侧面。本文还公开了其它实例和相关方法。

Description

半导体装置及制造半导体装置的方法
技术领域
本公开总体上涉及电子装置，并且更具体地涉及半导体装置及用于制造半导体装置的方法。
背景技术
现有半导体封装和用于形成半导体封装的方法存在不足之处，例如造成成本过多、可靠性降低、性能相对较低或封装尺寸太大。对于本领域的技术人员来说，通过将常规和传统方法与本公开进行比较并且参考附图，此类方法的另外的局限性和缺点将变得明显。
发明内容
本揭露的各种态样提供一种半导体结构，其包括：重新分布结构，所述重新分布结构包括导电结构；腔衬底，所述腔衬底位于所述重新分布结构的顶侧上并且具有腔和与所述重新分布结构接触的柱；电子组件，所述电子组件位于所述重新分布结构的顶表面上和所述腔中，其中所述电子组件与所述导电结构电耦合；以及包封件，所述包封件位于所述腔中和所述重新分布结构的所述顶侧上，所述包封件接触所述电子组件的侧面、所述腔的侧面以及所述柱的侧面。在所述半导体结构中，所述重新分布结构的所述顶侧与所述腔衬底的底侧之间的第一距离不同于所述重新分布结构的所述顶侧与所述电子组件的底侧之间的第二距离。在所述半导体结构中，所述腔衬底在至少两个侧面上形成电子装置的边界。在所述半导体结构中，所述包封件位于所述腔衬底与所述重新分布结构之间。在所述半导体结构中，所述包封件位于所述电子组件与所述重新分布结构之间。所述半导体结构进一步包括组件互连件，所述组件互连件将所述电子装置与所述重新分布结构的所述导电结构耦合，其中所述组件互连件的宽度小于所述柱的宽度。在所述半导体结构中，所述包封件的顶侧与所述电子组件的顶侧共面。在所述半导体结构中，所述重新分布结构包括重新分布层(RDL)衬底。在所述半导体结构中，所述重新分布结构包括重新分布层衬底，并且所述腔衬底包括预形成的衬底。在所述半导体结构中，所述腔衬底的厚度大于所述重新分布结构的厚度。
本揭露的各种态样提供一种用于制造半导体结构的方法，所述方法包括：提供具有腔和衬底互连件的腔衬底；将具有组件互连件的电子组件放置在所述腔衬底的所述腔中；在所述腔衬底的顶侧上在所述腔中提供包封件，所述包封件接触所述电子组件的侧面、所述衬底互连件和所述组件互连件；以及在所述腔衬底的所述顶侧上提供重新分布结构，其中所述重新分布结构具有与所述衬底互连件耦合的导电结构。所述方法进一步包括在提供所述重新分布结构之前研磨所述包封件和所述衬底互连件的一部分。在所述方法中，所述研磨包含研磨所述组件互连件的一部分。在所述方法中，提供所述重新分布结构包括：在所述包封件、所述腔衬底和所述电子组件之上形成所述重新分布结构的介电层；并且然后在所述介电层之上形成所述重新分布结构的导电层，所述导电层通过所述介电层耦合到所述腔衬底和所述电子组件。
本揭露的各种态样提供一种半导体结构，其包括：第一半导体装置，所述第一半导体装置包括：重新分布结构，所述重新分布结构包括导电结构；第一衬底，所述第一衬底位于所述重新分布结构的顶侧上并且具有腔和接触所述重新分布结构的柱；电子组件，所述电子组件位于所述重新分布结构的顶表面上和所述腔中，其中所述电子组件通过组件互连件与所述导电结构电耦合；以及包封件，所述包封件位于所述腔中和所述重新分布结构的所述顶侧上，所述包封件形成所述电子组件和所述柱的侧面的边界；以及第二半导体装置，所述第二半导体装置位于所述第一半导体装置的顶侧上，其中所述第二半导体装置与所述第一衬底的顶侧上的衬底焊盘电耦合。在所述半导体结构中，所述第二半导体装置包括第二衬底、第二电子组件以及第二包封件，所述第二电子组件位于所述第二衬底的顶侧上，所述第二包封件位于所述第二衬底的所述顶侧上，所述第二包封件接触所述第二电子组件的侧面。在所述半导体结构中，所述重新分布结构包括重新分布层衬底，并且所述第一衬底包括预形成的衬底。在所述半导体结构中，所述第一半导体装置的所述柱包括导电桩，所述导电桩与所述重新分布结构的所述导电结构和所述衬底焊盘电耦合。在所述半导体结构中，所述第一衬底在至少两个侧面上形成电子装置的边界。在所述半导体结构中，所述包封件位于所述电子组件与所述重新分布结构之间并且位于所述第一衬底与所述重新分布结构之间。
附图说明
图1示出了示例半导体装置的横截面视图。
图2A到图2G示出了用于制造示例半导体装置的示例方法的横截面视图。
图3A到图3C示出了用于形成衬底的示例方法的透视图。
图4A和图4B示出了用于形成电子组件的示例方法的透视图。
图5示出了示例半导体装置的横截面视图。
图6A和图6B示出了用于制造示例半导体装置的示例方法的横截面视图。
具体实施方式
以下讨论提供了半导体装置及制造半导体装置的方法的各种实例。此类实例是非限制性的，并且所附权利要求的范围不应限于所公开的特定实例。在以下讨论中，术语“实例”和“例如”是非限制性的。
附图展示了一般的构造方式，并且可以省略公知特征和技术的描述和细节，以避免不必要地模糊本公开。另外，附图中的元件不一定按比例绘制。例如，图中元件中的一些元件的尺寸可能相对于其它元件而被放大以有助于改善对本公开所讨论的实例的理解。不同附图中的相同附图标记指示相同的元件。
术语“或”意味着由“或”连接的列表中的项目的任何一个或多个项目。作为实例，“x或y”意味着三元素集合{(x),(y),(x,y)}中的任何元素。作为另一个实例，“x、y或z”意味着七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。
术语“包括(comprises)”、“包括(comprising)”、“包含(includes)”和/或“包含(including)”是“开放式”术语并且指定存在所陈述的特征，但不排除存在或增加一个或多个其它特征。在本文中可以使用术语“第一”、“第二”等来描述各种元件，并且这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件进行区分。因此，例如，在不背离本公开的教导的情况下，本公开中所讨论的第一元件可以被称为第二元件。
除非另外指明，否则术语“耦合”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。例如，如果元件A耦合到元件B，则元件A可以直接接触元件B或通过中间元件C间接连接到元件B。类似地，术语“之上”或“上”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。如共面、平面、垂直、竖直、水平等几何描述性术语不仅涵盖此类确切术语，还涵盖此类术语的例如，在制造公差范围内的基本上近似情况。
在一个实例中，一种半导体结构包括：重新分布结构，所述重新分布结构包括导电结构；腔衬底，所述腔衬底位于所述重新分布结构的顶侧上并且具有腔和接触所述重新分布结构的柱；电子组件，所述电子组件位于所述重新分布结构的顶表面上和所述腔中，其中所述电子组件与所述导电结构电耦合；以及包封件，所述包封件位于所述腔中和所述重新分布结构的所述顶侧上，所述包封件接触所述电子组件的侧面、所述腔的侧面以及所述柱的侧面。
在另一个实例中，一种用于制造半导体结构的方法包括提供具有腔和衬底互连件的腔衬底；将具有组件互连件的电子组件放置在所述腔衬底的所述腔中；在所述腔衬底的顶侧上在所述腔中提供包封件，所述包封件接触所述电子组件的侧面、所述衬底互连件和所述组件互连件；以及在所述腔衬底的所述顶侧上提供重新分布结构，其中所述重新分布结构具有与所述衬底互连件耦合的导电结构。
在另外的实例中，一种半导体结构包括：第一半导体装置，所述第一半导体装置包括：重新分布结构，所述重新分布结构包括导电结构；第一衬底，所述第一衬底位于所述重新分布结构的顶侧上并且具有腔和接触所述重新分布结构的柱；电子组件，所述电子组件位于所述重新分布结构的顶表面上和所述腔中，其中所述电子组件通过组件互连件与所述导电结构电耦合；以及包封件，所述包封件位于所述腔中和所述重新分布结构的所述顶侧上，所述包封件形成所述电子组件和所述柱的侧面的边界。半导体结构还包括第二半导体装置，所述第二半导体装置位于所述第一半导体装置的顶侧上，其中所述第二半导体装置与所述第一衬底的顶侧上的衬底焊盘电耦合。
本公开中包含其它实例。此类实例可以存在于本公开的附图中、权利要求中和/或说明书中。
图1示出了示例半导体装置的横截面视图。在图1所示的实例中，半导体装置100可以包括衬底110、电子组件120、包封件130、重新分布结构140和外部互连件150。
衬底110可以包括绝缘层111、导电衬垫112和113、导电路径114、介电层115和116以及衬底互连件117。电子组件120可以包括组件互连件122。重新分布结构140可以包括介电结构141和143以及导电结构142和144。
衬底110、包封件130、重新分布结构140和外部互连件150可以包括或被称为半导体封装101或封装101，并且半导体封装101可以为电子组件120提供保护以免受到外部元件和/或环境暴露。另外，半导体封装101可以提供外部组件与电子组件120之间的电耦合。
在一些实例中，电子组件120的顶侧可以与包封件130的顶侧共面。在一些实例中，共面可以意指在制造公差内，电子组件的顶侧总体上可以与包封件130的顶侧位于同一平面内。例如，电子组件120的顶侧可以稍微凸出到包封件130的顶侧上方，或者电子组件120的顶侧可以相对于包封件130的顶侧稍微凹陷，同时在此类公差内保持共面。应注意，这些仅仅是描述电子组件的顶侧与包封件130的顶侧之间的关系的实例，并且本公开的范围不限于这些方面。
在一些实例中，重新分布结构140可以包括导电结构142或144，并且衬底110可以包括位于重新分布结构140的顶侧上的腔衬底，所述腔衬底具有填充有包封件130的腔119和接触重新分布结构140的柱117。电子组件120可以位于重新分布结构140的顶表面上和腔119中，其中电子组件120与导电结构142或144电耦合。包封件可以位于腔119中和重新分布结构140的顶侧上，所述包封件接触电子组件120的侧面、腔119的侧面以及柱117的侧面。
图2A到2G示出了用于制造示例半导体装置100的示例方法的横截面视图。图3A到3C示出了用于形成图2A所示的衬底110的示例方法的透视图。图4A和4B示出了用于形成图2B所示的电子组件120的示例方法的透视图。
图2A示出了处于早期制造阶段的半导体装置100的横截面视图。图3A到图3C示出了用于形成衬底110的示例方法的透视图。
在图2A所示的实例中，载体10可以是基本上平面的板。在一些实例中，载体10可以包括或被称为板、晶片、面板或条带。在一些实例中，载体10可以包括例如但不限于钢、不锈钢、铝、铜、陶瓷、玻璃、半导体或晶片。载体10的厚度可以在大约1毫米(mm)到大约1.5mm的范围并且宽度内可以在大约200mm到大约320mm的范围内。
载体10可以用于以将衬底110附接到电子组件120的集成方式处理多个组件，从而形成包封件130并且形成重新分布结构140。载体10通常可以应用于本公开所公开的不同实例。电子组件120可以具有组件互连件122并且可以放置在腔衬底110的腔119中。可以在腔衬底110的顶侧上在腔119中提供包封件130，其中包封件130可以接触电子组件120的侧面、衬底互连件117的侧面和组件互连件122的侧面。然后，可以在腔衬底110的顶侧上提供重新分布结构140。重新分布结构140可以具有与衬底互连件117耦合的导电结构144或144。
可以在载体10的表面上提供临时接合层11。可以使用如以下涂覆工艺在载体10的表面上提供临时接合层11：旋涂、刮刀、铸造、刷涂、喷涂、狭缝式涂覆(slot die coating)、帘幕式涂覆(curtain coating)、斜板式涂覆(slide coating)或边缘刮刀式涂覆(knifeover edge coating)；印刷工艺，如丝网印刷、移印工艺、凹版印刷、柔性版涂覆或胶版印刷；喷墨印刷工艺；或粘合膜或胶带的直接附接。临时接合层11可以包括或被称为临时粘合膜或临时胶带。临时接合层11可以是例如但不限于可热释放膜或紫外线(UV)可释放膜，其接合强度可能被弱化，或者可以通过加热或UV照射来去除。在一些实例中，临时接合层11可以具有弱化的结合强度或者可以通过物理和/或化学外力去除。临时接合层11的厚度可以在大约50微米(μm)到大约100μm的范围内。临时接合层11可以在形成重新分布结构140之后使载体10分离，这将在稍后描述。临时接合层11通常可以应用于本公开所公开的不同实例。
可以将具有衬底互连件117和限定腔119的衬底110附接到临时接合层11。衬底110可以包括绝缘层111、导电衬垫112和113、导电路径114、介电层115和116以及衬底互连件117。在一些实例中，可以省略导电衬垫112和113、导电路径114或介电层115和116中的至少一个。另外，衬底110可以包括延伸通过顶表面110b与底表面110a之间的区域的腔119。
在一些实例中，衬底110可以包括或被称为印刷电路板(PCB)、腔衬底、印刷布线板、多层衬底、通孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或预模制引线框。在一些实例中，可以提供具有腔119和衬底互连件117的腔衬底110。
在一些实例中，绝缘层111可以具有基本上平面的顶表面111b和底表面111a。在一些实例中，绝缘层111可以包括或被称为介电层或芯层。在一些实例中，绝缘层111可以包括环氧树脂、酚树脂、玻璃环氧树脂、聚酰亚胺、聚酯、环氧模制化合物或硅树脂或陶瓷。在一些实例中，绝缘层111的厚度可以在大约10μm到大约500μm的范围内。绝缘层111可以将衬底110保持在基本上平面的状态或者可以限制弯曲，并且还可以在衬底110的导体之间提供绝缘。
可以在绝缘层111的底表面111a上形成导电衬垫112，并且可以在绝缘层111的顶表面111b上形成导电衬垫113。导电衬垫112和113可以以具有行和/或列的矩阵配置形成于绝缘层111的底表面111a和顶表面111b上。在一些实例中，导电衬垫112或113可以包括或被称为导体、导电材料、衬底焊盘、导电焊盘、衬底衬垫、引线衬垫、连接衬垫、微衬垫、迹线或凸点下金属(UBM)。在一些实例中，衬底焊盘112和衬底衬垫113可以包括铜、铁、镍、金、银、钯或锡。在一些实例中，衬底焊盘112和衬底衬垫113的厚度、宽度和空间可以在大约50μm到大约500μm的范围内。
在一些实例中，导电路径114可以电连接衬底焊盘112和衬底衬垫113，同时延伸通过绝缘层111。在一些实例中，导电路径114可以包括或被称为导体、导电材料、导电通孔、电路图案或导电桩。在一些实例中，导电路径114可以包括铜、铁、镍、金、银、钯或锡。在一些实例中，导电路径114的厚度可以在大约10μm到大约500μm的范围内。
如图2A和图2B所示，介电层115可以大致覆盖衬底焊盘112的部分和绝缘层111的底表面111a，并且介电层116可以大致覆盖衬底衬垫113的部分和绝缘层111的顶表面111b。在一些实例中，介电层115和116可以包括或被称为电介质、介电材料、介电层、绝缘层、焊接掩膜或阻焊剂。在一些实例中，可以通过介电层115暴露衬底焊盘112的要连接到另一个半导体装置的部分。另外，可以通过介电层116暴露衬底衬垫113的要连接到衬底互连件117的部分。在一些实例中，介电层115和116可以包括聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模制材料、酚树脂、环氧树脂、硅树脂或丙烯酸酯聚合物。在一些实例中，介电层115和116的厚度可以在大约10μm到大约100μm的范围内。介电层115可以用于保护接近衬底110的底表面110a的导体，并且介电层116可以用于保护接近衬底110的顶表面110b的导体。
图2A和图3A示出了用于在衬底110X上形成或提供衬底互连件117的示例方法。衬底110X可以用于一次制造大量具有大量衬底互连件117和大量腔119的单独衬底110。
在图2A和图3A所示的实例中，衬底110，包含绝缘层111、衬底焊盘112、衬底衬垫113、导电路径114和介电层115和116可以具有电连接到衬底衬垫113的衬底互连件117。
可以在衬底衬垫113的顶表面上形成衬底互连件117。与衬底衬垫113相似，可以以具有行或列的矩阵配置形成衬底互连件117。衬底互连件117可以形成为从衬底衬垫113向上延伸。在一些实例中，衬底互连件117的高度可以在大约0.1mm到大约0.5mm的范围内并且宽度可以在大约0.2mm到大约1mm的范围内。
在一些实例中，可以通过但不限于电镀、化学镀、溅射、PVD、CVD、MOCVD、ALD、LPCVD或PECVD形成衬底互连件117。在一些实例中，衬底互连件117可以包括铜、金、银、钯、镍或焊料。衬底互连件117可以包括或被称为柱、桩、栏、通孔、竖直引线、凸点或导电路径。在一些实例中，衬底互连件117可以将稍后要描述的重新分布结构140电连接或机械连接到衬底110。
图2A和图3B示出了用于在衬底110X上形成腔119的示例方法。在图2A和图3B所示的实例中，可以在衬底110X上形成延伸通过衬底110X的顶表面110b和底表面110a的腔119。可以以具有行或列的矩阵配置形成腔119。可以以矩形形状或与电子组件120相对应的形状形成腔119。可以在衬底110X上中在包含层111和介电层115和116的区域中形成腔119。可以在衬底110X的顶表面110b上定位衬底互连件117，以便在腔119周围在行方向和/列方向上间隔开。在一些实例中，腔119的大小可以在大约1mm到大约10mm的范围内。
图2A和3C示出了用于将衬底110X单切成各自具有腔119的单独衬底110的实例方法。在一些实例中，可以使用金刚石刀片或激光束将衬底110X单切成单独衬底110。可以通过临时接合层11将单独衬底110中的具有一个腔119的每个单独衬底的底表面110a附接到图2A所示的载体10。衬底110可以具有大致定位于其中心的腔119或可以是矩形环。另外，在行方向或列方向上彼此间隔开的衬底互连件117可以定位于腔119的在衬底110的顶表面上形成的相应侧之外。
图2B示出了处于后期制造阶段的半导体装置100的横截面视图。图4A和图4B示出了用于形成或提供电子组件120的示例方法的透视图。在图2B所示的实例中，可以将具有组件互连件122的电子组件120附接到载体10的临时接合层11。可以在电子组件120的顶表面上提供大量端子121，并且组件互连件122可以分别电连接到大量端子121。端子121可以是电子组件120的输入/输出端子并且可以包括或被称为管芯衬垫或接合衬垫。在一些实例中，端子121的宽度可以在大约50μm到大约500μm的范围内。
图4A示出了用于形成要电连接到电子组件120的端子121的组件互连件122的示例方法。在图2B和图4A所示的实例中，可以制备具有电子组件120的晶片120X，并且可以在晶片120X的顶表面上形成组件互连件122以电连接到电子组件120的端子121。可以分别在端子121的顶表面上形成组件互连件122。另外，可以在晶片120X的制造期间形成组件互连件122。
与端子121相似，可以以具有行或列的矩阵配置形成组件互连件122。组件互连件122可以形成为从端子121向上延伸。在一些实例中，组件互连件122的高度可以在大约20μm到大约150μm的范围内并且宽度可以在大约0.05mm到大约1mm的范围内。在制造晶片120X期间形成组件互连件122，并且组件互连件122的大小和宽度可以小于衬底互连件117的大小和宽度。
在一些实例中，可以通过但不限于电镀、化学镀、溅射、PVD、CVD、MOCVD、ALD、LPCVD或PECVD形成组件互连件122。在一些实例中，组件互连件122可以包括铜、金、银、钯、镍或焊料。组件互连件122可以包括或被称为柱、桩、栏、凸点或导电路径。在一些实例中，组件互连件122可以将稍后要描述的重新分布结构140电连接或机械连接到电子组件120。
图4B示出了用于将具有组件互连件122的晶片120X单切成单独的电子组件120的示例方法。在图2B和图4B所示的实例中，可以将具有组件互连件122的晶片120X单切成单独的电子组件120。在一些实例中，可以使用金刚石刀片或激光束将晶片120X划分为单独的电子组件120。
可以通过临时接合层11将具有组件互连件122的电子组件120中的每个电子组件的底表面120a附接到图2B所示的载体10。可以在衬底110的腔119内定位电子组件120。电子组件120的大小可以小于腔119的大小。电子组件120的侧表面可以与衬底110间隔开。
电子组件120可以包括或被称为半导体管芯、半导体芯片或半导体封装，如芯片级封装(chip-scale package)。在一些实例中，电子组件120可以包括专用集成电路、逻辑管芯、微控制单元、存储器、数字信号处理器、网络处理器、电源管理单元、音频处理器、射频(RF)电路或无线基带片上系统处理器中的至少一个。电子组件120的厚度可以在大约50μm到大约780μm的范围内。电子组件120的大小可以在大约3mm到大约10mm的范围内。
图2C示出了处于后期制造阶段的半导体装置100的横截面视图。在图2C所示的实例中，包封件130可以形成为完全覆盖衬底110和电子组件120。在一些实例中，包封件130可以接触衬底110的顶表面110b，可以填充腔119，并且接触衬底互连件117的侧表面和顶表面。在一些实例中，包封件130可以接触电子组件120的侧表面或者可以接触组件互连件122的侧表面和顶表面两者。
在一些实例中，包封件130可以包括或被称为环氧模制化合物、环氧树脂、保护性电介质或密封剂。另外，在一些实例中，包封件130可以包括或被称为模制部件、密封部件、包封部件、保护部件或封装主体。在一些实例中，包封件130可以包括但不限于有机树脂、无机填料、固化剂、催化剂、偶联剂、着色剂或阻燃剂。包封件130可以通过各种工艺中的任何工艺形成。在一些实例中，包封件130可以通过但不限于压缩模制、传递模制、液相包封件模制、真空层压、膏印刷或膜辅助模制形成。包封件130的厚度可以在大约0.1mm到大约1mm的范围内。包封件130可以形成为覆盖衬底110和电子组件120以保护衬底110和电子组件120免受外部元件和/或环境暴露。
图2D示出了处于后期制造阶段的半导体装置100的横截面视图。在图2D所示的实例中，可以去除包封件130的上部部分以暴露衬底互连件117的顶表面117b和位于包封件130的顶表面130b处的组件互连件122的顶表面122b。可以通过研磨或化学蚀刻来去除包封件130。还可以去除衬底互连件117的上部部分和组件互连件122的上部部分。包封件130的顶表面130b可以与衬底互连件117的顶表面117b和组件互连件122的顶表面122b共面。其上部部分去除的包封件130的厚度可以在大约10μm到大约100μm的范围内。
图2E示出了处于后期制造阶段的半导体装置100的横截面视图。在图2E所示的实例中，可以在包封件130的顶表面130b、衬底互连件117的顶表面117b和组件互连件122的顶表面122b上形成重新分布结构140。在一些实例中，重新分布结构140可以类似于衬底110，或者可以包括或被称为衬底。重新分布结构140可以包括按顺序形成的第一介电结构141、第一导电结构142、第二介电结构143和第二导电结构144。在重新分布结构140中，第一电介质结构141可以首先形成为覆盖包封件130的顶表面130b、衬底互连件117的顶表面117b和组件互连件122的顶表面122b到基本上均匀的厚度。另外，可以在第一介电结构141中形成孔口141X和141Y以暴露衬底互连件117的顶表面117b和组件互连件122的顶表面122b。
第一介电结构141或第二介电结构143可以包括或被称为电介质、介电材料、介电层、钝化层、绝缘层或保护层。在一些实例中，第一介电结构141或第二介电结构143可以包括但不限于电绝缘材料，如聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模制材料、酚树脂、环氧树脂、硅树脂或丙烯酸酯聚合物。另外，在一些实例中，可以通过各种工艺中的任何工艺来形成第一介电结构141或第二介电结构143。在一些实例中，可以通过旋涂、喷涂、印刷、PVD、CVD、MOCVD、ALD、LPCVD或PECVD形成第一介电结构141或第二介电结构143。第一介电结构(即，钝化层)141或第二介电结构143的厚度可以在约1μm到大约20μm的范围内。
在一些实例中，可以在第一介电结构141的顶表面上形成掩模图案，并且然后可以通过蚀刻去除第一介电结构141的区域，从而形成孔口141X和141Y。孔口141X和141Y可以包括或被称为开口或孔。第一介电结构141可以通过孔口141X暴露衬底互连件117的顶表面117b并且可以通过孔口141Y暴露组件互连件122的顶表面122b。在一些实例中，可以将光刻胶用作掩模图案。通过孔口141X和141Y暴露的衬底互连件117的顶表面117b和组件互连件122的顶表面122b可以具有圆形、矩形或多边形形状。
重新分布结构140可以具有第一导电结构142，所述第一导电结构形成为覆盖第一介电结构141的顶表面以及衬底互连件117的顶表面117b和组件互连件122的顶表面122b，这些顶表面通过孔口141X和141Y暴露。
第一导电结构142可以由大量导体、迹线或图案形成，并且可以使相应导体与衬底互连件117的顶表面117b或者组件互连件122的顶表面122b(如通过孔口141X和141Y所暴露)接触。导体或第一导电结构142可以通过衬底互连件117电连接到衬底110，或者通过组件互连件122电连接到电子组件120。第一导电结构142可以包括导体142X，所述导体使衬底互连件117的顶表面117b与组件互连件122的顶表面122b电连接。导体142X可以从电子组件120之上的点延伸到衬底110之上的点并且可以将电子组件120和衬底110彼此电连接。
在一些实例中，第一导电结构142或第二导电结构144可以包括或被称为导体、导电材料、导电层、重新分布层(RDL)、布线图案、迹线图案或电路图案。在一些实例中，导体142X可以包括或被称为扇出路径，其在电子组件120的占用空间内延伸并且延伸超过所述占用空间。在一些实例中，第一导电结构142或第二导电结构144可以由各种导电材料中的任何导电材料制成，所述各种导电材料包含例如铜、金、银或等同物。第一导电结构142或第二导电结构可以通过各种工艺中的任何工艺形成，所述各种工艺包含例如溅射、化学镀、电镀、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物。第一导电结构142可以形成为用于覆盖第一介电结构141的顶表面、衬底互连件117的顶表面117b和组件互连件122的顶表面122b的预定厚度，所述顶表面通过孔口141X和141Y暴露，并且所述第一导电结构可以通过掩膜图案来图案化以限定大量导体。第一导电结构142的厚度可以在大约5μm到大约50μm的范围内。
重新分布结构140可以具有第二介电结构143，所述第二介电结构形成为覆盖第一介电结构141和第一导电结构142到基本上均匀的厚度。可以在第二介电结构143中形成暴露第一导电结构142的顶表面142b的孔口143X。第二介电结构143还可以通过孔口143X暴露导体142X的顶表面。第二介电结构143可以类似于第一介电结构141并且可以类似地形成为第一介电结构141。
重新分布结构140可以具有第二导电结构144，所述第二导电结构形成为覆盖第一导电结构142的通过孔口143X暴露的顶表面142b。第二导电结构144可以由大量导体、迹线或图案形成，并且可以使相应导体与第一导电结构142的如通过孔口143X暴露的顶表面142b接触。第二导电结构144可以形成为部分覆盖第二介电结构143的顶表面。第二导电结构144可以通过第一导电结构142电连接到衬底互连件117和/或组件互连件122。第二导电结构144可以包括或被称为导体、导电材料、导电层、导电衬垫、微衬垫、接合衬垫、导电桩或凸点下金属(UBM)。第二导电结构144可以类似于第一导电结构142并且可以类似地形成为第一导电结构142。作为实例，示出了包括两个介电结构141和143以及两个导电结构142和144的重新分布结构140，但是重新分布结构140可以包括少于或多于介电结构141和143或导电结构142和144。
在本发明的实例中，衬底140呈现为重新分布层(“RDL”)衬底。RDL衬底可以包括(a)可以在RDL衬底要电耦合到的电子装置之上逐层形成的，或者(b)可以在可以在将电子装置和RDL衬底耦合在一起之后完全去除或至少部分地去除的载体之上逐层形成的一个或多个导电重新分布层和一个或多个介电层。RDL衬底可以在圆形晶片上以晶片级工艺逐层制造为晶片级衬底，和/或在矩形或方形面板载体上以面板级工艺逐层制造为面板级衬底。RDL衬底可以以可以包含与限定相应的导电重新分布图案或迹线的一个或多个导电层交替堆叠的一个或多个介电层的添加剂堆积工艺形成，所述导电重新分布图案或迹线被配置成共同(a)将电迹线扇出电子装置的占用空间外，和/或(b)将电迹线扇入电子装置的占用空间内。可以使用镀覆工艺，例如电镀工艺或化学镀工艺来形成导电图案。导电图案可以包括导电材料，例如铜或其它可镀覆金属。可以使用光图案化工艺，例如光刻工艺和用于形成光刻掩模的光刻胶材料来制作导电图案的位置。可以利用可以包含光刻掩模的光图案化工艺来图案化RDL衬底的介电层，光通过所述光刻掩模暴露到光图案期望的特征，如介电层中的通孔中。介电层可以由光可限定的有机介电材料，例如聚酰亚胺(PI)、苯并环丁烯(BCB)或聚苯并恶唑(PBO)制成。此类介电材料可以以液体形式旋涂或以其它方式涂覆，而不是以预形成的膜的形式附接。为了允许适当地形成期望的光限定的特征，此类光可限定的介电材料可以省略结构增强剂，或者可以是不含填料的，没有可能会干扰来自光图案化工艺的光的线、织物或其它颗粒。在一些实例中，不含填料的介电材料的此类不含填料的特性可以允许减小所得的介电层的厚度。尽管上文描述的光可限定的介电材料可以是有机材料，但是在其它实例中，RDL衬底的介电材料可以包括一个或多个无机介电层。一个或多个无机介电层的一些实例可以包括氮化硅(Si3N4)、氧化硅(SiO2)和/或SiON。所述一个或多个无机介电层可以通过使用氧化或氮化工艺而不是使用光限定的有机介电材料来增长无机介电层形成。此类无机介电层可以是不含填料的，没有线、织物或其它不同的无机颗粒。在一些实例中，RDL衬底可以省略永久性芯结构或载体，例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料，并且这些类型的RDL衬底可以被称为无芯衬底。本公开中的其它衬底也可以包括RDL衬底。
在一些实例中，衬底140可以是预形成的衬底。预形成的衬底可以在附接到电子装置之前制造并且可以包括位于相应的导电层之间的介电层。导电层可以包括铜并且可以使用电镀工艺形成。介电层可以是可以以预形成的膜的形式而不是以液体的形式附接的相对较厚的非光可限定层，并且可以包含用于刚性和/或结构性支撑的具有如线、织物和/或其它无机颗粒等填料的树脂。由于介电层是非光可限定的，因此可以通过使用钻孔或激光来形成如通孔或开口等特征。在一些实例中，介电层可以包括预浸材料或味之素增层膜(ABF)。预形成的衬底可以包含永久性芯结构或载体，例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料，并且介电层和导电层可以形成于永久性芯结构上。在其它实例中，预形成的衬底可以是省略永久性芯结构的无芯衬底，并且介电层和导电层可以形成于在形成介电层和导电层之后并且在附接到电子装置之前被去除的牺牲载体上。预形成的衬底可以被称为印刷电路板(PCB)或层压衬底。此类预形成的衬底可以通过半加成法工艺或经改进的半加成法工艺形成。本公开中的其它衬底也可以包括预形成的衬底。
图2F示出了处于后期制造阶段的半导体装置100的横截面视图。在图2F所示的实例中，可以从衬底110的底表面110a、电子组件120的底表面120a和包封件130的底表面130a去除载体10。在临时接合层11附接到载体10的状态下，可以从衬底110、电子组件120和包封件130去除载体10。在一些实例中，可以通过提供热、光、化学溶液或物理外力来去除或弱化临时接合层11的粘附性。因此，可以暴露衬底110的底表面110a、电子组件120的底表面120a和包封件130的底表面130a。另外，还可以暴露衬底焊盘112的底表面112a。
图2G示出了处于后期制造阶段的半导体装置100的横截面视图。在图2G所示的实例中，可以在第二导电结构144的顶表面144b上提供外部互连件150。外部互连件150可以电连接到第二导电结构144的顶表面144b。外部互连件150可以通过重新分布结构140和衬底互连件117电连接到衬底110，或者通过重新分布结构140和组件互连件122电连接到电子组件120。另外，外部互连件150可以通过重新分布结构140的导体142X电连接到衬底110和电子组件120两者。
在一些实例中，外部互连件150可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。外部互连件150可以通过例如球落、丝网印刷或电镀形成。例如，外部互连件150可以通过球落在重新分布结构140的第二导电结构144的顶表面144b上形成含有焊料的导电材料，然后执行回流工艺来形成。外部互连件150可以包括或被称为如焊球等导电球、如铜柱等导电柱，或具有在铜柱上形成的焊帽的导电桩。外部互连件150的大小可以在大约0.1mm到大约0.5mm的范围内。另外，已完成的半导体装置100可以翻转，并且外部互连件150可以定位于半导体装置100的衬底100的底表面100y上。在一些实例中，外部互连件150可以包括或被称为半导体装置100的外部输入/输出端子。
现在参考图5，示出了示例性半导体装置300的横截面视图。在图5所示的实例中，半导体装置300可以包括第一半导体装置100和第二半导体装置200。第一半导体装置100可以与图1所示的半导体装置100相同。第二半导体装置200可以包括衬底210、电子组件220、包封件230和互连件240。第一半导体装置100可以包括重新分布结构140、第一衬底110，所述重新分布结构包括导电结构142或144，所述第一衬底位于重新分布结构140的顶侧并且具有腔119和接触重新分布结构140的柱。电子组件120可以位于重新分布结构140的顶表面上和腔119中，其中电子组件120可以通过组件互连件122与导电结构142或144电耦合。包封件130可以位于腔119中和重新分布结构140的顶侧上，所述包封件形成电子组件120和柱117的侧面的边界。
第二半导体装置200可以位于第一半导体装置100的顶侧上，其中第二半导体装置200可以在第一半导体装置100的顶侧上与衬底焊盘112电耦合。参考第二半导体装置200，衬底210可以包括介电层212和214以及导电层211、213和215。电子组件220可以包括端子221和内部互连件222。衬底210、包封件230和互连件240可以包括或被称为半导体封装202并且可以为电子组件220提供保护以免受到外部元件或环境暴露。另外，半导体封装202可以提供外部组件与电子组件220之间的电耦合。
图6A和6B示出了用于制造示例半导体装置的示例方法的横截面视图。图6A示出了处于早期制造阶段的半导体装置300的横截面视图。
在图6A所示的实例中，可以制备半导体装置100。用于制造图6A所示的第一半导体装置100的示例方法可以类似于制造图2A到2G、图3A到3C和图4A和4B所示的半导体装置100的示例方法。
在图6A和图6B所示的实例中，可以将第二半导体装置200的互连件240电连接到第一半导体装置100的衬底焊盘112的顶表面112a。第二半导体装置200可以堆叠在第一半导体装置100上。
在一些实例中，拾放设备(未示出)可以拾取第二半导体装置200以将第二半导体装置200放置在第一半导体装置100的衬底焊盘112的顶表面112a上。随后，第二半导体装置200可以通过质量回流、热压缩或激光辅助接合来电连接到第一半导体装置100。
在第二半导体装置200的衬底210中，可以在介电层212和214内提供具有大量导体、迹线或图案的导电结构211、213和215。衬底210示出为包括三个导电结构211、213和215以及两个介电层212和214，但是衬底210的导电层和介电层的数量可以更少或更多。衬底210可以类似于重新分布结构120或衬底110并且可以类似地形成。衬底210可以包括或被称为重新分布结构、中介件或印刷电路板。
在一些实例中，可以使用粘合剂将电子组件220的非有源区域粘附到衬底210的顶表面，并且电子组件220的有源区域中的端子221可以通过呈例如引线形式的内部互连件222电连接到衬底210的导电层215。在一些实例中，电子组件220的有源区域可以定位于其底表面处并且可以通过呈例如导电凸点或导电桩形式的内部互连件222以倒装配置连接到衬底210的导电结构215。电子组件220可以类似于电子组件120并且可以类似地形成为电子组件120。电子组件220可以通过内部互连件222和衬底210电连接到互连件240。
包封件230可以形成为覆盖衬底210的顶表面210a和电子组件220两者。包封件230可以类似于包封件130并且可以类似地形成为包封件130。
互连件240可以电连接到衬底210的导电结构211。导电结构211可以类似于第二导电结构144并且可以类似地形成为第二导电结构144。互连件240可以类似于互连件150并且可以类似地形成为互连件150。互连件240可以使衬底210和衬底110彼此电连接。互连件240可以通过衬底210电连接到电子组件220。互连件240可以通过衬底110和重新分布结构140电连接到电子组件120。互连件240可以使第一半导体装置100和第二半导体装置200彼此电连接。电子组件220可以通过衬底210、互连件240、衬底110、衬底互连件117和重新分布结构140电连接到互连件150。
本公开包含对某些实例的引用。然而，本领域的技术人员应理解的是，在不脱离本公开的范围的情况下，可以作出各种改变并且可以取代等同物。另外，在不脱离本公开的范围的情况下，可以对所公开的实例进行修改。因此，本公开旨在并不受限于所公开的实例，而是本公开将包含落入所附权利要求的范围内的所有实例。

Claims (20)

1.一种半导体结构，其包括：
重新分布结构，所述重新分布结构包括导电结构；
腔衬底，所述腔衬底位于所述重新分布结构的顶侧上并且具有腔和与所述重新分布结构接触的柱；
电子组件，所述电子组件位于所述重新分布结构的顶表面上和所述腔中，其中所述电子组件与所述导电结构电耦合；以及
包封件，所述包封件位于所述腔中和所述重新分布结构的所述顶侧上，所述包封件接触所述电子组件的侧面、所述腔的侧面以及所述柱的侧面。
2.根据权利要求1所述的半导体结构，其中：
所述重新分布结构的所述顶侧与所述腔衬底的底侧之间的第一距离不同于所述重新分布结构的所述顶侧与所述电子组件的底侧之间的第二距离。
3.根据权利要求1所述的半导体结构，其中所述腔衬底在至少两个侧面上形成所述电子装置的边界。
4.根据权利要求1所述的半导体结构，其中所述包封件位于所述腔衬底与所述重新分布结构之间。
5.根据权利要求4所述的半导体结构，其中所述包封件位于所述电子组件与所述重新分布结构之间。
6.根据权利要求1所述的半导体结构，其进一步包括组件互连件，所述组件互连件将所述电子装置与所述重新分布结构的所述导电结构耦合，其中所述组件互连件的宽度小于所述柱的宽度。
7.根据权利要求1所述的半导体结构，其中所述包封件的顶侧与所述电子组件的顶侧共面。
8.根据权利要求1所述的半导体结构，其中所述重新分布结构包括重新分布层衬底。
9.根据权利要求1所述的半导体结构，其中所述重新分布结构包括重新分布层衬底，并且所述腔衬底包括预形成的衬底。
10.根据权利要求1所述的半导体结构，其中所述腔衬底的厚度大于所述重新分布结构的厚度。
11.一种用于制造半导体结构的方法，所述方法包括：
提供具有腔和衬底互连件的腔衬底；
将具有组件互连件的电子组件放置在所述腔衬底的所述腔中；
在所述腔衬底的顶侧上在所述腔中提供包封件，所述包封件接触所述电子组件的侧面、所述衬底互连件和所述组件互连件；以及
在所述腔衬底的所述顶侧上提供重新分布结构，其中所述重新分布结构具有与所述衬底互连件耦合的导电结构。
12.根据权利要求11所述的方法，其进一步包括在提供所述重新分布结构之前研磨所述包封件和所述衬底互连件的一部分。
13.根据权利要求12所述的方法，其中所述研磨包含研磨所述组件互连件的一部分。
14.根据权利要求11所述的方法，其中提供所述重新分布结构包括：
在所述包封件、所述腔衬底和所述电子组件之上形成所述重新分布结构的介电层；并且然后
在所述介电层之上形成所述重新分布结构的导电层，所述导电层通过所述介电层耦合到所述腔衬底和所述电子组件。
15.一种半导体结构，其包括：
第一半导体装置，所述第一半导体装置包括：
重新分布结构，所述重新分布结构包括导电结构；
第一衬底，所述第一衬底位于所述重新分布结构的顶侧上并且具有腔和接触所述重新分布结构的柱；
电子组件，所述电子组件位于所述重新分布结构的顶表面上和所述腔中，其中所述电子组件通过组件互连件与所述导电结构电耦合；以及
包封件，所述包封件位于所述腔中和所述重新分布结构的所述顶侧上，所述包封件形成所述电子组件和所述柱的侧面的边界；以及
第二半导体装置，所述第二半导体装置位于所述第一半导体装置的顶侧上，其中所述第二半导体装置与所述第一衬底的顶侧上的衬底焊盘电耦合。
16.根据权利要求15所述的半导体结构，其中所述第二半导体装置包括第二衬底、第二电子组件以及第二包封件，所述第二电子组件位于所述第二衬底的顶侧上，所述第二包封件位于所述第二衬底的所述顶侧上，所述第二包封件接触所述第二电子组件的侧面。
17.根据权利要求15所述的半导体结构，其中所述重新分布结构包括重新分布层衬底，并且所述第一衬底包括预形成的衬底。
18.根据权利要求15所述的半导体结构，其中所述第一半导体装置的所述柱包括导电桩，所述导电桩与所述重新分布结构的所述导电结构和所述衬底焊盘电耦合。
19.根据权利要求15所述的半导体结构，其中所述第一衬底在至少两个侧面上形成所述电子装置的边界。
20.根据权利要求15所述的半导体结构，其中所述包封件位于所述电子组件与所述重新分布结构之间并且位于所述第一衬底与所述重新分布结构之间。
CN202010736607.1A 2019-08-02 2020-07-28 半导体装置及制造半导体装置的方法 Pending CN112310033A (zh)

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