CN112216674A - 半导体装置及制造半导体装置的方法 - Google Patents
半导体装置及制造半导体装置的方法 Download PDFInfo
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- CN112216674A CN112216674A CN202010643581.6A CN202010643581A CN112216674A CN 112216674 A CN112216674 A CN 112216674A CN 202010643581 A CN202010643581 A CN 202010643581A CN 112216674 A CN112216674 A CN 112216674A
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Abstract
半导体装置及制造半导体装置的方法。在一个实例中,一种半导体装置包括:衬底,所述衬底包括电介质、第一导体以及第二导体,所述第一导体位于所述电介质的顶侧上,所述第二导体位于所述电介质的底侧上,其中所述电介质具有孔口,并且所述第一导体包括部分通孔,所述部分通孔通过所述孔口接触所述第二导体的衬垫;电子装置,所述电子装置具有电耦合到所述第一导体的互连件;以及包封件,所述包封件位于所述衬底的顶侧上,所述包封件接触所述电子装置的侧面。本文还公开了其它实例和相关方法。
Description
技术领域
本公开总体上涉及电子装置,并且更具体地涉及半导体装置和用于制造半导体装置的方法。
背景技术
现有半导体封装和用于形成半导体封装的方法存在不足之处,例如造成成本过多、可靠性降低、性能相对较低或封装尺寸太大。对于本领域的技术人员来说,通过将常规和传统方法与本公开进行比较并且参考附图,此类方法的另外的局限性和缺点将变得明显。
发明内容
在一个实例中,一种半导体装置包括:衬底,所述衬底包括电介质、第一导体以及第二导体,所述第一导体位于所述电介质的顶侧上,所述第二导体位于所述电介质的底侧上,其中所述电介质具有孔口,并且所述第一导体包括部分通孔,所述部分通孔通过所述孔口接触所述第二导体的衬垫;电子装置,所述电子装置具有电耦合到所述第一导体的互连件;以及包封件,所述包封件位于所述衬底的顶侧上,所述包封件接触所述电子装置的侧面。
在所述实例中的所述半导体装置中,所述衬底包括第三导体和第四导体,所述第三导体位于所述电介质的所述顶侧上,所述第四导体位于所述电介质的所述底侧上,其中所述电介质具有另外的孔口,并且所述第三导体包括部分通孔,所述部分通孔通过所述另外的孔口接触所述第四导体的衬垫。
所述实例中的所述半导体装置进一步包括迹线,所述迹线位于所述电介质上、所述第一导体的所述部分通孔与所述第三导体的所述部分通孔之间。
在所述实例中的所述半导体装置中,所述第一导体的所述部分通孔的端部和所述第三导体的所述部分通孔的端部间隔开30微米或更少。
在所述实例中的所述半导体装置中,所述第一导体包括第一迹线,所述第一迹线位于所述电介质的所述顶侧上并且与所述部分通孔相连续;并且所述第一迹线和所述部分通孔的宽度相同。
在所述实例中的所述半导体装置中,所述部分通孔的端部接触所述第二导体的所述衬垫;并且与所述部分通孔的所述端部相邻的迹线与所述第二导体的所述衬垫的未被所述部分通孔覆盖的一部分重叠。
在所述实例中的所述半导体装置中,所述迹线与位于所述第二导体的所述衬垫与相邻衬垫之间的间隙的一部分重叠。
在所述实例中的所述半导体装置中,所述部分通孔包括线性形状。
在所述实例中的所述半导体装置中,所述部分通孔包括半圆形形状。
在所述实例中的所述半导体装置中,所述部分通孔覆盖所述衬垫的由所述孔口暴露的基底部分的一半或少于一半。
在所述实例中的所述半导体装置中,所述部分通孔的端部位于所述第二导体的所述衬垫的中心处。
在所述实例中的所述半导体装置中,所述部分通孔覆盖所述孔口的侧壁的一半或少于一半。
在另一个实例中,一种用于制造半导体装置的方法包括:在电介质的顶侧上提供第一导体;在所述电介质的底侧上提供第二导体;在所述电介质中提供孔口,其中所述第一导体包括部分通孔,所述部分通孔通过所述孔口接触所述第二导体的衬垫;提供电子装置,所述电子装置具有接触所述第一导体的互连件;以及提供包封件,所述包封件位于所述电介质的顶侧上并且接触所述电子装置的侧面。
所述另一个实例中的所述方法进一步包括:在所述电介质的所述顶侧上提供第三导体;在所述电介质的所述底侧上提供第四导体;以及在所述电介质中提供另外的孔口,其中所述第三导体包括部分通孔,所述部分通孔通过所述另外的孔口接触所述第四导体的衬垫。
在所述另一个实例中的所述方法中,与穿过同一电介质的全通孔之间的距离相比,所述第一导体的所述部分通孔和所述第三导体的所述部分通孔在所述电介质中间隔开的距离减小。
在所述另一个实例中的所述方法中,与用于穿过同一电介质的全通孔的衬垫的大小相比,所述第二导体的用于所述部分通孔的所述衬垫的大小减小。
在又另一个实例中,一种半导体结构包括重新分布层(RDL)衬底,所述RDL衬底包括:第一介电层,所述第一介电层具有第一孔口;第一导电层,所述第一导电层位于所述第一介电层上,其中所述第一导电层具有所述第一孔口中的全通孔(full via);第二介电层,所述第二介电层具有第二孔口,其中所述第二介电层位于所述第一介电层的顶表面上;以及第二导电层,所述第二导电层位于所述第二介电层的顶表面上,其中所述第二导电层具有所述第二孔口中的部分通孔,所述部分通孔通过所述第二孔口接触所述第一导电层。所述半导体结构还包括:电子装置,所述电子装置位于所述RDL衬底的顶侧上,其中所述电子装置包括与所述第二导电层电耦合的互连件;以及包封件,所述包封件位于所述RDL衬底的所述顶侧上,所述包封件接触所述电子装置的侧面。
在所述又另一个实例中的所述半导体结构中,所述第一介电层具有第三孔口并且所述第一导电层具有所述第三孔口中的全通孔,并且其中所述第二介电层具有第四孔口并且所述第二导电层具有所述第四孔口中的部分通孔,其中所述第一导电层的所述全通孔接触暴露在所述第一介电层的底表面处的下部衬垫,并且所述第二导电层的所述部分通孔接触所述第一导电层的衬垫,其中所述第一导电层的所述衬垫的大小小于所述下部衬垫的大小。
在所述又另一个实例中的所述半导体结构中,所述部分通孔的端部接触所述第一导电层的衬垫;并且与所述部分通孔的所述端部相邻的迹线与所述第一导电层的所述衬垫的未被所述部分通孔覆盖的一部分重叠。
在所述又另一个实例中的所述半导体结构中,所述部分通孔覆盖暴露在所述孔口的底部处的所述第一导电层的一半或少于一半。
附图说明
图1示出了示例半导体装置的横截面视图。
图2A到2M示出了用于制造示例半导体装置的示例方法的横截面视图。
图3A到3F示出了图2B到2G所示的半导体装置的横截面视图中的局部放大平面视图。
具体实施方式
以下讨论提供了半导体装置及制造半导体装置的方法的各种实例。此类实例是非限制性的,并且所附权利要求的范围不应限于所公开的特定实例。在以下讨论中,术语“实例”和“例如”是非限制性的。
图展示了一般的构造方式,并且可以省略对公知的特征和技术的描述和细节,以避免不必要地模糊本公开。另外,附图中的元件不一定按比例绘制。例如,图中元件中的一些元件的尺寸可能相对于其它元件而被放大以有助于改善对本公开中所讨论的实例的理解。不同附图中的相同附图标记指示相同的元件。
术语“或”意味着由“或”连接的列表中的项目的任何一个或多个项目。作为实例,“x或y”意味着三元素集合{(x),(y),(x,y)}中的任何元素。作为另一个实例,“x、y或z”意味着七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}。
术语“包括(comprises)”、“包括(comprising)”、“包含(includes)”或“包含(including)”是“开放式”术语并且指定存在所陈述的特征,但不排除存在或增加一个或多个其它特征。在本文中可以使用术语“第一”、“第二”等来描述各种元件,并且这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件进行区分。因此,例如,在不脱离本公开的教导的情况下,本公开中所讨论的第一元件可以被称为第二元件。
除非另外指明,否则术语“耦合”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。例如,如果元件A耦合到元件B,则元件 A可以直接接触元件B或通过中间元件C间接连接到元件B。类似地,术语“之上”或“上”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。
本公开中包含其它实例。此类实例可以存在于本公开的附图中、权利要求中或说明书中。
图1示出了示例半导体装置100的横截面视图。在图1所示的实例中,半导体装置100可以包含衬底110、电子装置120、包封件130和互连件140。
衬底110可以包含导电层111、113、115、117和119以及介电层112、114、116和 118。电子装置120可以包括端121和电连接到端121的互连件122。端121可以形成于电子装置120的底表面上。互连件122可以由导电材料制成并且可以电连接到衬底110 的导电层119。
包封件130可以覆盖衬底110的顶表面和电子装置120的顶表面或侧表面。另外,互连件140可以由导电材料制成并且可以形成于衬底110的底表面上。衬底110、包封件130和互连件140可以被称为半导体封装101或封装101。半导体封装101可以防止电子装置120暴露于外部因素或环境。另外,半导体封装101可以提供外部组件(如打印电路板)与电子装置120之间的电连接。
在一些实例中,衬底110可以是重新分布层(“RDL”)衬底。RDL衬底可以包括一个或多个导电重新分布层和一个或多个介电层,所述一个或多个导电重新分布层和一个或多个介电层(a)可以在RDL衬底要电耦合到的电子装置之上逐层形成的,或者(b) 可以在将电子装置和RDL衬底耦合在一起之后完全去除或至少部分地去除的载体之上逐层形成。RDL衬底可以在圆形晶片上以晶片级工艺逐层制造为晶片级衬底,或在矩形或方形面板载体上以面板级工艺逐层制造为面板级衬底。RDL衬底可以用可以包含与限定相应的导电重新分布图案或迹线的一个或多个导电层交替堆叠的一个或多个介电层的添加剂堆积工艺形成,所述导电重新分布图案或迹线被配置成共同(a)将电迹线扇出电子装置的占用空间外,或(b)将电迹线扇入电子装置的占用空间内。可以使用镀覆工艺,例如电镀工艺或化学镀工艺来形成导电图案。导电图案可以包括导电材料,例如铜或其它可镀覆金属。可以使用光图案化工艺,例如光刻工艺和用于形成光刻掩模的光刻胶材料来制作导电图案的位置。可以利用可以包含光刻掩模的光图案化工艺来图案化RDL衬底的介电层,光通过所述光刻掩模暴露到光图案期望的特征,如介电层中的通孔中。介电层可以由光可限定的有机介电材料,例如聚酰亚胺(PI)、苯并环丁烯(BCB) 或聚苯并恶唑(PBO)制成。此类介电材料可以以液体形式旋涂或以其它方式涂覆,而不是以预先形成的膜的形式附接。为了允许适当地形成期望的光限定的特征,此类光可限定的介电材料可以省略结构增强剂,或者可以是不含填料的,没有可能会干扰来自光图案化工艺的光的线、织物或其它颗粒。在一些实例中,不含填料的介电材料的此类不含填料的特性可以允许减小所得的介电层的厚度。尽管上文描述的光可限定的介电材料可以是有机材料,但是在其它实例中,RDL衬底的介电材料可以包括一个或多个无机介电层。一个或多个无机介电层的一些实例可以包括氮化硅(Si3N4)、氧化硅(SiO2)或SiON。所述一个或多个无机介电层可以通过使用氧化或氮化工艺而不是使用光限定的有机介电材料生长无机介电层而形成。此类无机介电层可以是不含填料的,没有线、织物或其它不同的无机颗粒。在一些实例中,RDL衬底可以省略永久性芯结构或载体,例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料,并且这些类型的RDL衬底可以被称为无芯衬底。本公开中的其它衬底也可以包括RDL衬底。
图2A到图2M示出了用于制造示例半导体装置100的示例方法的横截面视图。图 3A到图3D示出了图2B到图2E所示的半导体装置100的横截面视图的局部放大平面视图。
图2A示出了处于早期制造阶段的半导体装置100。在图2A所示的实例中,载体 10可以呈基本上平面板的形状。在一些实例中,载体10可以包括或被称为板、晶片、面板或条带。另外,在一些实例中,载体10可以由金属(例如,SUS)、晶片(例如,硅)、陶瓷(例如,氧化铝)、玻璃(例如,钠钙玻璃)或其任何等同物中的至少一种或多种制成。载体10的厚度可以在大约50μm(微米(micron/micrometer))到大约1000μm 的范围内并且宽度可以在大约100mm到大约300mm的范围内。载体10可以用于以集成方式处理多个组件,从而在形成衬底110的同时,在附接电子装置120的同时以及在施加包封件130的同时提供结构完整性。
可以在载体10上形成导电层111。导电层111可以形成为使用经过图案化的掩膜具有载体10的顶表面10x上的图案化。导电层111可以成形为例如圆形、矩形或多边形。在一些实例中,导电层111可以包括或称为导电桩、凸点下金属化(UBM)、下部衬垫或外部衬垫。在一些实例中,外部衬垫111可以由各种导电材料(例如,铜、金、银或等同物)中的任何导电材料制成。另外,在一些实例中,外部衬垫111可以使用各种工艺包含但不限于,溅射、化学镀、电镀、物理气相沉积(PVD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、原子层沉积(ALD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)或等同物中的任何工艺形成。在形成外部衬垫 111之后,可以去除掩模。外部衬垫111的厚度可以在大约0.1μm到大约20μm的范围内。外部衬垫111可以是衬底110的外部输入/输出端,以允许互连件140形成于或附接在衬底110之下。
图2B和图3A示出了处于后期制造阶段的半导体装置100。在图2B和图3A所示的实例中,可以形成介电层112以覆盖载体10的顶表面10x和外部衬垫111。可以通过图案化介电层112来形成暴露外部衬垫111的基底111d的孔口112a。
介电层112可以包括或被称为例如钝化层、绝缘层或保护层。在一些实例中,介电层112可以包含电绝缘材料,包含例如聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模制材料、酚树脂、环氧树脂、硅树脂或丙烯酸酯聚合物。在一些实例中,可以使用各种工艺(例如,旋涂、喷涂、印刷、PVD、 CVD、MOCVD、ALD、LPCVD或PECVD)中的任何工艺形成介电层112。介电层112 的厚度可以在大约3μm到大约30μm的范围内。
在介电层112的顶表面上形成掩膜图案之后,可以通过去除通过蚀刻暴露的介电层 112的一部分来形成孔口112a。孔口112a可以包括或被称为开口或孔。介电层112可以通过孔口112a暴露作为外部衬垫111的顶表面的一部分的基底111d。介电层112可以覆盖外部衬垫111的顶部外周边的一部分和载体10的顶表面10x。由孔口112a暴露的基底111d可以成形为例如圆形、矩形或多边形。由孔口112a暴露的基底111d的形状可以与外部衬垫111的形状相同。由孔口112a暴露的基底111d的面积可以小于外部衬垫 111的面积。另外,由孔口112a暴露的基底111d的直径可以在大约10μm到大约500μm 的范围内。
图2C和图3B示出了处于后期制造阶段的半导体装置100。在图2C和图3B所示的实例中,可以形成导电层113以覆盖外部衬垫111的基底111d和介电层112的暴露表面的一部分。
导电层113可以形成为具有多个图案,所述多个图案可以分别电连接到外部衬垫111 的通过孔口112a暴露的基底111d。另外,电连接到外部衬垫111的基底111d的导电层113可以延伸到介电层112的顶表面。
导电层113可以包括或被称为重新分布层(RDL)、布线图案、迹线图案或电路图案。在一些实例中,重新分布层113可以由各种导电材料(例如,铜、金、银或等同物) 中的任何导电材料制成。重新分布层113可以使用各种工艺,包含但不限于溅射、化学镀、电镀、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物中的任何工艺形成。在重新分布层113形成到覆盖外部衬垫111的基底111d和介电层112的暴露表面的预定厚度之后,可以使用掩膜图案化重新分布层113以创建多个布线图案或迹线。重新分布层113可以包含完全覆盖外部衬垫111的基底111d的全通孔113a和从全通孔113a 延伸到介电层112的顶表面的迹线113b。另外,重新分布层113可以进一步包含在迹线 113b的端部处形成的衬垫113c。衬垫113c可以定位于介电层112的顶表面上。迹线113b 可以电连接全通孔113a和衬垫113c。全通孔113a和衬垫113c可以成形为例如圆形、矩形或多边形。全通孔113a和衬垫113c的大小可以在大约15μm到大约550μm的范围内。重新分布层113的厚度可以在大约3μm到大约20μm的范围内。
图2D和图3C示出了处于后期制造阶段的半导体装置100。在图2D和图3C所示的实例中,可以形成介电层114以完全覆盖重新分布层113和介电层112,并且可以通过图案化介电层114来形成暴露重新分布层113的基底113d的孔口114a。孔口114a可以将作为衬垫113c的顶表面的一部分的基底113d暴露到外部。基底113d可以大致定位于衬垫113c的中心处。介电层114可以覆盖衬垫113c的顶表面的一部分。
介电层114可以包括或被称为例如钝化层、绝缘层或保护层。在一些实例中,介电层114可以包含电绝缘材料,包含例如聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模制材料、酚树脂、环氧树脂、硅树脂或丙烯酸酯聚合物。在一些实例中,可以使用各种工艺(例如,旋涂、喷涂、印刷、PVD、 CVD、MOCVD、ALD、LPCVD或PECVD)中的任何工艺形成介电层114。介电层114 的厚度可以在大约3μm到大约30μm的范围内。
在介电层114的顶表面上形成掩膜图案之后,可以通过去除通过蚀刻暴露的介电层 114来形成孔口114a。孔口114a可以包括或被称为开口或孔。介电层114可以通过孔口114a暴露作为衬垫113c的顶表面的一部分的基底113d。由孔口114a暴露的基底113d 可以成形为例如圆形、矩形或多边形。由孔口114a暴露的基底113d的面积可以小于重新分布层113的衬垫113c的面积。另外,由孔口114a暴露的基底113d的直径的大小可以在大约10μm到大约500μm的范围内。介电层114可以进一步包含覆盖衬垫113c的顶表面的外围部分114b。外围部分114b可以定位于孔口114a周围的外区域处,并且所述外围部分的宽度可以在大约5μm到大约50μm的范围内。
图2E和图3D示出了处于后期制造阶段的半导体装置100。在图2E和图3D所示的实例中,可以形成导电层115以覆盖重新分布层113的基底113d和介电层114的暴露表面的一部分。
衬底110可以包括重新分布层(RDL)衬底。导电层115可以形成为具有多个图案,所述多个图案可以分别电连接到重新分布层113的通过孔口114a暴露的基底113d。另外,电连接到重新分布层113的导电层115可以延伸到介电层114的顶表面。导电层115 可以通过重新分布层113电连接到外部衬垫111。在一些实例中,可以在电介质114的顶侧上提供第一导体115,并且可以在电介质114的底侧上提供第二导体113。可以在电介质114中提供孔口114a。第一导体115可以包括通过孔口114a接触第二导体113 的衬垫基底113d的部分通孔115a。
导电层115可以包括或被称为重新分布层(RDL)、布线图案、迹线图案或电路图案。在一些实例中,重新分布层115可以由各种导电材料(例如,铜、金、银或等同物) 中的任何导电材料制成。重新分布层115可以使用各种工艺,包含但不限于溅射、化学镀、电镀、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物中的任何工艺形成。在重新分布层115形成到覆盖重新分布层113的基底113d和介电层114的暴露表面的预定厚度之后,可以使用掩膜图案来图案化重新分布层115以具有多个图案。重新分布层115可以包含覆盖重新分布层113的基底113d的一部分的部分通孔115a和从部分通孔115a延伸到介电层114的顶表面的迹线115b。另外,重新分布层115可以进一步包含在迹线115b的端部处形成的衬垫115c。
部分通孔115a接触但不完全覆盖重新分布层113的基底113d。另外,部分通孔115a接触但不完全覆盖孔口114a的侧壁。在本发明实例中,部分通孔115a可以成形为具有恒定宽度的线路。部分通孔115a的端部115ax可以大致定位于重新分布层113的基底 113d的中心处。在重新分布层113的基底113d中,未被部分通孔115a覆盖的一部分可以保持暴露于外部。重新分布层115可以通过部分通孔115a电连接到重新分布层113。尽管部分通孔115a在此处示出为具有线性形状,但是仅部分覆盖重新分布层113的基底 113d的其它形状,例如半圆形或其它几何或非几何形状也是可能的。例如,部分通孔 115a可以覆盖基底113d的高达面积或直径的一半或少于一半,或者覆盖孔口114a的侧壁的高达面积的一半或少于一半。
在一些实例中,如图2B所示,衬底110包括重新分布层(RDL)衬底,所述RDL 衬底包括第一介电层112和第一导电层113,所述第一介电层具有第一孔口112a,所述第一导电层位于第一介电层112上,其中第一导电层113具有第一孔口112a中的全通孔 113a。如图2E所示,RDL衬底110可以包括第二介电层114和第二导电层115,所述第二介电层具有第二孔口114a,其中第二介电层114位于第一介电层112的顶表面上,所述第二导电层位于第二介电层114的顶表面上,其中第二导电层115具有在第二孔口 114a中通过第二孔口114a电接触第一导电层113的部分通孔115a。
迹线115b可以成形为具有恒定或几乎恒定宽度的线路。另外,迹线115b的宽度可以与部分通孔115a的宽度相同。迹线115b的宽度可以在大约1μm到大约100μm的范围内。迹线115b可以将部分通孔115a电连接到衬垫115c。迹线115b可以定位于介电层114的顶表面上。可以由从电连接到基底113d的部分通孔115a延伸的迹线115d部分覆盖介电层114的外围部分114b。另外,除了由迹线115b覆盖的部分,介电层114的外围部分114b的部分可以保持暴露。
衬垫115c可以成形为例如圆形、矩形或多边形。衬垫115c可以定位于介电层114的顶表面上。衬垫115c的大小可以在大约15μm到大约550μm的范围内。重新分布层 115的厚度可以在大约3μm到大约20μm的范围内。另外,与形成完全覆盖基底113d 的全通孔的情况相比,重新分布层115可以通过形成部分覆盖基底113d和外围部分114b 的部分通孔115a来减少重新分布层115的导电图案之间的距离,由此实现衬垫之间或衬垫端部之间间距的小型化或减小,如下文关于图2G和图2F进一步详细示出和描述的。
图2F和图3E示出了处于后期制造阶段的半导体装置100。在图2F和图3E所示的实例中,可以形成介电层116以完全覆盖基底113d、重新分布层115和介电层114。可以通过图案化介电层116来形成暴露重新分布层115的基底115d的孔口116a。孔口116a 可以将作为重新分布层115的衬垫115c的顶表面的一部分的基底115d暴露到外部。基底115d可以大致定位于衬垫115c的中心处。
介电层116可以包括或被称为例如钝化层、绝缘层或保护层。在一些实例中,介电层116可以包含电绝缘材料,包含例如聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模制材料、酚树脂、环氧树脂、硅树脂或丙烯酸酯聚合物。在一些实例中,可以使用各种工艺(例如,旋涂、喷涂、印刷、PVD、 CVD、MOCVD、ALD、LPCVD或PECVD)中的任何工艺形成介电层116。介电层116 的厚度可以在大约3μm到大约30μm的范围内。
在介电层116的顶表面上形成掩膜图案之后,可以通过去除通过蚀刻暴露的介电层 116的一部分来形成孔口116a。孔口116a可以包括或被称为开口或孔。介电层116可以将作为重新分布层115的衬垫115c的顶表面的一部分的基底115d暴露到外部。由孔口 116a暴露的基底115d可以成形为例如圆形、矩形或多边形。由孔口116a暴露的基底115d 的面积可以小于衬垫115c的面积。另外,由孔口116a暴露的基底115d的直径可以在大约10μm到大约500μm的范围内。介电层116可以进一步包含覆盖衬垫115c的顶表面的外围部分116b。外围部分116b可以定位于孔口116a周围的外区域处并且所述外围部分的宽度可以在大约5μm到大约50μm的范围内。
图2G和图3F示出了处于后期制造阶段的半导体装置100。在图2G和图3F所示的实例中,可以形成导电层117以覆盖重新分布层115的基底115d和介电层116的暴露表面的一部分。在一些实例中,衬底110包括电介质116、第一导体117和第二导体115,所述第一导体位于电介质116的顶侧上,所述第二导体位于电介质116的底侧上。电介质116可以具有孔口116a,并且第一导体117包括通过孔口116a接触第二导体115的衬垫基底115d的部分通孔117a。在一些实例中,第一导体117包括第一迹线117e,所述第一迹线位于电介质116的顶侧上并且与部分通孔117a相连续。在一些实例中,第一迹线117e和部分通孔117a的宽度相同。在一些实例中,部分通孔117a的端部117ax接触第二导体115的衬垫基底115d,并且与部分通孔117a的端部117ax相邻的迹线117e 与第二导体115的衬垫基底115d的未被部分通孔117a覆盖的一部分重叠。在一些实例中,第二导体115的相邻衬垫115c之间可以存在间隙,并且迹线117e与第二导体115 的衬垫115c与第二导体115的相邻衬垫115c之间的间隙的一部分重叠。
导电层117可以形成为具有多个图案,所述多个图案可以分别电连接到重新分布层 115的通过孔口116a暴露的基底115d。另外,电连接到重新分布层115的导电层117 可以延伸到介电层116的顶表面。导电层117可以通过重新分布层115以及重新分布层 113电连接到外部衬垫111。
导电层117可以包括或被称为重新分布层(RDL)、布线图案或电路图案。在一些实例中,重新分布层117可以由各种导电材料(例如,铜、金、银或等同物)中的任何导电材料制成。重新分布层117可以使用各种工艺,包含但不限于溅射、化学镀、电镀、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物中的任何工艺形成。在重新分布层117形成到预定厚度以便覆盖重新分布层115的基底115d和介电层116的暴露表面之后,可以使用掩膜图案来图案化所述重新分布层以具有多个布线图案或电路图案。重新分布层117可以包含覆盖重新分布层115的衬垫基底115d的一部分的部分通孔117a 和从部分通孔117a延伸到介电层116的顶表面的迹线117b。另外,重新分布层117可以进一步包含在迹线117b的端部处形成的衬垫117c。
部分通孔117a可以类似于部分通孔115a,并且可以类似地形成为所述部分通孔。部分通孔117a形成为使得不仅仅部分覆盖重新分布层115的衬垫基底115d。而且,部分通孔117a形成为使得不仅仅部分覆盖介电层116的孔口116a的侧壁。在一些实例中,部分通孔115a或部分通孔117a可以包括线性形状或另一种形状,如由图3F的部分通孔 117a的实例展示的半圆形形状。在一些实例中,部分通孔115a或部分通孔117a可以覆盖衬垫基底115d的一半或少于一半。
迹线117b可以类似于迹线115b,并且可以类似地形成为所述迹线。迹线117b可以形成于介电层116上,并且可以将部分通孔117a连接到衬垫117c。迹线117b可以定位于介电层116的顶表面上。还可以在两个相邻部分通孔117a之间形成如迹线117e等其它图案。
在没有到达彼此相邻地定位于部分通孔117a的衬垫115c的外区域之上的介电外围部分116b的部分或覆盖在其之上的情况下,所述部分通孔覆盖其衬垫基底115d(并且在此实例中仅部分覆盖)。这使得通孔到通孔的距离117z比由类似于例如全通孔113a 的全通孔代替覆盖衬垫基底115d的情况更进一步最小化(图2C,3B)。在一些实例中,减小的通孔到通孔的距离117z允许端部117ax以减小的间距更靠近地间隔开。另外,因为通过使用相邻的部分通孔117a而不是相邻的全通孔在导电层117中提供了另外的空间,所以在不违反相邻迹线或电路图案之间的最小距离的布局设计规则的情况下,可以将如迹线117e等图案定位于此类部分通孔117a之间。在一些实例中,与使用相邻的全通孔的相应情况相比,使用相邻的部分通孔117a可以允许将通孔到通孔的距离117z减少例如至少大约25%。例如,与使用将需要通孔到通孔的距离117z为至少大约40μm 的相邻的全通孔的情况相比,使用相邻部分通孔117a的情况将允许将通孔到通孔的距离117z最小化为至少大约30μm,但是本发明公开的范围并不限于此方面。
衬垫117c可以类似于衬垫115c,并且可以类似地形成为所述衬垫。衬垫117c形成于介电层116上并且耦合到迹线117b。与形成完全覆盖基底的全通孔的情况相比,重新分布层117可以通过形成部分覆盖基底115d和外围部分116b的部分通孔117a来减少重新分布层117的图案中的每个图案之间的距离,由此实现小型化。
图2H示出了处于后期制造阶段的半导体装置100。在图2H所示的实例中,可以形成介电层118以完全覆盖基底115d、重新分布层117和介电层116,并且可以通过图案化介电层118来形成暴露重新分布层117的基底117d的孔口118a。孔口118a可以将作为衬垫117c的顶表面的一部分的基底117d暴露到外部。
介电层118可以包括或被称为例如钝化层、绝缘层或保护层。在一些实例中,介电层118可以包含电绝缘材料,包含例如聚合物、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、模制材料、酚树脂、环氧树脂、硅树脂或丙烯酸酯聚合物。在一些实例中,可以使用各种工艺(例如,旋涂、喷涂、印刷、PVD、 CVD、MOCVD、ALD、LPCVD或PECVD)中的任何工艺形成介电层118。介电层118 的厚度可以在大约3μm到大约30μm的范围内。
在介电层118的顶表面上形成掩膜图案之后,可以通过去除通过蚀刻暴露的介电层 118来形成孔口118a。孔口118a可以包括或被称为开口或孔。介电层118可以通过孔口118a暴露作为衬垫117c的顶表面的一部分的基底117d。由孔口118a暴露的基底117d 可以成形为例如圆形、矩形或多边形。由孔口118a暴露的基底117d的形状可以与重新分布层117的衬垫117c的形状相同。由孔口118a暴露的基底117d的面积可以小于重新分布层117的衬垫117c的面积。另外,由孔口118a暴露的基底117d的直径可以在大约 10μm到大约500μm的范围内。
图2I示出了处于后期制造阶段的半导体装置100。在图2I所示的实例中,可以形成导电层119以覆盖重新分布层117的基底117d和介电层118的暴露表面。
导电层119可以形成为具有多个图案,所述多个图案可以分别电连接到重新分布层 117的通过孔口118a暴露的基底117d。另外,电连接到重新分布层117的导电层119 可以形成为部分覆盖介电层118的顶表面。导电层119可以通过重新分布层117以及重新分布层115和重新分布层113电连接到外部衬垫111。
导电层119可以包括或被称为导电衬垫、互连衬垫、微衬垫、接合衬垫、凸点衬垫或凸点下金属化(UBM)。在一些实例中,互连衬垫119可以由各种导电材料(例如,铜、金、银或等同物)中的任何导电材料制成。可以在互连衬垫119上进一步形成由锡、金、银、镍、钯或等同物制成的用于防止互连衬垫119被氧化的抗氧化层。互连衬垫119 可以使用各种工艺中的任何工艺形成,所述工艺包含但不限于溅射、化学镀、电镀、PVD、 CVD、MODVD、ALD、LPCVD、PECVD或等同物。在互连衬垫119形成到覆盖重新分布层117的基底117d和介电层118的暴露表面的预定厚度之后,可以使用掩膜图案来图案化重新分布层117以具有多个图案。互连衬垫119的厚度可以在大约5μm到大约300μm的范围内。
因为互连衬垫119是以上述方式形成的,所以可以完成衬底110。尽管展示了包括五个导电层111、113、115、117和119以及四个介电层112、114、116和118的衬底110,衬底110的层数可以小于或大于五个导电层111、113、115、117和119以及四个介电层 112、114、116和118,并且所公开的主题的范围并不限于这些方面。
图2J示出了处于后期制造阶段的半导体装置100。在图2J所示的实例中,装置120可以电连接到衬底110的导电衬垫119。在一些实例中,衬底110可以是重新分布层 (RDL)衬底。
在一些实例中,拾放设备可以拾取电子装置120以将其放置在衬底110的互连衬垫119上。接下来,电子装置120可以通过质量回流、热压缩或激光辅助接合来电连接到衬底110。可以提供具有互连件122的电子装置120,所述互连件电耦合到第一导体117 或电耦合到导体115、导体113或导体111。
在一些实例中,电子装置120可以包括或被称为半导体管芯或半导体芯片。另外,在一些实例中,电子装置120可以包括逻辑管芯、微控制单元、存储器、数字信号处理器、网络处理器、电源管理单元、音频处理器、RF电路、无线基带片上系统处理器、专用集成电路或等同物中的至少一个。
在一些实例中,电子装置120可以包含有源区域和非有源区域。另外,在一些实例中,有源区域可以安置成面对衬底110。另外,在一些实例中,有源区域可以包含互连件121。在一些实例中,互连件121可以被称为管芯衬垫、接合衬垫、铝衬垫、凸点、导电柱或导电桩。
另外,互连件121可以使用低熔点材料122连接到衬底110的互连衬垫119。在一个实例中,低熔点材料122可以包括Sn、Ag、Pb、Cu、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、 Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi、Sn-Ag-Cu或等同物中的一种或多种。电子装置120的互连件121和衬底110的互连衬垫119可以通过低熔点材料122彼此电连接。互连件121 和低熔点材料122的厚度可以在大约5μm到大约300μm的范围内。
图2K示出了处于后期制造阶段的半导体装置100。在图2K所示的实例中,可以形成包封件130以部分或完全覆盖衬底110的顶表面110x和电子装置120的顶表面或侧表面。在一些实例中,包封件130可以包括或被称为环氧模制化合物、环氧模制树脂或密封剂。另外,在一些实例中,包封件130可以包括或被称为模制部件、密封部件、包封部件、保护部件、封装或主体部件。在一些实例中,包封件130可以包含但不限于有机树脂、无机填料、固化剂、催化剂、着色剂、阻燃剂等。可以通过各种工艺中的任何工艺形成基于包封件130的模制。在一些实例中,包封件130可以通过但不限于压缩模制、传递模制、液相包封件模制、真空层压、膏印刷或膜辅助模制形成。包封件130的厚度可以在大约50μm到大约300μm的范围内。包封件130可以包封电子装置120,由此保护处于封装状态的电子装置120免受外部因素或环境的影响。在一些实例中,可以在衬底110的接触电子装置120的侧面的顶侧上提供包封件130。在一些实例中,衬底110可以是重新分布层(RDL)衬底。
图2L示出了处于后期制造阶段的半导体装置100。在图2L所示的实例中,可以通过去除载体10来暴露衬底110的底表面110y。如果去除了载体10,则可以通过衬底110 的底表面110y来暴露外部衬垫111和介电层112。可以通过普通研磨或化学蚀刻来去除载体10。可替代地,可以通过使用紫外(UV)辐射或激光的释放工艺来去除载体10。
图2M示出了处于后期制造阶段的半导体装置100。在图2M所示的实例中,可以在外部衬垫111上形成暴露于衬底110的底表面110y的互连件140。
互连件140可以电连接到外部衬垫111的底表面。互连件140可以通过衬底110的导电层111、113、115、117和119电连接到电子装置120。在一些实例中,互连件140 可以包含锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、 Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu或等同物。
互连件140可以通过例如球落工艺、丝网印刷工艺或电镀工艺形成。在一些实例中,互连件140可以通过形成导电材料,包含衬底110的外部衬垫111的底表面上的焊料、使用球落工艺的导电层122,然后通过回流工艺来形成。在此阶段,可以将衬底110的底表面110y安置为面朝上。互连件140可以包括或被称为如焊球等导电球、如铜柱等导电柱,或具有铜柱上的焊帽的导电桩。互连件140的大小可以在大约20μm到大约500 μm的范围内。
本公开包含对如本文所述的某些实例的引用。本领域的技术人员应理解的是,在不脱离本公开的范围的情况下,可以作出各种改变并且可以取代等同物。另外,在不脱离本公开的范围的情况下,可以对所公开的实例进行修改。因此,本公开旨在并不受限于所公开的实例,而是本公开将包含所有实例,包含落入所附权利要求的范围内的实例。
Claims (20)
1.一种半导体装置,其包括:
衬底,所述衬底包括电介质、第一导体以及第二导体,所述第一导体位于所述电介质的顶侧上,所述第二导体位于所述电介质的底侧上,其中所述电介质具有孔口,并且所述第一导体包括部分通孔,所述部分通孔通过所述孔口接触所述第二导体的衬垫;
电子装置,所述电子装置具有电耦合到所述第一导体的互连件;以及
包封件,所述包封件位于所述衬底的顶侧上,所述包封件接触所述电子装置的侧面。
2.根据权利要求1所述的半导体装置,其中所述衬底包括第三导体和第四导体,所述第三导体位于所述电介质的所述顶侧上,所述第四导体位于所述电介质的所述底侧上,其中所述电介质具有另外的孔口,并且所述第三导体包括部分通孔,所述部分通孔通过所述另外的孔口接触所述第四导体的衬垫。
3.根据权利要求2所述的半导体装置,其进一步包括迹线,所述迹线位于所述电介质上、所述第一导体的所述部分通孔与所述第三导体的所述部分通孔之间。
4.根据权利要求2所述的半导体装置,其中所述第一导体的所述部分通孔的端部和所述第三导体的所述部分通孔的端部间隔开30微米或更少。
5.根据权利要求2所述的半导体装置,其中:
所述第一导体包括第一迹线,所述第一迹线位于所述电介质的所述顶侧上并且与所述部分通孔相连续;并且
所述第一迹线和所述部分通孔的宽度相同。
6.根据权利要求1所述的半导体装置,其中:
所述部分通孔的端部接触所述第二导体的所述衬垫;并且
与所述部分通孔的所述端部相邻的迹线与所述第二导体的所述衬垫的未被所述部分通孔覆盖的一部分重叠。
7.根据权利要求6所述的半导体装置,其中所述迹线与位于所述第二导体的所述衬垫与相邻衬垫之间的间隙的一部分重叠。
8.根据权利要求1所述的半导体装置,其中所述部分通孔包括线性形状。
9.根据权利要求1所述的半导体装置,其中所述部分通孔包括半圆形形状。
10.根据权利要求1所述的半导体装置,其中所述部分通孔覆盖所述衬垫的由所述孔口暴露的基底部分的一半或少于一半。
11.根据权利要求1所述的半导体装置,其中所述部分通孔的端部位于所述第二导体的所述衬垫的中心处。
12.根据权利要求1所述的半导体装置,其中所述部分通孔覆盖所述孔口的侧壁的一半或少于一半。
13.一种用于制造半导体装置的方法,所述方法包括:
在电介质的顶侧上提供第一导体;
在所述电介质的底侧上提供第二导体;
在所述电介质中提供孔口,其中所述第一导体包括部分通孔,所述部分通孔通过所述孔口接触所述第二导体的衬垫;
提供电子装置,所述电子装置具有与所述第一导体电耦合的互连件;以及
提供包封件,所述包封件位于所述电介质的顶侧上并且接触所述电子装置的侧面。
14.根据权利要求13所述的方法,其进一步包括:
在所述电介质的所述顶侧上提供第三导体;
在所述电介质的所述底侧上提供第四导体;以及
在所述电介质中提供另外的孔口,其中所述第三导体包括部分通孔,所述部分通孔通过所述另外的孔口接触所述第四导体的衬垫。
15.根据权利要求14所述的方法,其中与穿过同一电介质的全通孔之间的距离相比,所述第一导体的所述部分通孔和所述第三导体的所述部分通孔在所述电介质中间隔开的距离减小。
16.根据权利要求14所述的方法,其中与用于穿过同一电介质的全通孔的衬垫的大小相比,所述第二导体的用于所述部分通孔的所述衬垫的大小减小。
17.一种半导体结构,其包括:
重新分布层衬底,所述重新分布层衬底包括:
第一介电层,所述第一介电层具有第一孔口;
第一导电层,所述第一导电层位于所述第一介电层上,其中所述第一导电层具有所述第一孔口中的全通孔;
第二介电层,所述第二介电层具有第二孔口,其中所述第二介电层位于所述第一介电层的顶表面上;以及
第二导电层,所述第二导电层位于所述第二介电层的顶表面上,其中所述第二导电层具有所述第二孔口中的部分通孔,所述部分通孔通过所述第二孔口接触所述第一导电层;
电子装置,所述电子装置位于所述重新分布层衬底的顶侧上,其中所述电子装置包括与所述第二导电层电耦合的互连件;以及
包封件,所述包封件位于所述重新分布层衬底的所述顶侧上,所述包封件接触所述电子装置的侧面。
18.根据权利要求17所述的半导体结构,其中所述第一介电层具有第三孔口并且所述第一导电层具有所述第三孔口中的全通孔,并且其中所述第二介电层具有第四孔口并且所述第二导电层具有所述第四孔口中的部分通孔,其中所述第一导电层的所述全通孔接触暴露在所述第一介电层的底表面处的下部衬垫,并且所述第二导电层的所述部分通孔接触所述第一导电层的衬垫,其中所述第一导电层的所述衬垫的大小小于所述下部衬垫的大小。
19.根据权利要求17所述的半导体结构,其中:
所述部分通孔的端部接触所述第一导电层的衬垫;并且
与所述部分通孔的所述端部相邻的迹线与所述第一导电层的所述衬垫的未被所述部分通孔覆盖的一部分重叠。
20.根据权利要求17所述的半导体结构,其中所述部分通孔覆盖暴露在所述孔口的底部处的所述第一导电层的一半或少于一半。
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