TW202105657A - 半導體裝置及製造半導體裝置的方法 - Google Patents
半導體裝置及製造半導體裝置的方法 Download PDFInfo
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- TW202105657A TW202105657A TW109120618A TW109120618A TW202105657A TW 202105657 A TW202105657 A TW 202105657A TW 109120618 A TW109120618 A TW 109120618A TW 109120618 A TW109120618 A TW 109120618A TW 202105657 A TW202105657 A TW 202105657A
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Abstract
在一個實例中,一種半導體裝置包括:基板,所述基板包括介電質、第一導體以及第二導體,所述第一導體位於所述介電質的頂側上,所述第二導體位於所述介電質的底側上,其中所述介電質具有孔口,並且所述第一導體包括部分通孔,所述部分通孔通過所述孔口接觸所述第二導體的襯墊;電子裝置,所述電子裝置具有電耦合到所述第一導體的互連件;以及囊封件,所述囊封件位於所述基板的頂側上,所述囊封件接觸所述電子裝置的側面。本文還揭露了其它實例和相關方法。
Description
本揭示內容總體上涉及電子裝置,並且更具體地涉及半導體裝置和用於製造半導體裝置的方法。
現有半導體封裝和用於形成半導體封裝的方法存在不足之處,例如造成成本過多、可靠性降低、性能相對較低或封裝尺寸太大。對於本領域的技術人員來說,通過將常規和傳統方法與本揭示內容進行比較並且參考附圖,此類常規和傳統方法的進一步限制和缺點將變得明顯。
本發明的一態樣為一種半導體裝置,其包括:基板,所述基板包括介電質、第一導體以及第二導體,所述第一導體位於所述介電質的頂側上,所述第二導體位於所述介電質的底側上,其中所述介電質具有孔口,並且所述第一導體包括部分通孔,所述部分通孔通過所述孔口接觸所述第二導體的襯墊;電子裝置,所述電子裝置具有電耦合到所述第一導體的互連件;以及囊封件,所述囊封件位於所述基板的頂側上,所述囊封件接觸所述電子裝置的側面。
根據本發明的一態樣所述的半導體裝置,所述基板包括第三導體和第四導體,所述第三導體位於所述介電質的所述頂側上,所述第四導體位於所述介電質的所述底側上,其中所述介電質具有另外的孔口,並且所述第三導體包括部分通孔,所述部分通孔通過所述另外的孔口接觸所述第四導體的襯墊。
根據本發明的一態樣所述的半導體裝置,進一步包括跡線,所述跡線位於所述介電質上且在所述第一導體的所述部分通孔與所述第三導體的所述部分通孔之間。
根據本發明的一態樣所述的半導體裝置,所述第一導體的所述部分通孔的端部和所述第三導體的所述部分通孔的端部間隔開30微米或更少。
根據本發明的一態樣所述的半導體裝置,所述第一導體包括第一跡線,所述第一跡線位於所述介電質的所述頂側上並且與所述部分通孔相連續;並且所述第一跡線和所述部分通孔的寬度相同。
根據本發明的一態樣所述的半導體裝置,所述部分通孔的端部接觸所述第二導體的所述襯墊;並且與所述部分通孔的所述端部相鄰的跡線與所述第二導體的所述襯墊的未被所述部分通孔覆蓋的一部分重疊。
根據本發明的一態樣所述的半導體裝置,所述跡線與位於所述第二導體的所述襯墊與相鄰襯墊之間的間隙的一部分重疊。
根據本發明的一態樣所述的半導體裝置,所述部分通孔包括線性形狀。
根據本發明的一態樣所述的半導體裝置,所述部分通孔包括半圓形形狀。
根據本發明的一態樣所述的半導體裝置,所述部分通孔覆蓋所述襯墊的由所述孔口暴露的基底部分的一半或少於一半。
根據本發明的一態樣所述的半導體裝置,所述部分通孔的端部位於所述第二導體的所述襯墊的中心處。
根據本發明的一態樣所述的半導體裝置,所述部分通孔覆蓋所述孔口的側壁的一半或少於一半。
本發明的另一態樣為一種用於製造半導體裝置的方法,所述方法包括:在介電質的頂側上提供第一導體;在所述介電質的底側上提供第二導體;在所述介電質中提供孔口,其中所述第一導體包括部分通孔,所述部分通孔通過所述孔口接觸所述第二導體的襯墊;提供電子裝置,所述電子裝置具有與所述第一導體電耦合的互連件;以及提供囊封件,所述囊封件位於所述介電質的頂側上並且接觸所述電子裝置的側面。
根據本發明的另一態樣所述的方法進一步包括:在所述介電質的所述頂側上提供第三導體;在所述介電質的所述底側上提供第四導體;以及在所述介電質中提供另外的孔口,其中所述第三導體包括部分通孔,所述部分通孔通過所述另外的孔口接觸所述第四導體的襯墊。
根據本發明的另一態樣所述的方法,與穿過同一介電質的全通孔之間的距離相比,所述第一導體的所述部分通孔和所述第三導體的所述部分通孔在所述介電質中間隔開的距離減小。
根據本發明的另一態樣所述的方法,與用於穿過同一介電質的全通孔的襯墊的大小相比,所述第二導體的用於所述部分通孔的所述襯墊的大小減小。
本發明的又一態樣為一種半導體結構,所述半導體結構包括:重新分佈層(RDL)基板,所述重新分佈層基板包括:第一介電層,所述第一介電層具有第一孔口;第一導電層,所述第一導電層位於所述第一介電層上,其中所述第一導電層具有所述第一孔口中的全通孔;第二介電層,所述第二介電層具有第二孔口,其中所述第二介電層位於所述第一介電層的頂表面上;以及第二導電層,所述第二導電層位於所述第二介電層的頂表面上,其中所述第二導電層具有所述第二孔口中的部分通孔,所述部分通孔通過所述第二孔口接觸所述第一導電層;電子裝置,所述電子裝置位於所述重新分佈層基板的頂側上,其中所述電子裝置包括與所述第二導電層電耦合的互連件;以及囊封件,所述囊封件位於所述重新分佈層基板的所述頂側上,所述囊封件接觸所述電子裝置的側面。
根據本發明的又一態樣所述的半導體結構,所述第一介電層具有第三孔口並且所述第一導電層具有所述第三孔口中的全通孔,並且其中所述第二介電層具有第四孔口並且所述第二導電層具有所述第四孔口中的部分通孔,其中所述第一導電層的所述全通孔接觸暴露在所述第一介電層的底表面處的下部襯墊,並且所述第二導電層的所述部分通孔接觸所述第一導電層的襯墊,其中所述第一導電層的所述襯墊的大小小於所述下部襯墊的大小。
根據本發明的又一態樣所述的半導體結構,所述部分通孔的端部接觸所述第一導電層的襯墊;並且與所述部分通孔的所述端部相鄰的跡線與所述第一導電層的所述襯墊的未被所述部分通孔覆蓋的一部分重疊。
根據本發明的又一態樣所述的半導體結構,所述部分通孔覆蓋暴露在所述孔口的底部處的所述第一導電層的一半或少於一半。
以下討論提供了半導體裝置及製造半導體裝置的方法的各種實例。此類實例是非限制性的,並且所附申請專利範圍的範疇不應限於所揭露的特定實例。在以下討論中,術語“實例”和“例如”是非限制性的。
圖展示了一般的構造方式,並且可以省略對公知的特徵和技術的描述和細節,以避免不必要地模糊本揭示內容。另外,附圖中的元件不一定按比例繪製。例如,圖中元件中的一些元件的尺寸可能相對於其它元件而被放大以有助於改善對本揭示內容中所討論的實例的理解。不同附圖中的相同附圖標記指示相同的元件。
術語“或”意味著由“或”連接的列表中的項目的任何一個或多個項目。作為實例,“x或y”意味著三元素集合{(x), (y), (x, y)}中的任何元素。作為另一個實例,“x、y或z”意味著七元素集合{(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}。
術語“包括(comprises)”、“包括(comprising)”、“包含(includes)”或“包含(including)”是“開放式”術語並且指定存在所陳述的特徵,但不排除存在或增加一個或多個其它特徵。在本文中可以使用術語“第一”、“第二”等來描述各種元件,並且這些元件不應受這些術語的限制。這些術語僅是用來將一個元件與另一個元件進行區分。因此,例如,在不脫離本揭露內容的教導的情況下,本揭露內容中所討論的第一元件可以被稱為第二元件。
除非另外指明,否則術語“耦合”可以用於描述彼此直接接觸的兩個元件或描述通過一個或多個其它元件間接連接的兩個元件。例如,如果元件A耦合到元件B,則元件A可以直接接觸元件B或通過中間元件C間接連接到元件B。類似地,術語“之上”或“上”可以用於描述彼此直接接觸的兩個元件或描述通過一個或多個其它元件間接連接的兩個元件。
在一個實例中,一種半導體裝置包括:基板,所述基板包括介電質、第一導體以及第二導體,所述第一導體位於所述介電質的頂側上,所述第二導體位於所述介電質的底側上,其中所述介電質具有孔口,並且所述第一導體包括部分通孔,所述部分通孔通過所述孔口接觸所述第二導體的襯墊;電子裝置,所述電子裝置具有電耦合到所述第一導體的互連件;以及囊封件,所述囊封件位於所述基板的頂側上,所述囊封件接觸所述電子裝置的側面。
在另一個實例中,一種用於製造半導體裝置的方法包括:在介電質的頂側上提供第一導體;在所述介電質的底側上提供第二導體;在所述介電質中提供孔口,其中所述第一導體包括部分通孔,所述部分通孔通過所述孔口接觸所述第二導體的襯墊;提供電子裝置,所述電子裝置接觸所述第一導體的互連件;以及提供囊封件,所述囊封件位於所述介電質的頂側上並且接觸所述電子裝置的側面。
在又另一個實例中,一種半導體結構包括重新分佈層(RDL)基板,所述RDL基板包括:第一介電層,所述第一介電層具有第一孔口;第一導電層,所述第一導電層位於所述第一介電層上,其中所述第一導電層具有所述第一孔口中的全通孔(full via);第二介電層,所述第二介電層具有第二孔口,其中所述第二介電層位於所述第一介電層的頂表面上;以及第二導電層,所述第二導電層位於所述第二介電層的頂表面上,其中所述第二導電層具有所述第二孔口中的部分通孔,所述部分通孔通過所述第二孔口接觸所述第一導電層。所述半導體結構還包括:電子裝置,所述電子裝置位於所述RDL基板的頂側上,其中所述電子裝置包括與所述第二導電層電耦合的互連件;以及囊封件,所述囊封件位於所述RDL基板的所述頂側上,所述囊封件接觸所述電子裝置的側面。
本揭示內容中包含其它實例。此類實例可以存在於本揭示內容的附圖中、申請專利範圍中或說明書中。
圖1示出了示例半導體裝置100的橫截面視圖。在圖1所示的實例中,半導體裝置100可以包含基板110、電子裝置120、囊封件130和互連件140。
基板110可以包含導電層111、113、115、117和119以及介電層112、114、116和118。電子裝置120可以包括端子121和電連接到端子121的互連件122。端子121可以形成於電子裝置120的底表面上。互連件122可以由導電材料製成並且可以電連接到基板110的導電層119。
囊封件130可以覆蓋基板110的頂表面和電子裝置120的側表面。另外,互連件140可以由導電材料製成並且可以形成於基板110的底表面上。基板110、囊封件130和互連件140可以被稱為半導體封裝101或封裝101。半導體封裝101可以防止電子裝置120暴露於外部因素或環境。另外,半導體封裝101可以提供外部組件(如印刷電路板)與電子裝置120之間的電連接。
在一些實例中,基板110可以是重新分佈層(“RDL”)基板。RDL基板可以包括(a)可以在RDL基板要電耦合到的電子裝置之上逐層形成的,或者(b)可以在可以在將電子裝置和RDL基板耦合在一起之後完全去除或至少部分地去除的載體之上逐層形成的一個或多個導電重新分佈層和一個或多個介電層。RDL基板可以在圓形晶片上以晶圓級製程逐層製造為晶圓級基板,或在矩形或方形面板載體上以面板級製程逐層製造為面板級基板。RDL基板可以以可以包含與限定相應的導電重新分佈圖案或跡線的一個或多個導電層交替堆疊的一個或多個介電層的添加劑堆積製程形成,所述導電重新分佈圖案或跡線被配置成共同(a)將電跡線扇出電子裝置的佔用空間外,或(b)將電跡線扇入電子裝置的佔用空間內。可以使用鍍覆製程,例如電鍍製程或化學鍍製程來形成導電圖案。導電圖案可以包括導電材料,例如銅或其它可鍍覆金屬。可以使用光圖案化製程,例如光刻製程和用於形成光刻遮罩的光刻膠材料來製作導電圖案的位置。可以利用可以包含光刻遮罩的光圖案化製程來圖案化RDL基板的介電層,光通過所述光刻遮罩暴露到光圖案期望的特徵,如介電層中的通孔中。介電層可以由光可限定的有機介電材料,例如聚醯亞胺(polyimide,PI)、苯並環丁烯(benzocyclobutene,BCB)或聚苯並噁唑(polybenzoxazole,PBO)製成。此類介電材料可以以液體形式旋塗或以其它方式塗覆,而不是以預先形成的膜的形式附接。為了允許適當地形成期望的光限定的特徵,此類光可限定的介電材料可以省略結構增強劑,或者可以是不含填料的,沒有可能會干擾來自光圖案化製程的光的線、織物或其它顆粒。在一些實例中,不含填料的介電材料的此類不含填料的特性可以允許減小所得的介電層的厚度。儘管上文描述的光可限定的介電材料可以是有機材料,但是在其它實例中,RDL基板的介電材料可以包括一個或多個無機介電層。一個或多個無機介電層的一些實例可以包括氮化矽(Si3
N4
)、氧化矽(SiO2
)或SiON。所述一個或多個無機介電層可以通過使用氧化或氮化製程而不是使用光限定的有機介電材料生長無機介電層而形成。此類無機介電層可以是不含填料的,沒有線、織物或其它不同的無機顆粒。在一些實例中,RDL基板可以省略永久性芯結構或載體,例如包括雙馬來醯亞胺三嗪(bismaleimide triazine,BT)或FR4的介電材料,並且這些類型的RDL基板可以被稱為無芯基板。本揭露內容中的其它基板也可以包括RDL基板。
圖2A到圖2M示出了用於製造示例半導體裝置100的示例方法的橫截面視圖。圖3A到圖3D示出了圖2B到圖2E所示的半導體裝置100的橫截面視圖的局部放大平面視圖。
圖2A示出了處於早期製造階段的半導體裝置100。在圖2A所示的實例中,載體10可以呈基本上平面板的形狀。在一些實例中,載體10可以包括或被稱為板、晶片、面板或條帶。另外,在一些實例中,載體10可以由金屬(例如,SUS)、晶片(例如,矽)、陶瓷(例如,氧化鋁)、玻璃(例如,鈉鈣玻璃)或其任何等同物中的至少一種或多種製成。載體10的厚度可以在大約50 μm(微米(micron/micrometer))到大約1000 μm的範圍內並且寬度可以在大約100 mm到大約300 mm的範圍內。載體10可以用於以集成方式處理多個組件,從而在形成基板110的同時,在附接電子裝置120的同時以及在施加囊封件130的同時提供結構完整性。
可以在載體10上形成導電層111。導電層111可以形成為使用經過圖案化的遮罩具有載體10的頂表面10x上的圖案化。導電層111可以成形為例如圓形、矩形或多邊形。在一些實例中,導電層111可以包括或稱為導電樁、凸點下金屬化(UBM)、下部襯墊或外部襯墊。在一些實例中,外部襯墊111可以由各種導電材料(例如,銅、金、銀或等同物)中的任何導電材料製成。另外,在一些實例中,外部襯墊111可以使用各種製程包含但不限於,濺射、化學鍍、電鍍、物理氣相沉積(PVD)、化學氣相沉積(CVD)、金屬有機化學氣相沉積(MOCVD)、原子層沉積(ALD)、低壓化學氣相沉積(LPCVD)、等離子體增強化學氣相沉積(PECVD)或等同物中的任何製程形成。在形成外部襯墊111之後,可以去除遮罩。外部襯墊111的厚度可以在大約0.1 μm到大約20 μm的範圍內。外部襯墊111可以是基板110的外部輸入/輸出端,以允許互連件140形成於或附接在基板110之下。
圖2B和圖3A示出了處於後期製造階段的半導體裝置100。在圖2B和圖3A所示的實例中,可以形成介電層112以覆蓋載體10的頂表面10x和外部襯墊111。可以通過圖案化介電層112來形成暴露外部襯墊111的基底111d的孔口112a。
介電層112可以包括或被稱為例如鈍化層、絕緣層或保護層。在一些實例中,介電層112可以包含電絕緣材料,包含例如聚合物、聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、模製材料、酚樹脂、環氧樹脂、矽樹脂或丙烯酸酯聚合物。在一些實例中,可以使用各種製程(例如,旋塗、噴塗、印刷、PVD、CVD、MOCVD、ALD、LPCVD或PECVD)中的任何製程形成介電層112。介電層112的厚度可以在大約3 μm到大約30 μm的範圍內。
在介電層112的頂表面上形成遮罩圖案之後,可以通過去除通過蝕刻暴露的介電層112的一部分來形成孔口112a。孔口112a可以包括或被稱為開口或孔。介電層112可以通過孔口112a暴露作為外部襯墊111的頂表面的一部分的基底111d。介電層112可以覆蓋外部襯墊111的頂部外周邊的一部分和載體10的頂表面10x。由孔口112a暴露的基底111d可以成形為例如圓形、矩形或多邊形。由孔口112a暴露的基底111d的形狀可以與外部襯墊111的形狀相同。由孔口112a暴露的基底111d的面積可以小於外部襯墊111的面積。另外,由孔口112a暴露的基底111d的直徑可以在大約10 μm到大約500 μm的範圍內。
圖2C和圖3B示出了處於後期製造階段的半導體裝置100。在圖2C和圖3B所示的實例中,可以形成導電層113以覆蓋外部襯墊111的基底111d和介電層112的暴露表面的一部分。
導電層113可以形成為具有多個圖案,所述多個圖案可以分別電連接到外部襯墊111的通過孔口112a暴露的基底111d。另外,電連接到外部襯墊111的基底111d的導電層113可以延伸到介電層112的頂表面。
導電層113可以包括或被稱為重新分佈層(RDL)、佈線圖案、跡線圖案或電路圖案。在一些實例中,重新分佈層113可以由各種導電材料(例如,銅、金、銀或等同物)中的任何導電材料製成。重新分佈層113可以使用各種製程,包含但不限於濺射、化學鍍、電鍍、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物中的任何製程形成。在重新分佈層113形成到覆蓋外部襯墊111的基底111d和介電層112的暴露表面的預定厚度之後,可以使用遮罩圖案化重新分佈層113以創建多個佈線圖案或跡線。重新分佈層113可以包含完全覆蓋外部襯墊111的基底111d的全通孔113a和從全通孔113a延伸到介電層112的頂表面的跡線113b。另外,重新分佈層113可以進一步包含在跡線113b的端部處形成的襯墊113c。襯墊113c可以定位於介電層112的頂表面上。跡線113b可以電連接全通孔113a和襯墊113c。全通孔113a和襯墊113c可以成形為例如圓形、矩形或多邊形。全通孔113a和襯墊113c的大小可以在大約15 μm到大約550 μm的範圍內。重新分佈層113的厚度可以在大約3 μm到大約20 μm的範圍內。
圖2D和圖3C示出了處於後期製造階段的半導體裝置100。在圖2D和圖3C所示的實例中,可以形成介電層114以完全覆蓋重新分佈層113和介電層112,並且可以通過圖案化介電層114來形成暴露重新分佈層113的基底113d的孔口114a。孔口114a可以將作為襯墊113c的頂表面的一部分的基底113d暴露到外部。基底113d可以大致定位於襯墊113c的中心處。介電層114可以覆蓋襯墊113c的頂表面的一部分。
介電層114可以包括或被稱為例如鈍化層、絕緣層或保護層。在一些實例中,介電層114可以包含電絕緣材料,包含例如聚合物、聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、模製材料、酚樹脂、環氧樹脂、矽樹脂或丙烯酸酯聚合物。在一些實例中,可以使用各種製程(例如,旋塗、噴塗、印刷、PVD、CVD、MOCVD、ALD、LPCVD或PECVD)中的任何製程形成介電層114。介電層114的厚度可以在大約3 μm到大約30 μm的範圍內。
在介電層114的頂表面上形成遮罩圖案之後,可以通過去除通過蝕刻暴露的介電層114來形成孔口114a。孔口114a可以包括或被稱為開口或孔。介電層114可以通過孔口114a暴露作為襯墊113c的頂表面的一部分的基底113d。由孔口114a暴露的基底113d可以成形為例如圓形、矩形或多邊形。由孔口114a暴露的基底113d的面積可以小於重新分佈層113的襯墊113c的面積。另外,由孔口114a暴露的基底113d的直徑的大小可以在大約10 μm到大約500 μm的範圍內。介電層114可以進一步包含覆蓋襯墊113c的頂表面的外圍部分114b。外圍部分114b可以定位於孔口114a周圍的外區域處,並且所述外圍部分的寬度可以在大約5 μm到大約50 μm的範圍內。
圖2E和圖3D示出了處於後期製造階段的半導體裝置100。在圖2E和圖3D所示的實例中,可以形成導電層115以覆蓋重新分佈層113的基底113d和介電層114的暴露表面的一部分。
基板110可以包括重新分佈層(RDL)基板。導電層115可以形成為具有多個圖案,所述多個圖案可以分別電連接到重新分佈層113的通過孔口114a暴露的基底113d。另外,電連接到重新分佈層113的導電層113可以延伸到介電層114的頂表面。導電層115可以通過重新分佈層113電連接到外部襯墊111。在一些實例中,可以在介電質114的頂側上提供第一導體115,並且可以在介電質114的底側上提供第二導體113。可以在介電質114中提供孔口114a。第一導體115可以包括通過孔口114a接觸第二導體113的襯墊基底113d的部分通孔115a。
導電層115可以包括或被稱為重新分佈層(RDL)、佈線圖案、跡線圖案或電路圖案。在一些實例中,重新分佈層115可以由各種導電材料(例如,銅、金、銀或等同物)中的任何導電材料製成。重新分佈層115可以使用各種製程,包含但不限於濺射、化學鍍、電鍍、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物中的任何製程形成。在重新分佈層115形成到覆蓋重新分佈層113的基底113d和介電層114的暴露表面的預定厚度之後,可以使用遮罩圖案來圖案化重新分佈層115以具有多個圖案。重新分佈層115可以包含覆蓋重新分佈層113的基底113d的一部分的部分通孔115a和從部分通孔115a延伸到介電層114的頂表面的跡線115b。另外,重新分佈層115可以進一步包含在跡線115b的端部處形成的襯墊115c。
部分通孔115a接觸但不完全覆蓋重新分佈層113的基底113d。另外,部分通孔115a接觸但不完全覆蓋孔口114a的側壁。在本發明實例中,部分通孔115a可以成形為具有恆定寬度的線路。部分通孔115a的端部115ax可以大致定位於重新分佈層113的基底113d的中心處。在重新分佈層113的基底113d中,未被部分通孔115a覆蓋的一部分可以保持暴露於外部。重新分佈層115可以通過部分通孔115a電連接到重新分佈層113。儘管部分通孔115a在此處示出為具有線性形狀,但是僅部分覆蓋重新分佈層113的基底113d的其它形狀,例如半圓形或其它幾何或非幾何形狀也是可能的。例如,部分通孔115a可以覆蓋基底113d的高達面積或直徑的一半或少於一半,或者覆蓋孔口114a的側壁的高達面積的一半或少於一半。
在一些實例中,如圖2B所示,基板110包括重新分佈層(RDL)基板,所述RDL基板包括第一介電層112和第一導電層113,所述第一介電層具有第一孔口112a,所述第一導電層位於第一介電層112上,其中第一導電層113具有第一孔口112a中的全通孔113a。如圖2E所示,RDL基板110可以包括第二介電層114和第二導電層115,所述第二介電層具有第二孔口114a,其中第二介電層114位於第一介電層112的頂表面上,所述第二導電層位於第二介電層114的頂表面上,其中第二導電層115具有在第二孔口114a中通過第二孔口114a電接觸第一導電層113的部分通孔115a。
跡線115b可以成形為具有恆定或幾乎恆定寬度的線路。另外,跡線115b的寬度可以與部分通孔115a的寬度相同。跡線115b的寬度可以在大約1 μm到大約100 μm的範圍內。跡線115b可以將部分通孔115a電連接到襯墊115c。跡線115b可以定位於介電層114的頂表面上。可以由從電連接到基底113d的部分通孔115a延伸的跡線115b部分覆蓋介電層114的外圍部分114b。另外,除了由跡線115b覆蓋的部分,介電層114的外圍部分114b的部分可以保持暴露。
襯墊115c可以成形為例如圓形、矩形或多邊形。襯墊115c可以定位於介電層114的頂表面上。襯墊115c的大小可以在大約15 μm到大約550 μm的範圍內。重新分佈層115的厚度可以在大約3 μm到大約20 μm的範圍內。另外,與形成完全覆蓋基底113d的全通孔的情況相比,重新分佈層115可以通過形成部分覆蓋基底113d和外圍部分114b的部分通孔115a來減少重新分佈層115的導電圖案之間的距離,由此實現襯墊之間或襯墊端部之間間距的小型化或減小,如下文關於圖2G和圖2F進一步詳細示出和描述的。
圖2F和圖3E示出了處於後期製造階段的半導體裝置100。在圖2F和圖3E所示的實例中,可以形成介電層116以完全覆蓋基底113d、重新分佈層115和介電層114。可以通過圖案化介電層116來形成暴露重新分佈層115的基底115d的孔口116a。孔口116a可以將作為重新分佈層115的襯墊115c的頂表面的一部分的基底115d暴露到外部。基底115d可以大致定位於襯墊115c的中心處。
介電層116可以包括或被稱為例如鈍化層、絕緣層或保護層。在一些實例中,介電層116可以包含電絕緣材料,包含例如聚合物、聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、模製材料、酚樹脂、環氧樹脂、矽樹脂或丙烯酸酯聚合物。在一些實例中,可以使用各種製程(例如,旋塗、噴塗、印刷、PVD、CVD、MOCVD、ALD、LPCVD或PECVD)中的任何製程形成介電層116。介電層116的厚度可以在大約3 μm到大約30 μm的範圍內。
在介電層116的頂表面上形成遮罩圖案之後,可以通過去除通過蝕刻暴露的介電層116的一部分來形成孔口116a。孔口116a可以包括或被稱為開口或孔。介電層116可以將作為重新分佈層115的襯墊115c的頂表面的一部分的基底115d暴露到外部。由孔口116a暴露的基底115d可以成形為例如圓形、矩形或多邊形。由孔口116a暴露的基底115d的面積可以小於襯墊115c的面積。另外,由孔口116a暴露的基底115d的直徑可以在大約10 μm到大約500 μm的範圍內。介電層116可以進一步包含覆蓋襯墊115c的頂表面的外圍部分116b。外圍部分116b可以定位於孔口116a周圍的外區域處並且所述外圍部分的寬度可以在大約5 μm到大約50 μm的範圍內。
圖2G和圖3F示出了處於後期製造階段的半導體裝置100。在圖2G和圖3F所示的實例中,可以形成導電層117以覆蓋重新分佈層115的基底115d和介電層116的暴露表面的一部分。在一些實例中,基板110包括介電質116、第一導體117和第二導體115,所述第一導體位於介電質116的頂側上,所述第二導體位於介電質116的底側上。介電質116可以具有孔口116a,並且第一導體117包括通過孔口116a接觸第二導體115的襯墊基底115d的部分通孔117a。在一些實例中,第一導體117包括第一跡線117e,所述第一跡線位於介電質116的頂側上並且與部分通孔117a相連續。在一些實例中,第一跡線117e和部分通孔117a的寬度相同。在一些實例中,部分通孔117a的端部117ax接觸第二導體115的襯墊基底115d,並且與部分通孔117a的端部117ax相鄰的跡線117e與第二導體115的襯墊基底115d的未被部分通孔117a覆蓋的一部分重疊。在一些實例中,第二導體115的相鄰襯墊115c之間可以存在間隙,並且跡線117e與第二導體115的襯墊115c與第二導體115的相鄰襯墊115c之間的間隙的一部分重疊。
導電層117可以形成為具有多個圖案,所述多個圖案可以分別電連接到重新分佈層115的通過孔口116a暴露的基底115d。另外,電連接到重新分佈層115的導電層117可以延伸到介電層116的頂表面。導電層117可以通過重新分佈層115以及重新分佈層113電連接到外部襯墊111。
導電層117可以包括或被稱為重新分佈層(RDL)、佈線圖案或電路圖案。在一些實例中,重新分佈層117可以由各種導電材料(例如,銅、金、銀或等同物)中的任何導電材料製成。重新分佈層117可以使用各種製程,包含但不限於濺射、化學鍍、電鍍、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物中的任何製程形成。在重新分佈層117形成到預定厚度以便覆蓋重新分佈層115的基底115d和介電層116的暴露表面之後,可以使用遮罩圖案來圖案化所述重新分佈層以具有多個佈線圖案或電路圖案。重新分佈層117可以包含覆蓋重新分佈層115的襯墊基底115d的一部分的部分通孔117a和從部分通孔117a延伸到介電層116的頂表面的跡線117b。另外,重新分佈層117可以進一步包含在跡線117b的端部處形成的襯墊117c。
部分通孔117a可以類似於部分通孔115a,並且可以類似地形成為所述部分通孔。部分通孔117a形成為使得不僅僅部分覆蓋重新分佈層115的襯墊基底115d。而且,部分通孔117a形成為使得不僅僅部分覆蓋介電層116的孔口116a的側壁。在一些實例中,部分通孔115a或部分通孔117a可以包括線性形狀或另一種形狀,如由圖3F的部分通孔117a的實例展示的半圓形形狀。在一些實例中,部分通孔115a或部分通孔117a可以覆蓋襯墊基底115d的一半或少於一半。
跡線117b可以類似於跡線115b,並且可以類似地形成為所述跡線。跡線117b可以形成於介電層116上,並且可以將部分通孔117a連接到襯墊117c。跡線117b可以定位於介電層116的頂表面上。還可以在兩個相鄰部分通孔117a之間形成如跡線117e等其它圖案。
在沒有到達彼此相鄰地定位於部分通孔117a的襯墊115c的外區域之上的介電外圍部分116b的部分或覆蓋在其之上的情況下,所述部分通孔覆蓋其襯墊基底115d(並且在此實例中僅部分覆蓋)。這使得通孔到通孔的距離117z比由類似於例如全通孔113a的全通孔代替覆蓋襯墊基底115d的情況更進一步最小化(圖2C,3B)。在一些實例中,減小的通孔到通孔的距離117z允許端部117ax以減小的間距更靠近地間隔開。另外,因為通過使用相鄰的部分通孔117a而不是相鄰的全通孔在導電層117中提供了另外的空間,所以在不違反相鄰跡線或電路圖案之間的最小距離的佈局設計規則的情況下,可以將如跡線117e等圖案定位於此類部分通孔117a之間。在一些實例中,與使用相鄰的全通孔的相應情況相比,使用相鄰的部分通孔117a可以允許將通孔到通孔的距離117z減少例如至少大約25%。例如,與使用將需要通孔到通孔的距離117z為至少大約40 μm的相鄰的全通孔的情況相比,使用相鄰部分通孔117a的情況將允許將通孔到通孔的距離117z最小化為至少大約30 μm,但是本發明揭露的範圍並不限於此方面。
襯墊117c可以類似於襯墊115c,並且可以類似地形成為所述襯墊。襯墊117c形成於介電層116上並且耦合到跡線117b。與形成完全覆蓋基底的全通孔的情況相比,重新分佈層117可以通過形成部分覆蓋基底115d和外圍部分116b的部分通孔117a來減少重新分佈層117的圖案中的每個圖案之間的距離,由此實現小型化。
圖2H示出了處於後期製造階段的半導體裝置100。在圖2H所示的實例中,可以形成介電層118以完全覆蓋基底115d、重新分佈層117和介電層116,並且可以通過圖案化介電層118來形成暴露重新分佈層117的基底117d的孔口118a。孔口118a可以將作為襯墊117c的頂表面的一部分的基底117d暴露到外部。
介電層118可以包括或被稱為例如鈍化層、絕緣層或保護層。在一些實例中,介電層118可以包含電絕緣材料,包含例如聚合物、聚醯亞胺(PI)、苯並環丁烯(BCB)、聚苯並噁唑(PBO)、雙馬來醯亞胺三嗪(BT)、模製材料、酚樹脂、環氧樹脂、矽樹脂或丙烯酸酯聚合物。在一些實例中,可以使用各種製程(例如,旋塗、噴塗、印刷、PVD、CVD、MOCVD、ALD、LPCVD或PECVD)中的任何製程形成介電層118。介電層118的厚度可以在大約3 μm到大約30 μm的範圍內。
在介電層118的頂表面上形成遮罩圖案之後,可以通過去除通過蝕刻暴露的介電層118來形成孔口118a。孔口118a可以包括或被稱為開口或孔。介電層118可以通過孔口118a暴露作為襯墊117c的頂表面的一部分的基底117d。由孔口118a暴露的基底117d可以成形為例如圓形、矩形或多邊形。由孔口118a暴露的基底117d的形狀可以與重新分佈層117的襯墊117c的形狀相同。由孔口118a暴露的基底117d的面積可以小於重新分佈層117的襯墊117c的面積。另外,由孔口118a暴露的基底117d的直徑可以在大約10 μm到大約500 μm的範圍內。
圖2I示出了處於後期製造階段的半導體裝置100。在圖2I所示的實例中,可以形成導電層119以覆蓋重新分佈層117的基底117d和介電層118的暴露表面。
導電層119可以形成為具有多個圖案,所述多個圖案可以分別電連接到重新分佈層117的通過孔口118a暴露的基底117d。另外,電連接到重新分佈層117的導電層119可以形成為部分覆蓋介電層118的頂表面。導電層119可以通過重新分佈層117以及重新分佈層115和重新分佈層113電連接到外部襯墊111。
導電層119可以包括或被稱為導電襯墊、互連襯墊、微襯墊、接合襯墊、凸點襯墊或凸點下金屬化(UBM)。在一些實例中,互連襯墊119可以由各種導電材料(例如,銅、金、銀或等同物)中的任何導電材料製成。可以在互連襯墊119上進一步形成由錫、金、銀、鎳、鈀或等同物製成的用於防止互連襯墊119被氧化的抗氧化層。互連襯墊119可以使用各種製程中的任何製程形成,所述製程包含但不限於濺射、化學鍍、電鍍、PVD、CVD、MODVD、ALD、LPCVD、PECVD或等同物。在互連襯墊119形成到覆蓋重新分佈層117的基底117d和介電層118的暴露表面的預定厚度之後,可以使用遮罩圖案來圖案化重新分佈層117以具有多個圖案。互連襯墊119的厚度可以在大約5 μm到大約300 μm的範圍內。
因為互連襯墊119是以上述方式形成的,所以可以完成基板110。儘管展示了包括五個導電層111、113、115、117和119以及四個介電層112、114、116和118的基板110,基板110的層數可以小於或大於五個導電層111、113、115、117和119以及四個介電層112、114、116和118,並且所揭露的請求像標的的範圍並不限於這些方面。
圖2J示出了處於後期製造階段的半導體裝置100。在圖2J所示的實例中,裝置120可以電連接到基板110的導電襯墊119。在一些實例中,基板110可以是重新分佈層(RDL)基板。
在一些實例中,拾放設備可以拾取電子裝置120以將其放置在基板110的互連襯墊119上。接下來,電子裝置120可以通過大批量回焊(mass reflow)、熱壓縮或雷射輔助接合來電連接到基板110。可以提供具有互連件122的電子裝置120,所述互連件電耦合到第一導體117或電耦合到導體115、導體113或導體111。
在一些實例中,電子裝置120可以包括或被稱為半導體晶粒或半導體晶片。另外,在一些實例中,電子裝置120可以包括邏輯晶粒、微控制單元、記憶體、數位訊號處理器、網絡處理器、電源管理單元、音頻處理器、RF電路、無線基帶晶片上系統處理器、特定應用積體電路或等同物中的至少一個。
在一些實例中,電子裝置120可以包含有源區域和非有源區域。另外,在一些實例中,有源區域可以安置成面對基板110。另外,在一些實例中,有源區域可以包含互連件121。在一些實例中,互連件121可以被稱為晶粒襯墊、接合襯墊、鋁襯墊、凸點、導電柱或導電樁。
另外,互連件121可以使用低熔點材料122連接到基板110的互連襯墊119。在一個實例中,低熔點材料122可以包括Sn、Ag、Pb、Cu、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi、Sn-Ag-Cu或等同物中的一種或多種。電子裝置120的互連件121和基板110的互連襯墊119可以通過低熔點材料122彼此電連接。互連件121和低熔點材料122的厚度可以在大約5 μm到大約300 μm的範圍內。
圖2K示出了處於後期製造階段的半導體裝置100。在圖2K所示的實例中,可以形成囊封件130以部分或完全覆蓋基板110的頂表面110x和電子裝置120的頂表面或側表面。在一些實例中,囊封件130可以包括或被稱為環氧模製化合物、環氧模製樹脂或密封劑。另外,在一些實例中,囊封件130可以包括或被稱為模製部件、密封部件、囊封部件、保護部件、封裝或主體部件。在一些實例中,囊封件130可以包含但不限於有機樹脂、無機填料、固化劑、催化劑、著色劑、阻燃劑等。可以通過各種製程中的任何製程形成基於囊封件130的模製。在一些實例中,囊封件130可以通過但不限於壓縮模製、傳遞模製、液相囊封件模製、真空層壓、膏印刷或膜輔助模製形成。囊封件130的厚度可以在大約50 μm到大約300 μm的範圍內。囊封件130可以囊封電子裝置120,由此保護處於封裝狀態的電子裝置120免受外部因素或環境的影響。在一些實例中,可以在基板110的接觸電子裝置120的側面的頂側上提供囊封件130。在一些實例中,基板110可以是重新分佈層(RDL)基板。
圖2L示出了處於後期製造階段的半導體裝置100。在圖2L所示的實例中,可以通過去除載體10來暴露基板110的底表面110y。如果去除了載體10,則可以通過基板110的底表面110y來暴露外部襯墊111和介電層112。可以通過普通研磨或化學蝕刻來去除載體10。可替代地,可以通過使用紫外(UV)輻射或雷射的釋放製程來去除載體10。
圖2M示出了處於後期製造階段的半導體裝置100。在圖2M所示的實例中,可以在外部襯墊111上形成暴露於基板110的底表面110y的互連件140。
互連件140可以電連接到外部襯墊111的底表面。互連件140可以通過基板110的導電層111、113、115、117和119電連接到電子裝置120。在一些實例中,互連件140可以包含錫(Sn)、銀(Ag)、鉛(Pb)、銅(Cu)、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu或等同物。
互連件140可以通過例如球落製程、絲網印刷製程或電鍍製程形成。在一些實例中,互連件140可以通過形成導電材料,包含基板110的外部襯墊111的底表面上的焊料、使用球落製程的導電層122,然後通過回焊製程來形成。在此階段,可以將基板110的底表面110y安置為面朝上。互連件140可以包括或被稱為如焊球等導電球、如銅柱等導電柱或具有銅柱上的焊帽的導電樁。互連件140的大小可以在大約20 μm到大約500 μm的範圍內。
本揭示內容包含對如本文所述的某些實例的引用。本領域的技術人員應理解的是,在不脫離本揭示內容的範圍的情況下,可以作出各種改變並且可以取代等同物。另外,在不脫離本揭示內容的範圍的情況下,可以對所揭露的實例進行修改。因此,本揭示內容旨在並不受限於所揭露的實例,而是本揭示內容將包含所有實例,包含落入所附申請專利範圍的範疇內的實例。
10:載體
10x:頂表面
100:半導體裝置
101:半導體封裝 / 封裝
110:基板
110y:底表面
111:導電層 / 外部襯墊 / 導體
111d:基底
112:介電層 / 第一介電層
112a:孔口 / 第一孔口
113:導電層 / 重新分佈層 / 導體
113a:全通孔
113b:跡線
113c:襯墊
113d:基底
114:介電層 / 第二介電層
114a:孔口 / 第二孔口
114b:外圍部分
115:導電層 / 第一導體 / 重新分佈層 / 第二導體 / 導體
115a:部分通孔
115ax:端部
115b:跡線
115c:襯墊
115d:基底
116:介電層
116a:孔口
116b:外圍部分
117:導電層 / 第一導體 / 重新分佈層
117a:部分通孔
117ax:端部
117b:跡線
117c:襯墊
117d:基底
117e:第一跡線 / 跡線
117z:距離
118:介電層
118a:孔口
119:導電層 / 互連襯墊 / 導電襯墊
120:電子裝置 / 裝置
121:端子
122:互連件
130:囊封件
140:互連件
[圖1]示出了示例半導體裝置的橫截面視圖。
[圖2A到2M]示出了用於製造示例半導體裝置的示例方法的橫截面視圖。
[圖3A到3F]示出了圖2B到2G所示的半導體裝置的橫截面視圖中的局部放大平面視圖。
100:半導體裝置
101:半導體封裝/封裝
110:基板
111:導電層/外部襯墊/導體
111d:基底
112:介電層/第一介電層
113:導電層/重新分佈層/導體
114:介電層/第二介電層
115:導電層/第一導體/重新分佈層/第二導體/導體
116:介電層
117:導電層/第一導體/重新分佈層
117e:第一跡線/跡線
118:介電層
119:導電層/互連襯墊/導電襯墊
120:電子裝置/裝置
121:端子
122:互連件
130:囊封件
140:互連件
Claims (20)
- 一種半導體裝置,其包括: 基板,所述基板包括介電質、第一導體以及第二導體,所述第一導體位於所述介電質的頂側上,所述第二導體位於所述介電質的底側上,其中所述介電質具有孔口,並且所述第一導體包括部分通孔,所述部分通孔通過所述孔口接觸所述第二導體的襯墊; 電子裝置,所述電子裝置具有電耦合到所述第一導體的互連件;以及 囊封件,所述囊封件位於所述基板的頂側上,所述囊封件接觸所述電子裝置的側面。
- 根據請求項1所述的半導體裝置,其中所述基板包括第三導體和第四導體,所述第三導體位於所述介電質的所述頂側上,所述第四導體位於所述介電質的所述底側上,其中所述介電質具有另外的孔口,並且所述第三導體包括部分通孔,所述部分通孔通過所述另外的孔口接觸所述第四導體的襯墊。
- 根據請求項2所述的半導體裝置,其進一步包括跡線,所述跡線位於所述介電質上且在所述第一導體的所述部分通孔與所述第三導體的所述部分通孔之間。
- 根據請求項2所述的半導體裝置,其中所述第一導體的所述部分通孔的端部和所述第三導體的所述部分通孔的端部間隔開30微米或更少。
- 根據請求項2所述的半導體裝置,其中: 所述第一導體包括第一跡線,所述第一跡線位於所述介電質的所述頂側上並且與所述部分通孔相連續;並且 所述第一跡線和所述部分通孔的寬度相同。
- 根據請求項1所述的半導體裝置,其中: 所述部分通孔的端部接觸所述第二導體的所述襯墊;並且 與所述部分通孔的所述端部相鄰的跡線與所述第二導體的所述襯墊的未被所述部分通孔覆蓋的一部分重疊。
- 根據請求項6所述的半導體裝置,其中所述跡線與位於所述第二導體的所述襯墊與相鄰襯墊之間的間隙的一部分重疊。
- 根據請求項1所述的半導體裝置,其中所述部分通孔包括線性形狀。
- 根據請求項1所述的半導體裝置,其中所述部分通孔包括半圓形形狀。
- 根據請求項1所述的半導體裝置,其中所述部分通孔覆蓋所述襯墊的由所述孔口暴露的基底部分的一半或少於一半。
- 根據請求項1所述的半導體裝置,其中所述部分通孔的端部位於所述第二導體的所述襯墊的中心處。
- 根據請求項1所述的半導體裝置,其中所述部分通孔覆蓋所述孔口的側壁的一半或少於一半。
- 一種用於製造半導體裝置的方法,所述方法包括: 在介電質的頂側上提供第一導體; 在所述介電質的底側上提供第二導體; 在所述介電質中提供孔口,其中所述第一導體包括部分通孔,所述部分通孔通過所述孔口接觸所述第二導體的襯墊; 提供電子裝置,所述電子裝置具有與所述第一導體電耦合的互連件;以及 提供囊封件,所述囊封件位於所述介電質的頂側上並且接觸所述電子裝置的側面。
- 根據請求項13所述的方法,其進一步包括: 在所述介電質的所述頂側上提供第三導體; 在所述介電質的所述底側上提供第四導體;以及 在所述介電質中提供另外的孔口,其中所述第三導體包括部分通孔,所述部分通孔通過所述另外的孔口接觸所述第四導體的襯墊。
- 根據請求項14所述的方法,其中與穿過同一介電質的全通孔之間的距離相比,所述第一導體的所述部分通孔和所述第三導體的所述部分通孔在所述介電質中間隔開的距離減小。
- 根據請求項14所述的方法,其中與用於穿過同一介電質的全通孔的襯墊的大小相比,所述第二導體的用於所述部分通孔的所述襯墊的大小減小。
- 一種半導體結構,其包括: 重新分佈層(RDL)基板,所述重新分佈層基板包括: 第一介電層,所述第一介電層具有第一孔口; 第一導電層,所述第一導電層位於所述第一介電層上,其中所述第一導電層具有所述第一孔口中的全通孔; 第二介電層,所述第二介電層具有第二孔口,其中所述第二介電層位於所述第一介電層的頂表面上;以及 第二導電層,所述第二導電層位於所述第二介電層的頂表面上,其中所述第二導電層具有所述第二孔口中的部分通孔,所述部分通孔通過所述第二孔口接觸所述第一導電層; 電子裝置,所述電子裝置位於所述重新分佈層基板的頂側上,其中所述電子裝置包括與所述第二導電層電耦合的互連件;以及 囊封件,所述囊封件位於所述重新分佈層基板的所述頂側上,所述囊封件接觸所述電子裝置的側面。
- 根據請求項17所述的半導體結構,其中所述第一介電層具有第三孔口並且所述第一導電層具有所述第三孔口中的全通孔,並且其中所述第二介電層具有第四孔口並且所述第二導電層具有所述第四孔口中的部分通孔,其中所述第一導電層的所述全通孔接觸暴露在所述第一介電層的底表面處的下部襯墊,並且所述第二導電層的所述部分通孔接觸所述第一導電層的襯墊,其中所述第一導電層的所述襯墊的大小小於所述下部襯墊的大小。
- 根據請求項17所述的半導體裝置,其中: 所述部分通孔的端部接觸所述第一導電層的襯墊;並且 與所述部分通孔的所述端部相鄰的跡線與所述第一導電層的所述襯墊的未被所述部分通孔覆蓋的一部分重疊。
- 根據請求項17所述的半導體結構,其中所述部分通孔覆蓋暴露在所述孔口的底部處的所述第一導電層的一半或少於一半。
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