CN113192922A - 半导体装置和制造半导体装置的方法 - Google Patents

半导体装置和制造半导体装置的方法 Download PDF

Info

Publication number
CN113192922A
CN113192922A CN202011486758.2A CN202011486758A CN113192922A CN 113192922 A CN113192922 A CN 113192922A CN 202011486758 A CN202011486758 A CN 202011486758A CN 113192922 A CN113192922 A CN 113192922A
Authority
CN
China
Prior art keywords
substrate
semiconductor device
examples
tab
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011486758.2A
Other languages
English (en)
Inventor
郑季洋
张胜哲
骆·休莫勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anrely Technology Singapore Holdings Pte Ltd
Amkor Technology Singapore Holding Pte Ltd
Original Assignee
Anrely Technology Singapore Holdings Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anrely Technology Singapore Holdings Pte Ltd filed Critical Anrely Technology Singapore Holdings Pte Ltd
Publication of CN113192922A publication Critical patent/CN113192922A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45664—Palladium (Pd) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1426—Driver
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/14335—Digital signal processor [DSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

半导体装置和制造半导体装置的方法。在一个实例中，一种电子组合件包括第一半导体装置和第二半导体装置。所述第一半导体装置和所述第二半导体装置中的每一个包括：衬底，所述衬底包括顶表面和导电结构；电子组件，所述电子组件处于所述衬底的所述顶表面之上；介电材料，所述介电材料处于所述衬底的所述顶表面之上并且接触所述电子组件的一侧；衬底接片，所述衬底接片处于衬底的一端处并且未被所述介电材料覆盖，其中所述衬底的所述导电结构在所述衬底接片处暴露；以及互连件，所述互连件电耦接到所述第一半导体装置的所述衬底接片处的所述导电结构和所述第二半导体装置的所述衬底接片处的所述导电结构。本文中还公开了其它实例和相关方法。

Description

半导体装置和制造半导体装置的方法
技术领域
本公开总体上涉及电子装置，并且更具体地，涉及半导体装置和用于制造半导体装置的方法。
背景技术
现有的半导体封装和用于形成半导体封装的方法存在不足之处，例如，从而造成成本过多、可靠性降低、性能相对较低或封装大小太大。对于本领域的技术人员来说，通过将常规和传统方法与本公开进行比较并且参考附图，此类方法的另外的局限性和缺点将变得显而易见。
发明内容
根据本发明的态样，一种电子组合件，其包括：第一半导体装置和第二半导体装置，其中所述第一半导体装置和所述第二半导体装置中的每一个包括：衬底，所述衬底包括顶表面和导电结构；电子组件，所述电子组件处于所述衬底的所述顶表面之上；介电材料，所述介电材料处于所述衬底的所述顶表面之上并且接触所述电子组件的一侧；衬底接片，所述衬底接片处于衬底的一端处并且未被所述介电材料覆盖，其中所述衬底的所述导电结构在所述衬底接片处暴露；以及互连件，所述互连件电耦接到所述第一半导体装置的所述衬底接片处的所述导电结构和所述第二半导体装置的所述衬底接片处的所述导电结构。电子组合件进一步包括基础结构，所述基础结构包括顶表面，其中所述第一半导体装置处于所述基础结构的所述顶表面之上，并且所述第二半导体装置处于所述基础结构的所述顶表面之上。在电子组合件中，所述互连件包括接合线。在电子组合件中，所述互连件包括线夹。在电子组合件中，所述第二半导体装置相对于所述第一半导体装置倒置，并且所述第二半导体装置的所述衬底接片处于所述第一半导体装置的所述衬底接片之上。在电子组合件中，所述互连件包括焊料。在电子组合件中，所述互连件包括铜柱。在电子组合件中，所述互连件包括互连衬底。在电子组合件中，所述互连件包括柔性衬底。在电子组合件中，所述互连件包括引线框架。在电子组合件中：所述基础结构包括第一支撑结构、第二支撑结构和处于所述第一支撑结构与所述第二支撑结构之间的中间结构，所述第一半导体装置耦接到所述第一支撑结构的顶表面并且所述第二半导体装置耦接到所述第二支撑结构的顶表面，并且所述第二半导体装置相对于所述第一半导体装置倒置，其中所述第二半导体装置的所述衬底接片处于所述第二半导体装置的所述衬底接片之上。
根据本发明的另一态样，一种方法，其包括：在第一衬底的顶表面之上提供第一电子组件，其中所述第一衬底包括耦接到所述第一电子组件的第一导电结构，所述第一衬底在所述顶表面上具有第一衬底接片，并且所述第一导电结构在所述第一衬底接片处暴露；以及在所述第一衬底的所述顶表面之上提供第一介电结构，其中所述第一介电结构接触所述第一电子组件的一侧并且所述第一衬底接片未被所述第一介电结构覆盖。方法进一步包括在所述第一衬底的所述顶表面之上提供所述第一电子组件之前，在载体上提供所述第一衬底，并且在所述第一衬底的所述顶表面上提供所述第一介电结构之后，去除所述载体。方法进一步包括：在第二衬底的顶表面之上提供第二电子组件，其中所述第二衬底包括耦接到所述第二电子组件的第二导电结构，所述第二衬底在所述顶表面上具有第二衬底接片，并且所述第二导电结构在所述第二衬底接片处暴露；在所述第二衬底的所述顶表面之上提供第二介电结构，其中所述第二介电结构接触所述第二电子组件的一侧并且所述第二衬底接片未被所述第二介电结构覆盖；以及将所述第一衬底的所述第一衬底接片耦接到所述第二衬底的所述第二衬底接片。
根据本发明的又另一态样，一种方法，其包括：提供第一半导体装置和第二半导体装置，其中所述提供所述第一半导体装置和所述第二半导体装置中的每一个包括：提供包括顶表面和导电结构的衬底；在所述衬底的所述顶表面之上提供电子组件；在衬底的一端处提供衬底接片，其中所述衬底的所述导电结构在所述衬底接片处暴露；以及提供互连件，所述互连件电耦接到所述第一半导体装置的所述衬底接片处的所述导电结构和所述第二半导体装置的所述衬底接片处的所述导电结构。在方法中，所述互连件包括接合线。在方法中，所述互连件包括线夹。在方法中，所述互连件包括焊料。在方法中，所述互连件包括铜柱。方法进一步包括提供介电材料，所述介电材料在所述衬底的所述顶表面之上并且接触所述电子组件的一侧，其中所述介电材料不覆盖所述衬底接片。
附图说明
图1示出了示例半导体装置的横截面视图。
图2A到2D示出了用于制造示例半导体装置的示例方法的横截面视图。
图3A到3F示出了用于制造示例半导体装置的示例方法的横截面视图。
图4示出了示例电子组合件的横截面视图。
图5A到5D示出了用于制造示例电子组合件的示例方法的横截面视图。
图6示出了示例电子组合件的横截面视图。
图7A和7B示出了用于制造示例电子组合件的示例方法的横截面视图。
图8示出了示例电子组合件的横截面视图。
图9A到9C示出了用于制造示例电子组合件的示例方法的横截面视图。
图10示出了示例电子组合件的横截面视图。
图11A和11B示出了用于制造示例电子组合件的示例方法的横截面视图。
图12示出了示例电子组合件的横截面视图。
图13A到13D示出了用于制造示例电子组合件的示例方法的横截面视图。
图14示出了示例电子组合件的横截面视图。
图15A到15E示出了用于制造示例电子组合件的示例方法的横截面视图。
具体实施方式
以下讨论提供了半导体装置和制造半导体装置的方法的各种实例。此类实例是非限制性的，并且所附权利要求的范围不应限于所公开的特定实例。在以下讨论中，术语“实例”和“例如”是非限制性的。
附图展示了总体构造方式，并且众所周知的特征和技术的描述和细节可以省略以避免不必要地模糊本公开。另外，附图中的元件不一定按比例绘制。例如，附图中的元件中的一些元件的尺寸可以相对于其它元件放大以有助于改善对本公开所讨论的实例的理解。不同附图中的相同附图标记指示相同的元件。
术语“或”意指由“或”连接的列表中的项中的任何一个或多个项。作为实例，“x或y”意指三元素集合{(x),(y),(x,y)}中的任何元素。作为另一个实例，“x、y或z”意指七元素集合{(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}中的任何元素。术语“包括(comprises)”、“包括(comprising)”、“包含(includes)”或“包含(including)”是“开放式”术语并且指定存在所陈述特征，但不排除存在或添加一个或多个其它特征。术语“第一”、“第二”等在本文中可以用于描述各种元件，并且这些元件不应受这些术语限制。这些术语仅用于将一个元件与另一个元件进行区分。因此，例如，在不脱离本公开的教导的情况下，本公开中讨论的第一元件可以被称为第二元件。
除非另外指定，否则术语“耦接”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。例如，如果元件A耦接到元件B，则元件A可以直接接触元件B或通过中间元件C间接连接到元件B。类似地，术语“之上”或“上”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。
在一个实例中，一种电子组合件包括第一半导体装置和第二半导体装置。所述第一半导体装置和所述第二半导体装置中的每一个包括：衬底，所述衬底包括顶表面和导电结构；电子组件，所述电子组件处于所述衬底的所述顶表面之上；介电材料，所述介电材料处于所述衬底的所述顶表面之上并且接触所述电子组件的一侧；衬底接片，所述衬底接片处于衬底的一端处并且未被所述介电材料覆盖，其中所述衬底的所述导电结构在所述衬底接片处暴露；以及互连件，所述互连件电耦接到所述第一半导体装置的所述衬底接片处的所述导电结构和所述第二半导体装置的所述衬底接片处的所述导电结构。
在另一个实例中，一种制造半导体装置或半导体装置的组合件的方法包括：在第一衬底的顶表面之上提供第一电子组件，其中所述第一衬底包括耦接到所述第一电子组件的第一导电结构，所述第一衬底在所述顶表面上具有第一衬底接片，并且所述第一导电结构在所述第一衬底接片处暴露；以及在所述第一衬底的所述顶表面之上提供第一介电结构，其中所述第一介电结构接触所述第一电子组件的一侧并且所述第一衬底接片未被所述第一介电结构覆盖。
在另外的实例中，一种制造半导体装置或半导体装置的组合件的方法包括提供第一半导体装置和第二半导体装置。提供所述第一半导体装置和所述第二半导体装置中的每一个包括：提供包括顶表面和导电结构的衬底；在所述衬底的所述顶表面之上提供电子组件；在衬底的一端处提供衬底接片，其中所述衬底的所述导电结构在所述衬底接片处暴露；以及提供互连件，所述互连件电耦接到所述第一半导体装置的所述衬底接片处的所述导电结构和所述第二半导体装置的所述衬底接片处的所述导电结构。
本公开中包含其它实例。此类实例可以存在于本公开的附图中、权利要求中或说明书中。
图1示出了示例半导体装置100的横截面视图。在图1所示的实例中，半导体装置100可以包括衬底110、电子组件121、122或123、电介质130和外部互连件150。
在一些实例中，衬底110可以包括介电结构110a、导电结构110b和衬底接片111。衬底110可以包括顶表面110c和与顶表面110c相对的底表面110d。在一些实例中，介电材料130可以处于衬底110的顶表面110c之上并且可以接触电子组件121、122或123中的一个或多个电子组件的一侧。一个或多个电子组件121、122或123可以处于衬底110的顶表面之上。衬底110、电介质130和外部互连件150可以被称为半导体封装或封装并且可以保护电子组件121、122或123免于外部元件或环境暴露。在一些实例中，半导体封装可以提供外部组件与电子组件121、122或123之间的电连接。在一些实例中，衬底接片111可以处于衬底110的一端处并且不被介电材料130覆盖。导电结构110b可以在衬底接片111处暴露。
图2A到2D示出了用于制造半导体装置100的示例方法的横截面视图。图2A示出了处于早期制造阶段的半导体装置100的横截面视图。
在图2A所示的实例中，衬底110可以包括顶表面110c和与顶表面110c相对的底表面110d，并且衬底110的底表面110d可以耦接到载体1的表面。尽管示出了单个衬底110，但这不是对本公开的限制。在其它实例中，多个衬底110可以布置在载体1上，以在行式或列式方向上彼此间隔开。
衬底110可以包括介电结构110a、导电结构110b和衬底接片111。衬底接片111可以包括在衬底110的顶表面110c处暴露的导电结构110b。衬底接片111可以位于衬底110的至少一侧或一端处或附近。另外，衬底接片111可以被暴露以形成半导体装置100与外部组件或另一个半导体装置之间的电连接路径。
在一些实例中，衬底110可以是预成型衬底。预成型衬底可以在附接到电子组件或电子装置之前制造并且可以包括相应导电层之间的介电层。导电层可以包括铜并且可以使用电镀工艺形成或提供。介电层可以是可以按预成型膜的形式而不是以液体的形式附接的相对较厚的非光可限定层并且可以包含具有用于刚性或结构性支撑的如线股、织物或其它无机颗粒等填料的树脂。由于介电层是非光可限定的，因此可以通过使用钻机或激光器来形成或提供如通孔或开口等特征。在一些实例中，介电层可以包括预浸材料或味之素堆积膜(Ajinomoto Buildup Film)(ABF)。预成型衬底可以包含永久性核心结构或载体，例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料，并且介电层和导电层可以形成或提供于永久性核心结构上。在一些实例中，预成型衬底可以是无核心衬底并且可以省略永久性核心结构，并且介电层和导电层可以形成或提供于在形成介电层和导电层之后并且在附接到电子装置之前被去除的牺牲载体上。预成型衬底可以被称为印刷电路板(PCB)或层压衬底。此类预成型衬底可以通过半加成工艺或改良的半加成工艺形成或提供。
在一些实例中，衬底110可以是再分布层(“RDL”)衬底。RDL衬底可以包括一个或多个介电层和一个或多个导电再分布层，所述一个或多个介电层和所述一个或多个导电再分布层：(a)可以在RDL衬底要电耦接的电子组件之上逐层形成或提供；或者(b)可以在载体之上逐层形成或提供，所述载体可以在电子组件和RDL衬底耦接在一起之后完全去除或至少部分地去除。RDL衬底可以在圆形晶圆上以晶圆级工艺逐层制造为晶圆级衬底或在矩形或方形面板载体上以面板级工艺逐层制造为面板级衬底。RDL衬底可以以加成堆积工艺形成或提供，所述加成堆积工艺可以包含与定义相应导电再分布图案或迹线的一个或多个导电层交替堆叠的一个或多个介电层，所述导电再分布图案或迹线被配置成共同：(a)将电迹线扇出电子组件的占用空间外；或者(b)将电迹线扇进电子组件的占用空间内。导电图案可以使用镀覆工艺，例如电镀工艺或无电镀工艺形成或提供。导电图案可以包括导电材料，例如铜或其它可镀覆金属。可以使用光图案化工艺，例如光刻工艺和光刻胶材料形成光刻掩模来制作导电图案的位置。可以利用可以包含光刻掩模的光图案化工艺来图案化RDL衬底的介电层，光通过所述光刻掩模暴露到光图案期望的特征，如介电层中的通孔。因此，介电层可以由光可限定的有机介电材料，例如聚酰亚胺(PI)、苯并环丁烯(BCB)或聚苯并恶唑(PBO)制成。此类介电材料可以以液体形式旋涂或以其它方式涂覆而不是以预成型膜的形式附接。为了允许适当地形成期望的光限定特征，此类光可限定介电材料可以省略结构增强剂或可以不含填料，没有可能会干扰来自光图案化工艺的光的线股、织物或其它颗粒。在一些实例中，不含填料的介电材料的此类不含填料特性可以允许减小所得介电层的厚度。尽管上文描述的光可限定介电材料可以是有机材料，但是在一些实例中，RDL衬底的介电材料可以包括一个或多个无机介电层。一个或多个无机介电层的一些实例可以包括氮化硅(Si3N4)、氧化硅(SiO2)或氮氧化硅(SiON)。所述一个或多个无机介电层可以通过使用氧化或氮化工艺而不是使用光限定的有机介电材料使无机介电层生长来形成或提供。此类无机介电层可以不含填料，没有线股、织物或其它不同的无机颗粒。在一些实例中，RDL衬底可以省略永久性核心结构或载体，例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料，并且这些类型的RDL衬底可以被称为无核心衬底。
在一些实例中，衬底110可以包括或被称为预成型衬底、RDL衬底、印刷电路板(PCB)、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。
在一些实例中，介电结构110a可以具有平坦顶表面和底表面。介电结构110a的顶表面和底表面可以与衬底110的顶表面110c和底表面110d平行。在一些实例中，介电结构110a可以被称为介电层或核心层。介电结构110a可以包含一个或多个介电层。在一些实例中，介电结构110a可以包括环氧树脂、酚树脂、玻璃环氧树脂、聚酰亚胺、聚酯、环氧模制化合物、陶瓷、双马来酰亚胺三嗪(BT)或FR4。在一些实例中，介电结构110a的厚度可以在大约0.1毫米(mm)到大约10mm的范围内。介电结构110a可以用于防止翘曲或保持衬底110的平坦性。
导电结构110b可以耦接到介电结构110a。在一些实例中，导电结构110b可以被称为导体、导电材料、导电通孔、电路图案、迹线或布线图案。在一些实例中，导电结构110b的一部分可以暴露以用于电耦接到电子组件121、122或123或外部互连件150。在一些实例中，导电结构110b可以通过导体、导电材料、导电通孔、衬底焊盘(substrate land)、导电焊盘、衬底垫(substrate pad)、布线垫、连接垫、微型垫或凸点下金属(UBM)电耦接到电子组件121、122或123或外部互连件150。在一些实例中，导电结构110b可以包括铜、铝、铁、镍、金、银、钯或锡。
在一些实例中，衬底接片111可以在衬底110的顶表面110c处或附近暴露。衬底接片111可以包括在衬底110的一侧处或附近暴露的导电结构110b。在一些实例中，衬底接片111可以包括向上弯曲并暴露的导电结构110b。在一些实例中，衬底接片111可以提供暴露的电连接路径。
在一些实例中，载体1可以包括平坦结构。载体1可以被称为板、晶圆、面板、半导体载体或条带。在一些实例中，载体1可以包括钢、不锈钢、铝、铜、陶瓷、玻璃、硅、金属、合金或半导体材料。载体1的厚度可以在大约1mm到大约1.5mm的范围内并且宽度可以在大约200mm到大约510mm的范围内。
在一些实例中，载体1可以在半导体装置100的制造期间支撑多个组件。例如，载体1可以提供用于支撑衬底110、电子组件121、122或123以及电介质130的基础结构。在一些实例中，电子组合件10可以包括包含顶表面的基础结构，其中半导体装置100和200可以处于基础结构的顶表面之上。
在一些实例中，接合层2可以形成或提供于载体1的顶表面上。用于形成接合层2的实例可以包括使用：涂覆工艺，例如旋涂、叶片涂覆(blade)、铸造(casting)、刷涂、喷涂、狭缝式模具涂覆(slot die coating)、帘幕式涂覆(curtain coating)、斜板式涂覆(slidecoating)或边缘刮刀式涂覆(knife over edge coating)；印刷工艺，例如丝网印刷、移印、凹版印刷、柔性版涂覆或胶版印刷；具有涂覆和印刷的中间特征的喷墨印刷工艺；或者粘合膜或胶带的直接附接。可以在接合层2上形成或提供衬底110。
接合层2可以被称为临时粘合膜或临时胶带。接合层2可以包括热释放带或紫外线(UV)释放带。在一些实例中，接合层2的接合强度可以通过热或UV辐射来降低。在一些实例中，临时接合层2可以在后期制造阶段从衬底110或载体1去除。
图2B示出了处于后期制造阶段的半导体装置100的横截面视图。在图2B所示的实例中，电子组件121和122可以提供于衬底110的表面110c上或之上，并且电子组件123可以处于电子组件122上。在一些实例中，电子组件121、122或123可以电耦接到衬底110的导电结构110b。
在一些实例中，拾取和放置设备可以拾取电子组件121、122或123、将电子组件121和122放置在衬底110上并且将组件123放置在组件122上。在一些实例中，可以使用质量回流、热压缩或激光辅助接合(LAB)工艺来将组件121、122或123彼此附接并且附接到衬底110或将衬底110电耦接到组件121、122或123。
在一些实例中，电子组件121、122或123可以包括半导体管芯或半导体芯片。在一些实例中，电子组件121、122或123可以包括半导体材料，例如硅(Si)。电子组件121、122或123可以包括无源电子电路元件(未示出)或有源电子电路元件(未示出)，如晶体管。在一些实例中，电子组件121、122或123可以包括专用集成电路、逻辑管芯、微控制单元、存储器、数字信号处理器、网络处理器、电源管理单元、音频处理器、射频(RF)电路或无线基带片上系统处理器。
在一些实例中，电子组件122可以包括硅通孔(TSV)中介层并且可以提供电子组件123与衬底110之间的导电路径。电子组件121、122或123各自的厚度可以在大约50μm到大约780μm的范围内。电子组件121、122或123各自的宽度可以在大约3mm到大约10mm的范围内。
在一些实例中，电子组件121、122或123可以包括无源装置。在一些实例中，电子组件121、122或123可以包括电阻器、电容器、电感器或连接器。另外，电子组件121、122或123可以电耦接到衬底110的导电结构110b。
在一些实例中，电子组件121、122或123可以包括电互连件，例如互连件125。在一些实例中，互连件125可以将电子组件121、122或123的管芯端子电耦接到衬底110。在一些实例中，互连件125可以包括晶圆凸点、柱晶圆凸点、铜柱晶圆凸点、包括在铜柱的外部端部上形成或提供的焊料尖端的铜柱晶圆凸点、铜螺柱凸点、金螺柱凸点或焊料晶圆凸点。在一些实例中，互连件125可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、铝、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。
图2C示出了处于后期制造阶段的半导体装置100的横截面视图。在图2C所示实例中，电介质130可以形成或提供于衬底110的顶表面110c上或之上以及组件121、122或123上。在一些实例中，电介质130可以接触衬底110的顶表面110c以及组件121、122或123的顶表面、底表面或侧表面，以包封电子组件121、122或123。在一些实例中，电介质130可以被称为包封件。
在一些实例中，可以形成或提供包封件130以暴露衬底接片111，其中衬底接片111不被包封件或介电材料130覆盖。在一些实例中，衬底接片111可以电耦接到外部电路或另一个半导体装置。
在一些实例中，包封件130可以包括环氧模制化合物、环氧模制树脂或密封剂。在一些实例中，包封件130可以被称为模制部件、密封部件、包封部件、保护部件或主体。在一些实例中，包封件130可以包括有机树脂、无机填料、固化剂、催化剂、偶联剂、着色剂或阻燃剂。在一些实例中，包封件130可以通过压缩模制、传递模制、液相包封件模制、真空层压、膏印刷或膜辅助模制来形成或提供。包封件130的厚度可以在大约0.1mm到大约1mm的范围内。包封件130可以保护衬底110和电子组件121、122或123免于外部元件或环境暴露。在一些实例中，在衬底110的顶表面之上提供电子组件121、122或123之前，可以将衬底110提供在载体1上。
图2D示出了处于后期制造阶段的半导体装置100的横截面视图。在图2D所示的实例中，载体1可以与图2C所示的组合件分离。在一些实例中，可以通过向图2C所示的组合件施加热或UV光降低接合层2的接合强度来去除载体1。在一些实例中，可以通过施加物理力从衬底110拉出接合层2和载体1来去除接合层2和载体1。在其它实例中，可以使用研磨工艺来去除接合层2和载体1。在一些实例中，可以在顶表面衬底110上提供电介质或包封件130之后去除载体1。
另外，外部互连件150可以耦接到衬底110的底表面110d。在一些实例中，外部互连件150可以包括导电材料。在一些实例中，外部互连件150可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、铝、金、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。在一些实例中，外部互连件150可以通过焊球滴落工艺、丝网印刷或电镀来形成或提供。用于制造互连件150的实例可以包括：使用焊球滴落工艺在衬底110的底表面110d上形成包括焊料的导电材料、然后执行焊料回流工艺以将热施加到半导体装置100。在一些实例中，外部互连件150可以被称为导电球、焊球、导电柱或铜柱。在一些实例中，互连件150可以包括铜柱，所述铜柱包括铜柱的端部区域上的焊料盖。外部互连件150的宽度可以在大约0.1mm到大约0.5mm的范围内。在一些实例中，外部互连件150可以被称为半导体装置100的外部输入/输出(I/O)端子。
图3A到3F示出了用于制造半导体装置100的示例方法的横截面视图。图3A示出了处于早期制造阶段的半导体装置100的横截面视图。在图3A所示的实例中，载体1可以包括平坦结构并且可以在半导体装置100的制造期间支撑多个组件。
图3B示出了处于后期制造阶段的半导体装置100的横截面视图。在图3B所示的实例中，可以在载体1上形成或提供接合层2。在一些实例中，电子组件121和122可以处于接合层2上，并且电子组件123可以处于电子组件122上。
图3C示出了处于后期制造阶段的半导体装置100的横截面视图。在图3C所示实例中，电介质130可以形成或提供于接合层2的顶表面上以及组件121、122或123上。在一些实例中，电介质130可以接触接合层2的顶表面以及组件121、122或123的顶表面、底表面和侧表面，以包封电子组件121、122或123。在一些实例中，电介质130可以被称为包封件。
图3D示出了处于后期制造阶段的半导体装置100的横截面视图。在图3D所示的实例中，载体1可以与图3C所示的组合件分离。在一些实例中，可以通过向图3C所示的组合件施加热或UV光降低接合层2的接合强度来去除载体1。在一些实例中，可以通过施加物理力拉动接合层2和载体1来去除接合层2和载体1。在一些实例中，在去除接合层2和载体1之后，可以暴露包封件130以及互连件125的较低部分。
图3E示出了处于后期制造阶段的半导体装置100的横截面视图。在图3E所示的实例中，可以在载体3上形成或提供接合层4。在一些实例中，用于形成接合层4和载体3的制造工艺以及所述接合层和所述载体的配置可以与参考图1和图2A到2D讨论的接合层2和载体1的制造工艺和配置相同或类似。在一些实例中，在接合层4耦接到载体3之后，衬底110可以耦接到接合层4。
在一些实例中，在衬底110耦接到接合层4之后，图3D所示的组合件可以耦接到衬底110。在一些实例中，包封件130的底表面以及互连件125的较低部分可以耦接到衬底110的顶表面110c。
图3F示出了处于后期制造阶段的半导体装置100的横截面视图。在图3F所示的实例中，载体3可以与图3E所示的组合件分离。在一些实例中，可以通过向图3E所示的组合件施加热或UV光降低接合层4的接合强度来去除载体3。在一些实例中，可以通过施加物理力从衬底110拉出接合层4和载体3来去除接合层4和载体3。在其它实例中，可以使用研磨工艺来去除接合层4和载体3。在一些实例中，在去除接合层4和载体3之后，外部互连件150可以耦接到衬底110的底表面110d。
图4示出了示例电子组合件10的横截面视图。在图4所示的实例中，电子组合件10可以包括基础结构11、电互连件12(如接合线或线夹(clip))以及半导体装置100和200。在一些实例中，基础结构11可以包括介电结构11a和导电结构11b。在一些实例中，电子组合件10可以包括彼此电耦接的半导体装置100和半导体装置200，其中半导体装置100和半导体装置200中的每一个可以包括例如如图1所示出并且相对于所述图描述的半导体装置100。在一些实例中，电子组合件10可以包括包含顶表面的基础结构11，其中半导体装置100和200可以处于基础结构11的顶表面之上。在一些实例中，半导体装置100和200可以通过耦接到半导体装置的衬底接片111的电互连件，例如通过如图4所示的电互连件12、通过如图6所示的电互连件22或通过如图8所示的电互连件32彼此电耦接，并且所公开的主题的范围在这些方面不受限制。
在一些实例中，半导体装置200可以包括衬底210、电子组件221、222或223、电互连件225、包封件230、外部互连件250和覆盖层260。在一些实例中，衬底210可以包括顶表面210c、底表面210d、介电结构210a、导电结构210b和衬底接片211。在一些实例中，电互连件225可以被称为接合线，并且电互连件225可以包括导电材料，例如合金、金、银、铜或钯涂覆的铜(PCC)。在一些实例中，组件223的管芯端子可以使用电互连件225电耦接到衬底210的导电结构210b。
在一些实例中，衬底210、包封件230和外部互连件250可以被称为半导体封装并且可以保护电子组件221、222或223免于外部元件或环境暴露。半导体封装可以提供外部组件与电子组件221、222或223之间的电耦接。在一些实例中，用于形成半导体装置200的制造工艺以及所述半导体装置的配置可以与参考图1、图2A到2D以及图3A到3F在本公开中描述的用于形成半导体装置100的制造工艺以及所述半导体装置的配置相同或类似。在一些实例中，可以通过将衬底接片211耦接到衬底接片111来将半导体装置200耦接到半导体装置100。
在一些实例中，半导体装置200可以包括包封件230的外表面上的覆盖层260。在一些实例中，覆盖层260可以被称为适形屏蔽件。在一些实例中，包封件可以包括四个侧表面，并且覆盖层260可以包括导电材料并且可以位于包封件230的顶表面和四个侧表面上。在一些实例中，层260可以为电子组件221、222或223提供电磁干扰(EMI)屏蔽。在一些实例中，覆盖层260可以通过衬底210的导电结构211b电耦接到接地以提供EMI屏蔽。
图5A到5D示出了用于制造电子组合件10的示例方法的横截面视图。图5A示出了处于早期制造阶段的电子组合件10的横截面视图。
在图5A所示的实例中，基础结构11可以包括介电结构11a和导电结构11b。在一些实例中，基础结构11可以包括或被称为预成型衬底、RDL衬底、印刷电路板、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。
在一些实例中，介电结构11a可以具有平坦顶表面和底表面。介电结构11a的顶表面和底表面可以与基础结构11的顶表面和底表面平行。在一些实例中，介电结构11a可以被称为介电层或核心层。介电结构11a可以包含一个或多个介电层。在一些实例中，介电结构11a可以包括环氧树脂、酚树脂、玻璃环氧树脂、聚酰亚胺、聚酯、环氧模制化合物、陶瓷、双马来酰亚胺三嗪(BT)或FR4。
导电结构11b可以耦接到介电结构11a。在一些实例中，导电结构11b可以被称为导体、导电材料、导电通孔、电路图案、迹线或布线图案。
图5B示出了处于后期制造阶段的电子组合件10的横截面视图。在图5B所示的实例中，半导体装置100可以处于基础结构11的顶表面的一部分上。半导体装置100可以电耦接到导电结构11b。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件150附接到基础结构11或将互连件150电耦接到基础结构11的导电结构11b。
图5C示出了处于后期制造阶段的电子组合件10的横截面视图。在图5C所示的实例中，半导体装置200可以处于基础结构11的顶表面的一部分上。在一些实例中，半导体装置200的衬底接片211可以与半导体装置100的衬底接片111相邻。在一些实例中，衬底接片111可以接触衬底接片211。在其它实例中，衬底接片111可以与衬底接片211间隔开。
在一些实例中，基础结构11的导电结构11b可以通过导体、导电材料、导电通孔、衬底焊盘、导电焊盘、衬底垫、布线垫、连接垫、微型垫或凸点下金属(UBM)电耦接到半导体装置100或200。在一些实例中，导电结构11b可以包括铜、铝、铁、镍、金、银、钯或锡。
图5D示出了处于后期制造阶段的电子组合件10的横截面视图。在图5D所示的实例中，电互连件12可以耦接到衬底接片111和211。在一些实例中，互连件12可以包括导电接合线或线夹或多个接合线和线夹。在一些实例中，互连件12可以包括导电材料，例如合金、金、银、铜或钯涂覆的铜(PCC)。在一些实例中，衬底110的导电结构110b可以通过互连件12电耦接到衬底210的导电结构210b。在一些实例中，互连件12可以提供半导体装置100与200之间的导电路径。与其它电子组合件相比，由于相对较短的电路径，电子组合件10的互连件12可以提供相对较低的热阻和相对较高的性能。
图6示出了电子组合件20的横截面视图。在图6所示的实例中，电子组合件20可以包括电互连件22以及半导体装置100和300。
在一些实例中，半导体装置300可以包括衬底310、电子组件321、互连件325、包封件330和外部互连件350。衬底310可以包括介电结构310a、导电结构310b和衬底接片311。在图6所示的实例中，半导体装置300可以相对于半导体装置100倒置，以允许半导体装置300的衬底接片311处于半导体装置100的衬底接片111之上，以便于半导体装置100和300的耦接。在一些实例中，本文所描述的包含电互连件12、电互连件22或互连件32的互连件中的任何互连件可以包括互连衬底，所述互连件衬底包括导电材料和用于形成衬底的任何适合的衬底材料、介电材料、刚性材料或柔性材料。在一些实例中，本文所描述的互连件中的任何互连件可以包括引线框架。在一些实例中，当半导体装置300如图6的配置所示相对于半导体装置100倒置时，外部互连件350可以处于与包封件130的顶表面相同的高度或者可以在所述顶表面上方延伸或以其它方式高于所述顶表面。同样地，在此类倒置配置中，外部互连件150可以处于与包封件330的顶表面相同的高度或者在所述顶表面下方延伸或以其它方式低于所述顶表面。
在一些实例中，衬底310、包封件330和外部互连件350可以被称为半导体封装并且可以保护电子组件321免于外部元件或环境暴露。半导体封装可以提供外部组件与电子组件321之间的电耦接。在一些实例中，衬底310可以包括或被称为预成型衬底、RDL衬底、印刷电路板、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。在一些实例中，用于形成半导体装置300的制造工艺以及所述半导体装置的配置可以与参考图1、图2A到2D以及图3A到3F在本公开中描述的用于形成半导体装置100的制造工艺以及所述半导体装置的配置相同或类似。在一些实例中，可以通过将衬底接片311耦接到衬底接片111来将半导体装置300耦接到半导体装置100。
图7A和7B示出了用于制造电子组合件20的示例方法的横截面视图。图7A示出了处于早期制造阶段的电子组合件20的横截面视图。
在图7A所示的实例中，互连件22可以位于半导体装置100的衬底接片111上。在一些实例中，互连件22可以包括导电材料，例如焊料或铜柱。在一些实例中，互连件22可以电耦接到导电结构110b。在一些实例中，互连件22可以包括锡(Sn)、银(Ag)、铅(Pb)、铜(Cu)、金、铝、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi或Sn-Ag-Cu。在一些实例中，互连件22可以通过焊球滴落工艺、丝网印刷或电镀来形成或提供。在一些实例中，互连件22可以包括铜柱，所述铜柱包括铜柱的端部区域上的焊料盖。
图7B示出了处于后期制造阶段的电子组合件20的横截面视图。在图7B所示的实例中，半导体装置300可以耦接到半导体装置100。在一些实例中，半导体装置300的衬底接片311可以耦接到互连件22，并且衬底接片111和311可以通过互连件22彼此电耦接并机械耦接。在一些实例中，衬底接片311处于衬底接片111之上，并且衬底接片111和311可以提供半导体装置100与300之间的电路径。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将接片311附接到互连件22或将装置100的组件电耦接到装置300的组件。与其它电子组合件相比，由于相对较短的电路径，电子组合件20的互连件22可以提供相对较低的热阻和相对较高的性能。
图8示出了示例电子组合件30的横截面视图。在图8所示的实例中，电子组合件30可以包括互连件32以及半导体装置100和300。
图9A到9C示出了用于制造电子组合件30的示例方法的横截面视图。图9A示出了处于早期制造阶段的电子组合件30的横截面视图。
在图9A所示的实例中，互连件32可以处于半导体装置100的衬底接片111上。在一些实例中，互连件32可以包括或被称为预成型衬底、RDL衬底、印刷电路板、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。在一些实例中，互连件32可以具有顶表面和底表面并且可以在其底表面上包括导电图案。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件32附接到半导体装置100的衬底接片111或将装置100的组件电耦接到互连件32的导电图案。
图9B示出了处于后期制造阶段的电子组合件30的横截面视图。在图9B所示的实例中，半导体装置300可以耦接到半导体装置100。在一些实例中，在互连件32耦接到衬底接片111之后，半导体装置300的衬底接片311可以耦接到互连件32的顶表面，并且衬底接片111和311可以通过互连件32彼此电耦接并机械耦接。在一些实例中，接片111接触互连件32的第一部分并且接片311接触互连件32的第二部分。在一些实例中，接片111接触互连件32的底表面并且接片311接触互连件32的顶表面。在一些实例中，互连件32以及衬底接片111和311可以提供半导体装置100与300之间的电路径。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将接片311附接到互连件32或将装置100的组件电耦接到装置300的组件。与其它电子组合件相比，由于相对较短的电路径，电子组合件30的互连件32可以提供相对较低的热阻和相对较高的性能。
图9C示出了处于后期制造阶段的电子组合件30的横截面视图。在图9C所示的实例中，除了互连件32被示出为弯折使得半导体装置300和半导体装置可以呈折叠布置之外，半导体装置300可以如图9B所示耦接到半导体装置100。在此类折叠布置中，互连件32的柔性可以允许将半导体装置300折叠在半导体装置100的顶侧之上或反之亦然并且可以允许半导体装置300和半导体装置100以堆叠式封装布置提供。在图9C所示的实例中，半导体装置300被示为相对于半导体装置100的朝向倒置。在其它实例中，半导体装置300相对于半导体装置100的朝向不倒置，并且所公开主题的范围在此方面不受限制。
图10示出了电子组合件40的横截面视图。在图10所示的实例中，电子组合件40可以包括电互连件32以及半导体装置100和400。
在一些实例中，半导体装置400可以包括衬底410、电子组件421、422或423、互连件425、包封件430和外部互连件450。衬底410可以包括介电结构410a、导电结构410b和衬底接片411。
在一些实例中，衬底410、包封件430和外部互连件450可以被称为半导体封装并且可以保护电子组件421、422或423免于外部元件或环境暴露。半导体封装可以提供外部组件与电子组件421、422或423之间的电耦接。在一些实例中，衬底410可以包括或被称为预成型衬底、RDL衬底、印刷电路板、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。在一些实例中，用于形成半导体装置400的制造工艺以及所述半导体装置的配置可以与参考图1、图2A到2D以及图3A到3F在本公开中描述的用于形成半导体装置100的制造工艺以及所述半导体装置的配置相同或类似。在一些实例中，可以通过将衬底接片411耦接到衬底接片111来将半导体装置400耦接到半导体装置100。
图11A和11B示出了用于制造电子组合件40的示例方法的横截面视图。图11A示出了处于早期制造阶段的电子组合件40的横截面视图。
在图11A所示的实例中，半导体装置400的衬底接片411可以与半导体装置100的衬底接片111相邻。在一些实例中，衬底接片111可以与衬底接片411间隔开。在其它实例中，衬底接片111可以接触衬底接片411。
图11B示出了处于后期制造阶段的电子组合件40的横截面视图。在图11B所示的实例中，互连件32可以耦接到衬底接片111和411。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件32附接到衬底接片111和411、将装置100的组件电耦接到互连件32的导电图案、将装置400的组件电耦接到互连件32的导电图案或者将装置100的组件电耦接到装置400的组件。
在一些实例中，半导体装置400可以耦接到半导体装置100。在一些实例中，衬底接片111和411可以耦接到互连件32的底表面，并且衬底接片111和411可以通过互连件32彼此电耦接并机械耦接。在一些实例中，衬底接片111接触互连件32的底表面的第一部分并且衬底接片411接触互连件32的底表面的第二部分。在一些实例中，互连件32以及衬底接片111和411可以提供半导体装置100与400之间的电路径。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件32附接到接片111和411或将装置100的组件电耦接到装置400的组件。与其它电子组合件相比，由于相对较短的电路径，电子组合件40的互连件32可以提供相对较低的热阻和相对较高的性能。
图12示出了示例电子组合件50的横截面视图。在图12所示的实例中，电子组合件50可以包括电互连件22、支撑结构51、中间结构52、支撑结构53以及半导体装置100和300。在一些实例中，基础结构可以包括支撑结构51、支撑结构53以及支撑结构51与支撑结构53之间的中间结构52。半导体装置100可以耦接到支撑结构51的顶表面，并且半导体装置300可以耦接到支撑结构53的顶表面。半导体装置300连同支撑结构53一起可以相对于半导体装置100和支撑结构51倒置，其中半导体装置300的衬底接片311处于半导体装置100的衬底接片111之上，以便于通过互连件22耦接衬底接片。
在一些实例中，支撑结构51和53可以分别包括介电结构51a和53a。支撑结构51和53可以分别包括导电结构51b和53b。中间结构42可以包括介电结构和导电结构52a。在一些实例中，中间结构52可以处于支撑结构51与支撑结构53之间。
图13A到13D示出了用于制造电子组合件50的示例方法的横截面视图。图13A示出了处于早期制造阶段的电子组合件50的横截面视图。
在图13A所示的实例中，支撑结构51可以包括介电结构51a和导电结构51b。在一些实例中，支撑结构51可以包括或被称为液晶聚合物、预成型衬底、RDL衬底、印刷电路板、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。
在一些实例中，介电结构51a可以具有平坦顶表面和底表面。介电结构51a的顶表面和底表面可以与支撑结构51的顶表面和底表面平行。在一些实例中，介电结构51a可以被称为介电层或核心层。介电结构51a可以包含一个或多个介电层。在一些实例中，介电结构51a可以包括环氧树脂、酚树脂、玻璃环氧树脂、聚酰亚胺、聚酯、环氧模制化合物、陶瓷、双马来酰亚胺三嗪(BT)或FR4。导电结构51b可以耦接到介电结构51a。在一些实例中，导电结构51b可以被称为导体、导电材料、导电通孔、电路图案、迹线或布线图案。
在图13A所示的实例中，半导体装置100可以处于支撑结构51的顶表面的一部分上。半导体装置100可以电耦接到支撑结构51的导电结构51b。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件150附接到支撑结构51或将互连件150电耦接到基础结构51的导电结构51b。
图13B示出了处于后期制造阶段的电子组合件50的横截面视图。在图13B所示的实例中，半导体装置300可以耦接到半导体装置100。在一些实例中，在互连件22形成于或提供于接片111上之后，半导体装置300的衬底接片311可以耦接到互连件22，并且衬底接片111和311可以通过互连件22彼此电耦接并机械耦接。在一些实例中，衬底接片311处于衬底接片111之上，并且互连件22以及衬底接片111和311可以提供半导体装置100与300之间的电路径。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将接片311附接到互连件22或将装置100的组件电耦接到装置300的组件。与其它电子组合件相比，由于相对较短的电路径，电子组合件50的互连件22可以提供相对较低的热阻和相对较高的性能。
图13C示出了处于后期制造阶段的电子组合件50的横截面视图。在图13C所示的实例中，中间结构52可以耦接到支撑结构51的顶表面。在一些实例中，中间结构52可以是单个一体的矩形结构。在其它实例中，中间结构52可以包括多个间隔开的组件。
在一些实例中，中间结构52可以包括或被称为液晶聚合物、预成型衬底、RDL衬底、印刷电路板、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。在一些实例中，中间结构52可以具有顶表面和底表面并且可以在其顶表面和底表面上包括导电图案。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将中间结构52附接到支撑结构51、将装置100和300的组件电耦接到中间结构52的导电图案或者将导电结构52a电耦接到导电结构51b。在其它实例中，中间结构52可以使用粘合剂耦接到支撑结构51。
图13D示出了处于后期制造阶段的电子组合件50的横截面视图。在图13D所示的实例中，支撑结构53可以处于中间结构52、装置100或装置300上。支撑结构53可以包括介电结构53a和导电结构53b。在一些实例中，支撑结构53可以包括或被称为液晶聚合物、预成型衬底、RDL衬底、印刷电路板、腔衬底、印刷布线板、多层衬底、贯穿孔衬底、刚性衬底、柔性衬底、玻璃环氧树脂衬底、聚酰亚胺衬底、聚酯衬底、模制塑料衬底、陶瓷衬底、蚀刻箔工艺衬底、加成工艺衬底、堆积衬底或模制引线框架。
在一些实例中，介电结构53a可以具有平坦顶表面和底表面。介电结构53a的顶表面和底表面可以与支撑结构53的顶表面和底表面平行。在一些实例中，介电结构53a可以被称为介电层或核心层。介电结构53a可以包含一个或多个介电层。在一些实例中，介电结构53a可以包括环氧树脂、酚树脂、玻璃环氧树脂、聚酰亚胺、聚酯、环氧模制化合物、陶瓷、双马来酰亚胺三嗪(BT)或FR4。导电结构53b可以耦接到介电结构53a。在一些实例中，导电结构53b可以被称为导体、导电材料、导电通孔、电路图案、迹线或布线图案。
在一些实例中，半导体装置300可以电耦接到支撑结构53的导电结构53b。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件350附接到支撑结构53、将互连件350电耦接到基础结构53的导电结构53b或者将导电结构52a电耦接到导电结构53b。在其它实例中，中间结构52可以使用粘合剂耦接到支撑结构53。
图14示出了示例电子组合件60的横截面视图。在图14所示的实例中，电子组合件60可以包括互连件32、支撑结构51、中间结构52、支撑结构53以及半导体装置100和300。
图15A到15E示出了用于制造电子组合件60的示例方法的横截面视图。图15A示出了处于早期制造阶段的电子组合件60的横截面视图。
在图15A所示的实例中，半导体装置100可以处于支撑结构51的顶表面的一部分上。半导体装置100可以电耦接到导电结构51b。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件150附接到支撑结构51或将互连件150电耦接到基础结构51的导电结构51b。
图15B示出了处于后期制造阶段的电子组合件60的横截面视图。在图15B所示的实例中，互连件32可以处于半导体装置100的衬底接片111上。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件32附接到半导体装置100的衬底接片111或将装置100的组件电耦接到互连件32的导电图案。
图15C示出了处于后期制造阶段的电子组合件30的横截面视图。在图15C所示的实例中，半导体装置300可以耦接到半导体装置100。在一些实例中，半导体装置300的衬底接片311可以耦接到互连件32的顶表面，并且衬底接片111和311可以通过互连件32彼此电耦接并机械耦接。在一些实例中，衬底接片111接触互连件32的第一部分并且衬底接片311接触互连件32的第二部分。在一些实例中，衬底接片111接触互连件32的底表面并且衬底接片311接触互连件32的顶表面。在一些实例中，互连件32以及衬底接片111和311可以提供半导体装置100与300之间的电路径。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将接片311附接到互连件32或将装置100的组件电耦接到装置300的组件。与其它电子组合件相比，由于相对较短的电路径，电子组合件60的互连件32可以提供相对较低的热阻和相对较高的性能。
图15D示出了处于后期制造阶段的电子组合件50的横截面视图。在图15D所示的实例中，中间结构52可以耦接到支撑结构51的顶表面。在一些实例中，中间结构52可以是单个一体的矩形结构。在其它实例中，中间结构52可以包括多个间隔开的组件。
图15E示出了处于后期制造阶段的电子组合件60的横截面视图。在图15E所示的实例中，支撑结构53可以处于中间结构52、装置100或装置300上。
在一些实例中，半导体装置300可以电耦接到支撑结构53的导电结构53b。在一些实例中，可以使用质量回流工艺、热压缩工艺或激光辅助接合工艺来将互连件350附接到支撑结构53、将互连件350电耦接到支撑结构53的导电结构53b或者将导电结构52a电耦接到导电结构53b。在其它实例中，中间结构52可以使用粘合剂耦接到支撑结构53。
本公开包含对某些实例的引用。然而，本领域的技术人员应理解的是，在不脱离本公开的范围的情况下，可以作出各种改变并且可以取代等同物。另外，在不脱离本公开的范围的情况下，可以对所公开的实例进行修改。因此，本公开旨在不限于所公开的实例，而是本公开将包含落入所附权利要求的范围内的所有实例。

Claims (20)

1.一种电子组合件，其包括：
第一半导体装置和第二半导体装置，其中所述第一半导体装置和所述第二半导体装置中的每一个包括：
衬底，所述衬底包括顶表面和导电结构；
电子组件，所述电子组件处于所述衬底的所述顶表面之上；
介电材料，所述介电材料处于所述衬底的所述顶表面之上并且接触所述电子组件的一侧；
衬底接片，所述衬底接片处于衬底的一端处并且未被所述介电材料覆盖，其中所述衬底的所述导电结构在所述衬底接片处暴露；以及
互连件，所述互连件电耦接到所述第一半导体装置的所述衬底接片处的所述导电结构和所述第二半导体装置的所述衬底接片处的所述导电结构。
2.根据权利要求1所述的电子组合件，其进一步包括基础结构，所述基础结构包括顶表面，其中所述第一半导体装置处于所述基础结构的所述顶表面之上，并且所述第二半导体装置处于所述基础结构的所述顶表面之上。
3.根据权利要求1所述的电子组合件，其中所述互连件包括接合线。
4.根据权利要求1所述的电子组合件，其中所述互连件包括线夹。
5.根据权利要求1所述的电子组合件，其中所述第二半导体装置相对于所述第一半导体装置倒置，并且所述第二半导体装置的所述衬底接片处于所述第一半导体装置的所述衬底接片之上。
6.根据权利要求5所述的电子组合件，其中所述互连件包括焊料。
7.根据权利要求5所述的电子组合件，其中所述互连件包括铜柱。
8.根据权利要求1所述的电子组合件，其中所述互连件包括互连衬底。
9.根据权利要求1所述的电子组合件，其中所述互连件包括柔性衬底。
10.根据权利要求1所述的电子组合件，其中所述互连件包括引线框架。
11.根据权利要求2所述的电子组合件，其中：
所述基础结构包括第一支撑结构、第二支撑结构和处于所述第一支撑结构与所述第二支撑结构之间的中间结构，
所述第一半导体装置耦接到所述第一支撑结构的顶表面并且所述第二半导体装置耦接到所述第二支撑结构的顶表面，并且
所述第二半导体装置相对于所述第一半导体装置倒置，其中所述第二半导体装置的所述衬底接片处于所述第二半导体装置的所述衬底接片之上。
12.一种方法，其包括：
在第一衬底的顶表面之上提供第一电子组件，其中所述第一衬底包括耦接到所述第一电子组件的第一导电结构，所述第一衬底在所述顶表面上具有第一衬底接片，并且所述第一导电结构在所述第一衬底接片处暴露；以及
在所述第一衬底的所述顶表面之上提供第一介电结构，其中所述第一介电结构接触所述第一电子组件的一侧并且所述第一衬底接片未被所述第一介电结构覆盖。
13.根据权利要求12所述的方法，其进一步包括在所述第一衬底的所述顶表面之上提供所述第一电子组件之前，在载体上提供所述第一衬底，并且在所述第一衬底的所述顶表面上提供所述第一介电结构之后，去除所述载体。
14.根据权利要求12所述的方法，其进一步包括：
在第二衬底的顶表面之上提供第二电子组件，其中所述第二衬底包括耦接到所述第二电子组件的第二导电结构，所述第二衬底在所述顶表面上具有第二衬底接片，并且所述第二导电结构在所述第二衬底接片处暴露；
在所述第二衬底的所述顶表面之上提供第二介电结构，其中所述第二介电结构接触所述第二电子组件的一侧并且所述第二衬底接片未被所述第二介电结构覆盖；以及
将所述第一衬底的所述第一衬底接片耦接到所述第二衬底的所述第二衬底接片。
15.一种方法，其包括：
提供第一半导体装置和第二半导体装置，其中所述提供所述第一半导体装置和所述第二半导体装置中的每一个包括：
提供包括顶表面和导电结构的衬底；
在所述衬底的所述顶表面之上提供电子组件；
在衬底的一端处提供衬底接片，其中所述衬底的所述导电结构在所述衬底接片处暴露；以及
提供互连件，所述互连件电耦接到所述第一半导体装置的所述衬底接片处的所述导电结构和所述第二半导体装置的所述衬底接片处的所述导电结构。
16.根据权利要求15所述的方法，其中所述互连件包括接合线。
17.根据权利要求15所述的方法，其中所述互连件包括线夹。
18.根据权利要求15所述的方法，其中所述互连件包括焊料。
19.根据权利要求15所述的方法，其中所述互连件包括铜柱。
20.根据权利要求15所述的方法，其进一步包括提供介电材料，所述介电材料在所述衬底的所述顶表面之上并且接触所述电子组件的一侧，其中所述介电材料不覆盖所述衬底接片。
CN202011486758.2A 2020-01-29 2020-12-16 半导体装置和制造半导体装置的方法 Pending CN113192922A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/775,648 2020-01-29
US16/775,648 US11342268B2 (en) 2020-01-29 2020-01-29 Semiconductor devices and methods of manufacturing semiconductor devices

Publications (1)

Publication Number Publication Date
CN113192922A true CN113192922A (zh) 2021-07-30

Family

ID=76970279

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011486758.2A Pending CN113192922A (zh) 2020-01-29 2020-12-16 半导体装置和制造半导体装置的方法

Country Status (3)

Country Link
US (2) US11342268B2 (zh)
CN (1) CN113192922A (zh)
TW (1) TW202129897A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220066036A1 (en) * 2020-08-25 2022-03-03 Lumentum Operations Llc Package for a time of flight device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6169328B1 (en) * 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US9633950B1 (en) * 2016-02-10 2017-04-25 Qualcomm Incorporated Integrated device comprising flexible connector between integrated circuit (IC) packages
US9633977B1 (en) * 2016-02-10 2017-04-25 Qualcomm Incorporated Integrated device comprising flexible connector between integrated circuit (IC) packages
US10861773B2 (en) * 2017-08-30 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11062998B2 (en) * 2019-08-22 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Also Published As

Publication number Publication date
US11342268B2 (en) 2022-05-24
US20210233848A1 (en) 2021-07-29
US20220285277A1 (en) 2022-09-08
TW202129897A (zh) 2021-08-01

Similar Documents

Publication Publication Date Title
US11521918B2 (en) Semiconductor device having component mounted on connection bar and lead on top side of lead frame and method of manufacturing semiconductor device thereof
US11749654B2 (en) Semiconductor device and method of manufacturing semiconductor device
US11004801B2 (en) Semiconductor devices and methods of manufacturing semiconductor devices
CN111834304A (zh) 半导体装置及制造半导体装置的方法
CN113690197A (zh) 半导体装置及制造半导体装置的方法
US20220045037A1 (en) Semiconductor device and method of manufacturing a semiconductor device
US20240047852A1 (en) Semiconductor devices and methods of manufacturing semiconductor devices
US20220285277A1 (en) Semiconductor devices and methods of manufacturing semiconductor devices
TWI760725B (zh) 半導體裝置和製造半導體裝置的方法
US20240113090A1 (en) Electronic devices and methods of manufacturing electronic devices
US20240145369A1 (en) Electronic devices and methods of manufacturing electronic devices
US11562936B2 (en) Electrionic devices with interposer and redistribution layer
US20240079282A1 (en) Electronic devices and method of manufacturing an electronic devices
US20240006337A1 (en) Electronic devices and methods of manufacturing electronic devices
TW202416469A (zh) 電子裝置及製造電子裝置的方法
CN112216674A (zh) 半导体装置及制造半导体装置的方法
TW202414714A (zh) 堆疊式混合基板的半導體裝置及方法
CN117727719A (zh) 半导体装置和堆叠混合基底的方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination