CN111834304A - 半导体装置及制造半导体装置的方法 - Google Patents

半导体装置及制造半导体装置的方法 Download PDF

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Publication number
CN111834304A
CN111834304A CN202010297973.1A CN202010297973A CN111834304A CN 111834304 A CN111834304 A CN 111834304A CN 202010297973 A CN202010297973 A CN 202010297973A CN 111834304 A CN111834304 A CN 111834304A
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conductive
redistribution layer
layer substrate
substrate
protective material
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CN202010297973.1A
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English (en)
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金泰基
新及補
孙山南
杜旺朱
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Anrely Technology Singapore Holdings Pte Ltd
Amkor Technology Singapore Holding Pte Ltd
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Anrely Technology Singapore Holdings Pte Ltd
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Publication of CN111834304A publication Critical patent/CN111834304A/zh
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    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

在一个实例中，一种半导体装置包括：重新分布层(RDL)衬底，所述RDL衬底具有顶表面和底表面，其中所述RDL衬底包括不含填料的介电材料；电子装置，所述电子装置位于所述RDL衬底的所述顶表面上；电互连件，所述电互连件位于所述RDL衬底的所述底表面上并且电耦接到所述电子装置；第一保护材料，所述第一保护材料接触所述电子装置的侧表面和所述RDL衬底的所述顶表面；以及第二保护材料，所述第二保护材料接触所述电互连件的侧表面和所述RDL衬底的所述底表面。本文还公开了其它实例和相关方法。

Description

半导体装置及制造半导体装置的方法
技术领域
本公开总体上涉及电子装置，并且更具体地涉及半导体装置和用于制造半导体装置的方法。
背景技术
现有半导体封装和用于形成半导体封装的方法存在不足之处，例如造成成本过多、可靠性降低、性能相对较低或封装尺寸太大。对于本领域的技术人员来说，通过将常规和传统方法与本公开进行比较并且参考附图，此类方法的另外的局限性和缺点将变得明显。
发明内容
本揭露的各种态样提供一种半导体装置，其包括：重新分布层衬底，所述重新分布层衬底具有顶表面和底表面，其中所述重新分布层衬底包括不含填料的介电材料；电子装置，所述电子装置位于所述重新分布层衬底的所述顶表面上；电互连件，所述电互连件位于所述重新分布层衬底的所述底表面上并且电耦接到所述电子装置；第一保护材料，所述第一保护材料接触所述电子装置的侧表面和所述重新分布层衬底的所述顶表面；以及第二保护材料，所述第二保护材料接触所述电互连件的侧表面和所述重新分布层衬底的所述底表面。在所述半导体装置中，所述电互连件包括在所述重新分布层衬底的所述底表面上的导电桩、所述导电桩上的导电柱以及所述导电柱上的互连尖端。在所述半导体装置中，所述电互连件进一步包括位于所述导电桩与所述导电柱之间的晶种层。在所述半导体装置中，所述电互连件包括在所述重新分布层衬底的所述底表面上的凸点下金属。在所述半导体装置中，所述电互连件包括在所述重新分布层衬底的所述底表面上的导电桩和所述导电桩上的焊球。在所述半导体装置中，所述重新分布层衬底包括导电层和介电层。所述半导体装置进一步包括另外的电互连件，所述另外的电互连件位于所述重新分布层衬底的所述顶表面上，所述另外的电互连件用于通过所述导电层将所述电子装置耦接到所述重新分布层衬底的所述底表面上的所述电互连件。在所述半导体装置中，所述第一保护材料和所述第二保护材料包括具有相同热膨胀系数的相同材料。在所述半导体装置中，所述第一保护材料和所述第二保护材料包括具有相同或类似热膨胀系数的不同材料。在所述半导体装置中，所述第一保护材料具有第一热膨胀系数和第一厚度，并且所述第二保护材料具有第二热膨胀系数和第二厚度，使得所述第一保护材料与所述重新分布层衬底之间的翘曲抵消所述第二保护材料与所述重新分布层衬底之间的翘曲。
本揭露的各种态样提供一种用于制造半导体装置的方法，所述方法包括：形成具有导电桩的基底结构；在所述基底结构上形成重新分布层衬底；在所述重新分布层衬底的顶表面上放置电子装置；以及形成接触所述电子装置的侧表面和所述重新分布层衬底的所述顶表面的保护材料。在所述方法中，所述导电桩是使用镀覆操作形成的，并且所述基底结构是在所述镀覆操作之后使用模制操作形成的。在所述方法中，所述重新分布层衬底包括不含填料的介电材料，并且所述导电桩是使用镀覆操作形成的，并且所述方法进一步包括使用第二镀覆操作在所述导电桩上形成导电柱并且使用第三镀覆操作在所述导电桩上形成互连尖端。在所述方法中，形成所述重新分布层衬底包括：在所述基底结构上形成第一介电层；在所述介电层中形成开口以暴露所述导电桩；以及在所述介电层和所述导电桩上形成导电层。在所述方法中，所述基底结构是使用第一模制操作在第一载体上形成的，并且所述保护材料是使用第二模制操作形成的，并且所述方法进一步包括：在所述保护材料上附接第二载体；去除所述第一载体；以及在所述去除所述第一载体之后拆下所述第二载体。
本揭露的各种态样提供一种用于制造半导体装置的方法，所述方法包括在第一载体上形成重新分布层衬底，所述重新分布层衬底具有顶表面和底表面；在所述重新分布层衬底的所述顶表面上放置电子装置；使用第一模制操作形成第一保护材料，其中所述第一保护材料接触所述电子装置的侧表面和所述重新分布层衬底的所述顶表面；将第二载体附接到所述第一保护材料；从所述重新分布层衬底去除所述第一载体；使用第一镀覆操作在所述重新分布层衬底的所述底表面上形成导电桩；以及使用第二模制操作形成第二保护材料，其中所述第二保护材料接触所述导电桩的侧表面和所述重新分布层衬底的所述底表面。所述方法进一步包括使用第二镀覆操作在所述导电桩上形成导电柱并且使用第三镀覆操作在所述导电桩上形成互连尖端。所述方法进一步包括在所述导电桩上形成焊球。所述方法进一步包括在所述第三镀覆操作之后去除所述第二载体。在所述方法中，所述第一载体是使用研磨或蚀刻操作去除的。
附图说明
图1示出了示例半导体装置的横截面视图。
图2A到2L示出了用于制造示例半导体装置的示例方法的横截面视图。
图3示出了另一个示例半导体装置的横截面视图。
图4A到4K示出了用于制造另一个示例半导体装置的示例方法的横截面视图。
具体实施方式
以下讨论提供了半导体装置和制造半导体装置的方法的各种实例。此类实例是非限制性的，并且所附权利要求的范围不应限于所公开的特定实例。在以下讨论中，术语“实例”和“例如”是非限制性的。
附图展示了一般的构造方式，并且可以省略公知特征和技术的描述和细节，以避免不必要地模糊本公开。另外，附图中的元件不一定按比例绘制。例如，图中的元件中的一些元件的尺寸可能相对于其它元件而被放大以有助于改善对本公开中所讨论的实例的理解。不同附图中的相同附图标记表示相同的元件。
术语“或”和“和/或”包含由“或”或“和/或”连接的列表中的任何单个项目或项目的任何组合。如本公开中所使用的，除非上下文明确指示不包含复数形式，否则单数形式旨在同样包含复数形式。
术语“包括(comprises)”、“包括(comprising)”、“包含(includes)”和/或“包含(including)”是“开放式”术语并且指定存在所陈述的特征，但不排除存在或增加一个或多个其它特征。
在本文中可以使用术语“第一”、“第二”等来描述各种元件，并且这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件进行区分。因此，例如，在不背离本公开的教导的情况下，本公开中所讨论的第一元件可以被称为第二元件。
除非另外指明，否则术语“耦接”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。例如，如果元件A耦接到元件B，则元件A可以直接接触元件B或通过中间元件C间接连接到元件B。类似地，术语“之上”或“上”可以用于描述彼此直接接触的两个元件或描述通过一个或多个其它元件间接连接的两个元件。
在一个实例中，一种半导体装置包括：重新分布层(RDL)衬底，所述RDL衬底具有顶表面和底表面，其中所述RDL衬底包括不含填料的介电材料；电子装置，所述电子装置位于所述RDL衬底的所述顶表面上；电互连件，所述电互连件位于所述RDL衬底的所述底表面上并且电耦接到所述电子装置；第一保护材料，所述第一保护材料接触所述电子装置的侧表面和所述RDL衬底的所述顶表面；以及第二保护材料，所述第二保护材料接触所述电互连件的侧表面和所述RDL衬底的所述底表面。
在另一个实例中，一种用于制造半导体装置的方法包括：形成具有导电桩的基底结构；在所述基底结构上形成重新分布层(RDL)衬底；在所述RDL衬底的顶表面上放置电子装置；以及形成接触所述电子装置的侧表面和所述RDL衬底的所述顶表面的保护材料。
在另外的实例中，一种用于制造半导体装置的方法包括：在第一载体上形成重新分布层(RDL)衬底，所述RDL衬底具有顶表面和底表面；在所述RDL衬底的所述顶表面上放置电子装置；使用第一模制操作形成第一保护材料，其中所述第一保护材料接触所述电子装置的侧表面和所述RDL衬底的所述顶表面；将第二载体附接到所述第一保护材料；从所述RDL衬底去除所述第一载体；使用第一镀覆操作在所述RDL衬底的所述底表面上形成导电桩；以及使用第二模制操作形成第二保护材料，其中所述第二保护材料接触所述导电桩的侧表面和所述RDL衬底的所述底表面。
本公开中包含其它实例。此类实例可以存在于本公开的附图中、权利要求中和/或说明书中。
图1示出了示例半导体装置的横截面视图。在图1所示的实例中，半导体装置100可以包括基底结构110、衬底120、电子装置130、包封料140和互连件150。另外，半导体装置100可以进一步包括位于衬底120与电子装置130之间的介电层160。在一些实例中，电子装置130可以包括如半导体管芯或晶体管等有源装置，并且在其它实例中，电子装置130可以包括如电阻器、电容器、电感器、连接器或等同物等无源装置。
基底结构110可以包括导电层112和介电层113。衬底120可以包括介电层121a、122a、123a和124a以及导电层121b、122b、123b、124b、121c、122c、123c、124c和124d。电子装置130可以包括互连件131和132。包封料140可以接触衬底120的顶表面和电子装置130的侧表面。另外，互连件150可以包括导电层151、152和153并且可以位于基底结构110的底表面上。
基底结构110、衬底120、包封料140和互连件150可以被称为半导体封装190或封装190。另外，半导体封装190可以保护电子装置130免受外部元件和/或环境暴露的影响。另外，半导体封装190可以提供外部装置(未示出)与电子装置130之间的电耦接。
图2A到2L示出了用于制造示例半导体装置的示例方法的横截面视图。图2A示出了在早期制造阶段提供载体171的工艺。
在图2A所示的实例中，载体171是基本上平面的。在一些实例中，载体171也可以被称为板、晶圆、面板或条带。另外，在一些实例中，载体171可以由金属(例如，SUS)、晶圆(例如，硅)、陶瓷(例如，氧化铝)、玻璃(例如，钠钙玻璃)或任何等同物中的任何一种或多种制成。载体171的厚度可以在大约500μm到大约1500μm的范围并且宽度可以在大约100mm到大约500mm的范围内。在形成基底结构110、形成衬底120以及附接和包封电子装置130的工艺期间，载体171可以起到以集成方式处理多个组件的作用。在一些实例中，载体171可以普遍应用于本公开的所有实例。
图2B示出了在稍后制造阶段形成导电层111和112的工艺。在图2B所示的实例中，可以在载体171上形成导电层111。在一些实例中，导电层111可以被称为晶种层或基底层。在一些实例中，晶种层111可以由各种导电材料(例如，钛、钨、钛/钨、铜、金、银、钯、镍或其等同物)中的任何导电材料制成。另外，在一些实例中，晶种层111可以使用各种工艺(例如，溅射、化学镀(electroless plating)、电镀、物理气相沉积(PVD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、原子层沉积(ALD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)或其等同物)中的任何工艺形成。晶种层111的厚度可以在大约500埃
Figure BDA0002452933620000051
到大约
Figure BDA0002452933620000052
的范围内。晶种层111可以促进在稍后制造阶段将导电层112形成到预定的厚度。
另外，在图2B所示的实例中，可以在相对较薄的晶种层111上形成相对较厚的导电层112。在一些实例中，可以使用经过图案化的掩模(未示出)在晶种层111上形成图案，并且相对较厚的导电层112可以仅形成于图案内。在一些实例中，导电层112可以被称为导电桩或凸点下金属。在一些实例中，导电桩112可以由各种导电材料(例如，铜、金、银或其等同物)中的任何导电材料制成。导电桩112可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。在导电桩112形成之后，可以去除经过图案化的掩模。另外，还可以使用例如软蚀刻工艺来去除在相对较厚的导电桩112周围形成的相对较薄的晶种层111。导电桩112的厚度可以在大约1μm到大约10μm的范围内。导电桩112可以起到在稍后制造阶段在导电桩112上堆积衬底120并且在导电桩112下方形成互连件150的作用。
图2C示出了在稍后制造阶段形成介电层113的工艺。在图2C所示的实例中，可以由介电层113覆盖在载体171上形成的导电桩111和112。在一些实例中，介电层113可以使用模制操作形成，并且介电层113可以接触导电桩112的侧面。在一些实例中，介电层113可以覆盖导电桩112的顶表面和侧表面，并且介电层113可以不覆盖导电桩112的底表面。在一些实例中，介电层113可以不覆盖导电桩112的顶表面以允许导电桩112的顶表面通过介电层113暴露于外部。在一些实例中，介电层113可以被称为包封料、密封剂、环氧树脂模制化合物、保护材料或环氧模制树脂。另外，在一些实例中，包封料113也可以被称为包封部件、模制部件、保护部件或主体。在一些实例中，包封料113可以包括但不限于有机树脂、无机填料、固化剂、催化剂、着色剂、阻燃剂或前述各项的等同物。包封料113可以通过包含模制操作的各种工艺中的任何工艺形成。在一些实例中，包封料113可以通过但不限于压缩模制、传递模制、液相包封料模制、真空层压、膏印刷或膜辅助模制形成。包封料113的厚度可以在大约50μm到大约100μm的范围内。包封料113可以包封导电桩111和112，以减少或防止衬底120在稍后阶段翘曲。
图2D示出了用于在稍后制造阶段去除导电桩112和包封料113的部分的工艺。在图2D所示的实例中，如通过研磨或蚀刻去除导电桩112以及包封料113的顶表面，以使导电桩112和包封料113的顶表面共面。在一些实例中，可以通过研磨和/或蚀刻使导电桩112和包封料113的顶表面共面，以改善在导电桩112和包封料113上形成的衬底120的平面性。以这种方式，可以完成基底结构110，稍后可以在基底结构110上形成衬底120，并且可以在基底结构110的下方形成互连件150。
图2E示出了在稍后制造阶段形成衬底120的工艺。在图2E所示的实例中，可以在基底结构110上直接形成或堆积基本上平面的衬底120。在一个实例中，可以在基底结构110上多次堆积介电层121a、122a、123a和124a以及导电层121b、122b、123b、124b、121c、122c、123c、124c和124d以完成衬底120。
在一些实例中，介电层121a可以覆盖基底结构110的顶表面。由于基底结构110的顶表面可以是平面的，因此介电层121a也可以是平面的。在一些实例中，介电层121a可以被称为钝化层、绝缘层或保护层。介电层121a可以由各种非导电材料(例如，Si3N4、SiO2、SiON、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、环氧树脂、酚树脂、硅树脂、丙烯酸酯聚合物或其等同物)中的任何非导电材料制成。另外，介电层121a可以使用各种工艺(例如，PVD、CVD、MOCVD、ALD、LPCVD、PECVD、印刷、旋涂、喷涂、烧结、热氧化或其等同物)中的任何工艺形成。在一些实例中，介电层121a可以被图案化以形成暴露导电桩112同时覆盖包封料113的开口。介电层121a的厚度可以在大约1μm到大约10μm的范围内，并且开口的宽度可以在大约5μm到大约70μm的范围内。
在一些实例中，导电层121b可以保形地形成于介电层121a和暴露的导电桩112上。在一些实例中，导电层121b可以被称为晶种层或基底层。在一些实例中，晶种层121b可以形成于介电层121a的顶表面、开口的侧壁和导电桩112的顶表面上。
在一些实例中，晶种层121b可以由各种导电材料(例如，钛、钨、钛/钨、铜、金、银、钯、镍或其等同物)中的任何导电材料制成。另外，在一些实例中，晶种层121b可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。晶种层121b的厚度可以在大约
Figure BDA0002452933620000071
到大约
Figure BDA0002452933620000072
的范围内。晶种层121b可以促进在稍后制造阶段将导电层121c形成到预定的厚度。
尽管未示出，但是可以在晶种层121b上形成掩模，然后所述掩模通过一般的光刻工艺被图案化。在一些实例中，晶种层121b可以通过经过图案化的掩模暴露于外部。在一些实例中，经过图案化的掩模可以包含可以将晶种层121b的一部分暴露到外部的开口。在一些实例中，掩模可以被称为光刻胶或树脂。
在一些实例中，可以在经过图案化的掩模的位于相对较薄的晶种层121b的暴露部分上的开口中形成相对较厚的导电层121c。此处，由于已经使用掩模形成了图案，因此相对较厚的导电层121c可以仅形成于形成的图案的开口内。在一些实例中，导电层121c可以被称为重新分布层(RDL)、布线图案或电路图案。在一些实例中，重新分布层121c可以由各种导电材料(例如，铜、金、银或其等同物)中的任何导电材料制成。重新分布层121c可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。在重新分布层121c形成之后，可以去除经过图案化的掩模。另外，在经过图案化的掩模的下方形成的相对较薄的晶种层121b可以在经过图案化的掩模去除之后使用例如软蚀刻工艺去除。重新分布层121c的厚度可以在大约2μm到大约10μm的范围内。重新分布层121c可以起到将电子装置130的互连件131和132电连接到基底结构110的导电桩112的作用。
重复上述工艺多次以在基底结构110上形成衬底120。此处，在衬底120的最顶表面上形成的导电层124c可以被称为导电衬垫、微衬垫或键合衬垫。在一些实例中，导电衬垫124c可以形成为从衬底120的顶表面凸出预定的高度。导电衬垫124c的宽度可以在大约1μm到大约80μm的范围内。
在一些实例中，为了防止导电衬垫124c被氧化，可以在导电衬垫124c的顶表面上进一步形成抗氧化剂层124d。在一些实例中，抗氧化剂层124d可以被称为防腐蚀层或焊料扩展改善层。在一些实例中，抗氧化剂层124d可以由锡、金、银、镍、钯或其等同物制成。抗氧化剂层124d可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。抗氧化剂层124d的宽度可以在大约1μm到大约80μm的范围内。
在一些实例中，衬底120可以被称为互连结构、堆积结构、电路堆叠结构、RDL结构或印刷电路板。在本公开所示的实例中，展示了包括四个介电层121a、122a、123a和124a、四个导电层121b、122b、123b和124b以及四个导电层121c、122c、123c和124c的衬底120。然而，这些层的数量可以小于或大于四。
在图2的实例中，衬底120呈现为重新分布层(RDL)衬底。RDL衬底可以包括(a)可以在RDL衬底要电耦接到的电子装置之上逐层形成的，或者(b)可以在将电子装置和RDL衬底耦接在一起之后完全去除或至少部分地去除的载体之上逐层形成的一个或多个导电重新分布层和一个或多个介电层。RDL衬底可以在圆形晶圆上以晶圆级工艺逐层制造为晶圆级衬底，和/或在矩形或方形面板载体上以面板级工艺逐层制造为面板级衬底。RDL衬底可以以可以包含与限定相应的导电重新分布图案或迹线的一个或多个导电层交替堆叠的一个或多个介电层的添加剂堆积工艺形成，所述导电重新分布图案或迹线被配置成共同(a)将电迹线扇出电子装置的占用空间外，和/或(b)将电迹线扇入电子装置的占用空间内。可以使用镀覆工艺，例如电镀工艺或化学镀工艺来形成导电图案。导电图案可以包括导电材料，例如铜或其它可镀覆金属。可以使用光图案化工艺，例如光刻工艺和用于形成光刻掩模的光刻胶材料来制作导电图案的位置。RDL衬底的介电层可以利用可以包含光刻掩模的光图案化工艺来图案化，通过所述光刻掩模，光暴露到光图案期望的特征，如介电层中的通孔中。因此，介电层可以由光可限定的有机介电材料，例如聚酰亚胺(PI)、苯并环丁烯(BCB)或聚苯并恶唑(PBO)制成。此类介电材料可以以液体形式旋涂或以其它方式涂覆，而不是以预先形成的膜的形式附接。为了允许适当地形成期望的光限定的特征，此类光可限定的介电材料可以省略结构增强剂，或者可以是不含填料的，没有可能会干扰来自光图案化工艺的光的线、织造物或其它颗粒。在一些实例中，不含填料的介电材料的此类不含填料的特性可以允许减小所得的介电层的厚度。尽管上文描述的光可限定的介电材料可以是有机材料，但是在其它实例中，RDL衬底的介电材料可以包括一个或多个无机介电层。一个或多个无机介电层的一些实例可以包括氮化硅(Si3N4)、氧化硅(SiO2)和/或SiON。所述一个或多个无机介电层可以通过使用氧化或氮化工艺而不是使用光限定的有机介电材料来生长无机介电层来形成。此类无机介电层可以是不含填料的，没有线、织造物或其它不同的无机颗粒。在一些实例中，RDL衬底可以省略永久性芯结构或载体，例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料，并且这些类型的RDL衬底可以被称为无芯衬底。
在其它实例中，衬底120可以是预先形成的衬底。预先形成的衬底可以在附接到电子装置之前制造并且可以包括位于相应的导电层之间的介电层。导电层可以包括铜并且可以使用电镀工艺形成。介电层可以是可以以预先形成的膜的形式而不是以液体的形式附接的相对较厚的非光可限定层，并且可以包含用于刚性和/或结构性支撑的具有如线、织造物和/或其它无机颗粒等填料的树脂。由于介电层是非光可限定的，因此可以通过使用钻孔或激光来形成如通孔或开口等特征。在一些实例中，介电层可以包括预浸材料或味之素增层膜(ABF)。预先形成的衬底可以包含永久性芯结构或载体，例如包括双马来酰亚胺三嗪(BT)或FR4的介电材料，并且介电层和导电层可以形成于永久性芯结构上。在其它实例中，预先形成的衬底可以是省略永久性芯结构的无芯衬底，并且介电层和导电层可以形成于在形成介电层和导电层之后并且在附接到电子装置之前被去除的牺牲载体上。预先形成的衬底可以被称为印刷电路板(PCB)或层压衬底。此类预先形成的衬底可以通过半加成工艺或经改进的半加成工艺来形成。
图2F示出了在稍后制造阶段附接电子装置130的工艺。在图2F所示的实例中，可以将电子装置130电连接到衬底120。在一些实例中，拾放设备(未示出)可以拾取电子装置130以将电子装置130放置在衬底120的导电衬垫124c上。接下来，可以例如通过批量回流、热压缩或激光辅助键合将电子装置130电连接到衬底120。
在一些实例中，电子装置130可以被称为半导体管芯或半导体芯片。另外，在一些实例中，电子装置130可以包括逻辑管芯、微控制单元、存储器、数字信号处理器、网络处理器、电源管理单元、音频处理器、RF电路、无线基带片上系统处理器、专用集成电路或其等同物中的至少一个。
在一些实例中，电子装置130可以包含有源区域和非有源区域。另外，在一些实例中，有源区域可以安置成面对衬底120。另外，在一些实例中，有源区域可以包含互连件131。在一些实例中，互连件131可以被称为管芯衬垫、键合衬垫、铝衬垫、导电柱或导电桩。互连件131的宽度可以在大约2μm到大约80μm的范围内。
另外，互连件131中的每个互连件可以通过低熔点材料132连接到衬底120的导电衬垫124c和/或抗氧化剂层124d。在一个实例中，低熔点材料132可以包括Sn、Ag、Pb、Cu、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi、Sn-Ag-Cu或任何等同物中的任何一种或多种。电子装置130的互连件131和衬底120的导电衬垫124c可以通过低熔点材料132彼此电连接。
在一些实例中，可以在衬底120与电子装置130之间进一步填充介电层160。在一些实例中，介电层160可以围绕电子装置130的互连件131、低熔点材料132、导电衬垫124c和抗氧化剂层124d。在一些实例中，介电层160可以被称为底部填料、毛细管底部填料(CUF)或非导电膏。在一些实例中，底部填料160可以是不具有无机填料的树脂。在一些实例中，在电子装置130电连接到衬底120之后，底部填料160可以通过毛细管注入到电子装置130与衬底120之间的间隙中，然后进行固化。在一些实例中，底部填料160可以围绕电子装置130与衬底120之间的间隙的周边形成，然后底部填料160将通过毛细管力填充间隙。在一些实例中，首先底部填料160可以分配以覆盖安置在衬底120上的导电衬垫124c，然后电子装置130的互连件131和/或低熔点材料132可以电连接到导电衬垫124c，同时穿过底部填料160。底部填料160可以防止电子装置130由于物理冲击或化学冲击而与衬底120断开电连接。
图2G示出了在稍后制造阶段的包封工艺。在图2G所示的实例中，可以由包封料140包封电子装置130。在一些实例中，包封料140可以接触电子装置130的顶表面和侧表面并且可以接触底部填料160。然而，在一些实例中，包封料140可以不接触电子装置130的底表面和底部填料160的底表面。在一些实例中，包封料140可以不接触电子装置130的顶表面以允许电子装置130的顶表面通过包封料140暴露于外部。在一些实例中，包封料140可以被称为环氧树脂模制化合物、环氧模制树脂、保护材料或密封剂。另外，在一些实例中，包封料140可以被称为模制部件、密封部件、包封部件、封装或主体。在一些实例中，包封料140可以包括但不限于有机树脂、无机填料、固化剂、催化剂、着色剂或阻燃剂。包封料140可以通过各种工艺中的任何工艺形成。在一些实例中，包封料140可以通过但不限于模制操作、压缩模制、传递模制、液相包封料模制、真空层压、膏印刷或膜辅助模制形成。包封料140的厚度可以在大约50μm到大约1000μm的范围内。包封料140可以包封电子装置130以保护电子装置130免受外部元件和/或环境暴露的影响。在一些实例中，包封料140可以充当底部填料，如在衬底120与电子装置130之间形成的经模制的底部填料。
在一些实例中，形成包封料140的材料可以与基底结构110的材料相同或不同。当形成包封电子装置130的包封料140的材料与基底结构110的材料相同时，半导体装置100的上部区域和下部区域的热膨胀系数(CTE)可以彼此基本上相同以抑制半导体装置100的翘曲。
例如，衬底120的CTE可以与包封料140的CTE不同。因此，衬底120和包封料140可能由于在半导体封装的制造工艺期间施加的热量或在半导体封装的电操作期间产生的热量而往往在一个方向上翘曲或弯曲。然而，可以对包封料113和140进行选择以具有相同或类似的CTE，并且所述包封料可以分别形成于衬底120的相对的上部部分和下部部分。因此，由于包封料140的CTE与衬底120的CTE之间的差异而引起的膨胀或翘曲往往会抵消由于包封料113的CTE与衬底120的CTE之间的差异而引起的膨胀或翘曲。因此，即使在半导体封装的制造工艺期间施加热量或在半导体封装的电操作期间产生热量，也可以抑制或减小半导体封装在一个方向上弯曲的翘曲量。在一些实例中，衬底120的CTE可以大于包封料140的CTE并且大于包封料113的CTE。
还可以存在形成包封电子装置130的包封料140的材料与包封料113和/或基底结构110的材料不同，同时仍改善半导装置100的翘曲的实例。例如，即使彼此不同，也可以选择包封料140的材料或CTE和包封料113的材料或CTE，使得当还考虑包封料140的厚度、包封料113的厚度，和/或电子装置130的存在时，净效应是由于衬底120与包封料140之间的界面引起的翘曲抵消了沿衬底120与包封料113之间的接口的翘曲。
图2H示出了在稍后制造阶段去除模制部件140的一部分的工艺。在图2H所示的实例中，可以研磨和/或蚀刻模制部件140，由此将电子装置130的顶表面暴露于外部。可以执行去除工艺直到电子装置130的厚度变得小于大约500μm。作为去除工艺的结果，模制部件140的顶表面可以与电子装置130的顶表面共面。
图2I示出了在稍后制造阶段附接载体172的工艺。在图2I所示的实例中，可以将载体172附接到模制部件140以及电子装置130的顶表面。在一些实例中，载体172可以使用临时粘合层附接到模制部件140以及电子装置130的顶表面。临时粘合层可以由被配置成当暴露于高温或光时会失去其粘合性的材料制成。上部载体172可以在去除下部载体171的同时固定或支撑装置。上部载体172可以是基本上平面的。在一些实例中，上部载体172也可以被称为板、晶圆、面板或条带。另外，在一些实例中，上部载体172可以由金属(例如，SUS)、晶圆(例如，硅)、陶瓷(例如，氧化铝)、玻璃(例如，钠钙玻璃)或任何等同物中的任何一种或多种制成。上部载体172的厚度可以在大约500μm到大约1500μm的范围内并且宽度可以在大约100mm到大约500mm的范围内。
图2J示出了在稍后制造阶段去除载体171的工艺。在图2J所示的实例中，可以从基底结构110去除载体171。在一些实例中，载体171可以使用研磨操作和/或蚀刻操作通过研磨和/或蚀刻来去除。在一些实例中，在对载体171执行研磨和/或蚀刻时，还可以去除在导电桩112的底表面上形成的晶种层111。因此，导电桩112的底表面可以通过包封料113暴露于外部。在一些实例中，导电桩112的底表面可以与包封料113的底表面共面。
图2K示出了在稍后制造阶段去除载体172的工艺。在图2K所示的实例中，也可以去除上部载体172。如上文所描述的，电子装置130的顶表面和包封料140的顶表面可以在半导体装置100上共面，而基底结构110的导电桩112的底表面和包封料113的底表面可以在半导体装置100下方共面。在一些实例中，载体172可以以与如上文关于图2J所讨论的去除载体171相同的方式或类似的方式使用研磨操作和/或蚀刻操作来去除。
图2L示出了在稍后制造阶段形成互连件150的工艺。在图2L所示的实例中，可以在基底结构110的整个底表面上形成相对较薄的导电层151，并且可以在相对较薄的导电层151上形成相对较厚的导电层152。在一些实例中，相对较薄的导电层151可以被称为晶种层或基底层。在一些实例中，晶种层151可以形成于导电桩112的底表面和包封料113的底表面上。
晶种层151可以由各种导电材料(例如，钛、钨、钛/钨、铜、金、银、钯、镍或其等同物)中的任何导电材料制成。另外，在一些实例中，晶种层151可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。晶种层151的厚度可以在大约
Figure BDA0002452933620000121
到大约
Figure BDA0002452933620000122
的范围内。晶种层151可以促进在稍后制造阶段将导电层152形成到预定的厚度。
在一些实例中，可以在相对较薄的晶种层151上形成相对较厚的导电层152。在一些实例中，可以使用经过图案化的掩模(未示出)在晶种层151上形成图案或开口，并且相对较厚的导电层152可以仅形成于图案或开口内。在一些实例中，可以在经过图案化的掩模的位于相对较薄的晶种层151的暴露部分上的图案中形成相对较厚的导电层152。此处，由于已经使用掩模形成了图案，因此相对较厚的导电层152可以仅形成于形成的图案的开口内。在一些实例中，导电层152可以被称为导电柱或导电桩。在一些实例中，导电柱152可以由各种导电材料(例如，铜、金、银或其等同物)中的任何导电材料制成。导电柱152可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。在导电柱152形成之后，可以去除经过图案化的掩模。另外，还可以使用例如软蚀刻工艺来去除在相对较厚的导电柱152周围形成的相对较薄的晶种层151。导电柱152的厚度可以在大约5μm到大约50μm的范围内。
在一些实例中，可以将具有相对较低熔点的材料的互连尖端153连接到导电柱152。在一些实例中，互连尖端153的熔点可以比导电柱152的熔点低。在一些实例中，互连尖端153可以被称为焊球、焊料凸点、焊帽、导电球、导电凸点或导电帽。在一些实例中，在将焊料分配到导电柱152的底表面之后，互连尖端153可以通过批量回流工艺形成于导电柱152的底表面上。在一些实例中，可以重新使用用于形成导电柱152的经过图案化的掩模以形成互连尖端153。在一些实例中，互连尖端153可以形成于经过图案化的掩模的位于导电柱152的暴露部分上的图案或开口中。此处，由于已经使用掩模形成了图案，因此互连尖端153可以仅形成于图案的开口内。在一些实例中，互连尖端153可以包括Sn、Ag、Pb、Cu、Sn-Pb、Sn37-Pb、Sn95-Pb、Sn-Pb-Ag、Sn-Cu、Sn-Ag、Sn-Au、Sn-Bi、Sn-Ag-Cu或任何等同物中的任何一种或多种。互连尖端153的厚度可以在大约0.5μm到大约30μm的范围内并且宽度可以在从大约2μm到大约80μm的范围内。在互连尖端153形成之后，可以去除经过图案化的掩模。在一些实例中，如果互连尖端153使用经过图案化的掩模形成，则现在可以使用但不限于软蚀刻工艺来去除形成于导电柱152周围的晶种层151以及互连尖端153。
如上文所描述的，可以完成包括晶种层151、导电柱152和互连尖端153的互连件150。互连件150可以起到将半导体装置100或半导体封装190电连接到外部装置(未示出)的作用。尽管互连件150被示为在去除载体172之后形成，但这不限制本公开。在其它实例中，互连件150可以在去除载体172之前形成。
图3示出了另一个示例半导体装置的横截面视图。由于制造工艺的差异，图3所示的半导体装置200可以具有与图1所示的半导体装置100的结构不同的结构。在图3所示的实例中，半导体装置200可以包括衬底120、电子装置130、包封料140、基底结构210和互连件150。
衬底120可以包括介电层121a、122a、123a和124a以及导电层121b、122b、123b、124b、121c、122c、123c、124c和124d。电子装置130可以包括互连件131和132。包封料140可以接触衬底120的顶表面和电子装置130的侧表面。基底结构210可以包括导电层211和212以及介电层213。另外，互连件150可以位于基底结构210的底表面上。
衬底120、包封料140、基底结构210和互连件150可以被称为半导体封装290或封装290。半导体封装290可以保护电子装置130免受外部元件和/或环境暴露的影响。另外，半导体封装290可以提供外部装置(未示出)与电子装置130之间的电耦接。
图4A到4K示出了用于制造另一个示例半导体装置的示例方法的横截面视图。图4A示出了在早期制造阶段提供载体271的工艺。
在图4A所示的实例中，载体271可以具有与图2A所示的载体171的形状和特性基本上相同的形状和特性。
图4B示出了在稍后制造阶段形成衬底120的工艺。在图4B所示的实例中，可以在载体271上直接形成或堆积基本上平面的衬底120。在一个实例中，可以顺序地在载体271上彼此堆积介电层121a、122a、123a和124a以及导电层121b、122b、123b、124b、121c、122c、123c、124c和124d，由此完成衬底120。
在一些实例中，介电层121a可以覆盖载体271的顶表面。由于载体271的顶表面形成为平面的，所以介电层121a也可以形成为平面的。在一些实例中，介电层121a可以被称为钝化层、绝缘层或保护层。介电层121a可以由各种非导电材料(例如，Si3N4、SiO2、SiON、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、双马来酰亚胺三嗪(BT)、环氧树脂、酚树脂、硅树脂、丙烯酸酯聚合物或其等同物)中的任何非导电材料制成。另外，介电层121a可以使用各种工艺(例如，PVD、CVD、MOCVD、ALD、LPCVD、PECVD、印刷、旋涂、喷涂、烧结、热氧化或其等同物)中的任何工艺形成。在一些实例中，介电层121a可以被图案化以形成暴露载体271的一部分的开口。介电层121a的厚度可以在大约1μm到大约10μm的范围内并且开口的宽度可以在大约5μm到大约70μm的范围内。
在一些实例中，导电层121b可以完全地形成于介电层121a和载体271的暴露的区域上。在一些实例中，导电层121b可以被称为晶种层或基底层。在一些实例中，晶种层121b可以分别形成于介电层121a的顶表面、开口的侧壁和载体271的顶表面上，并且所有这些导电层121b可以彼此电连接。
在一些实例中，晶种层121b可以由各种导电材料(例如，钛、钨、钛/钨、铜、金、银、钯、镍或其等同物)中的任何导电材料制成。另外，在一些实例中，晶种层121b可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。晶种层121b的厚度可以在大约
Figure BDA0002452933620000151
到大约
Figure BDA0002452933620000152
的范围内。晶种层121b可以促进在稍后制造阶段将导电层121c形成到预定的厚度。
尽管未示出，但是可以在晶种层121b上形成掩模，然后所述掩模通过一般的光刻蚀刻工艺被图案化。在一些实例中，晶种层121b可以通过经过图案化的掩模暴露于外部。在一些实例中，掩模可以被称为光刻胶或树脂。
在一些实例中，可以在经过图案化的掩模的位于相对较薄的晶种层121b的暴露部分上的开口中形成相对较厚的导电层121c。此处，由于已经使用掩模形成了图案，因此相对较厚的导电层121c可以仅形成于图案的开口内。在一些实例中，导电层121c可以被称为重新分布层(RDL)、布线图案或电路图案。在一些实例中，重新分布层121c可以由各种导电材料(例如，铜、金、银或其等同物)中的任何导电材料制成。重新分布层121c可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。在重新分布层121c形成之后，可以去除经过图案化的掩模。另外，在经过图案化的掩模的下方形成的相对较薄的晶种层121b可以在经过图案化的掩模去除之后使用软蚀刻工艺去除。重新分布层121c的厚度可以在大约2μm到大约10μm的范围内。重新分布层121c可以起到将电子装置130的互连件131和132电连接到基底结构210的导电桩212的作用。
可以重复上述工艺多次，由此在载体271上完成衬底120。此处，在衬底120的最顶表面上形成的导电层124c可以被称为导电衬垫、微衬垫或键合衬垫。在一些实例中，导电衬垫124c可以形成为从衬底120的顶表面凸出预定的高度。导电衬垫124c的宽度可以在大约2μm到大约80μm的范围内。
在一些实例中，为了防止导电衬垫124c被氧化，可以在导电衬垫124c的顶表面上进一步形成抗氧化剂层124d。在一些实例中，抗氧化剂层124d可以由锡、金、银、镍、钯或其等同物制成。抗氧化剂层124d可以被称为防腐蚀层或焊料扩展改善层。抗氧化剂层124d可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。抗氧化剂层124d的宽度可以在大约1μm到大约80μm的范围内。
在一些实例中，衬底120可以被称为互连结构、堆积结构、电路堆叠结构、RDL结构或印刷电路板。在示出本公开的实例中，展示了包括四个介电层121a、122a、123a和124a、四个导电层121b、122b、123b和124b以及四个导电层121c、122c、123c和124c的衬底120。然而，这些层的数量可以小于或大于四。
图4C示出了在稍后制造阶段附接电子装置130的工艺。在图4C所示的实例中，附接电子装置130的工艺可以与图2F所示的附接电子装置130的工艺类似。
图4D示出了在稍后制造阶段的包封工艺。在图4D所示的实例中，包封工艺可以与图2G的包封工艺相同或类似。
图4E示出了在稍后制造阶段去除模制部件140的一部分的工艺。在图4E所示的实例中，去除工艺可以与图2H的去除工艺相同或类似。
图4F示出了在稍后制造阶段附接载体272的工艺。图4F所示的附接载体272的工艺可以与图2I中的附接载体272的工艺相同或类似。
图4G示出了在稍后制造阶段去除载体271的工艺。在图4G所示的实例中，可以从衬底120去除载体271。在一些实例中，载体271可以通过研磨和/或蚀刻去除。在一些实例中，在对载体271执行研磨和/或蚀刻时，可以去除在衬底120的底表面上形成的晶种层121b。在一些实例中，可以去除重新分布层121c的底表面。因此，衬底120的重新分布层121c的底表面可以通过介电层121a暴露于外部。在一些实例中，重新分布层121c的底表面可以与介电层121a的底表面共面。
图4H示出了在稍后制造阶段形成导电层211和212的工艺。在图4H所示的实例中，可以在衬底120的底表面上形成导电层211和212。在一些实例中，导电层211和212可以形成于衬底120的介电层121a和重新分布层121c的底表面上。在一些实例中，导电层211可以被称为晶种层或基底层。在一些实例中，晶种层211可以由各种导电材料(例如，钛、钨、钛/钨、铜、金、银、钯、镍或其等同物)中的任何导电材料制成。另外，在一些实例中，晶种层211可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。晶种层211的厚度可以在大约
Figure BDA0002452933620000161
到大约
Figure BDA0002452933620000162
的范围内。晶种层211可以促进在稍后制造阶段将导电层212形成到预定的厚度。
另外，在图4H所示的实例中，可以在相对较薄的晶种层211上形成相对较厚的导电层212。在一些实例中，可以使用经过图案化的掩模在晶种层211上形成图案或开口，并且导电层212可以仅形成于所述图案或开口内。在一些实例中，导电层212可以形成于经过图案化的掩模的位于晶种层211的暴露部分上的开口中。此处，由于已经使用掩模形成了图案，因此导电层212可以仅形成于形成的图案的开口内。在一些实例中，导电层212可以被称为导电桩或凸点下金属。在一些实例中，导电桩212可以由各种导电材料(例如，铜、金、银或其等同物)中的任何导电材料制成。导电桩212可以使用各种工艺(例如，溅射、化学镀、电镀、PVD、CVD、MOCVD、ALD、LPCVD、PECVD或其等同物)中的任何工艺形成。在导电桩212形成之后，可以去除经过图案化的掩模。另外，还可以使用软蚀刻工艺来去除在相对较厚的导电桩212周围形成的相对较薄的晶种层。导电桩212的厚度可以在大约1μm到大约10μm的范围内。导电桩212可以电连接到要在稍后制造阶段在衬底120和/或基底结构210下方形成的互连件150。
图4I示出了在稍后制造阶段形成介电层213的工艺。在图4I所示的实例中，可以由介电层213覆盖在衬底120下方形成的导电桩212。在一些实例中，介电层213可以覆盖导电桩212的底表面和侧表面。然而，介电层213可以不覆盖导电桩212的顶表面。在一些实例中，介电层213可以不覆盖导电桩212的底表面，由此允许导电桩212的底表面通过介电层213暴露于外部。在一些实例中，介电层213可以被称为包封料、密封剂、环氧树脂模制化合物或环氧模制树脂。另外，在一些实例中，包封料213可以被称为包封部件、模制部件、保护部件或主体。在一些实例中，包封料213可以包括但不限于有机树脂、无机填料、固化剂、催化剂、着色剂、阻燃剂或前述各项的等同物。包封料213可以通过各种工艺中的任何工艺形成。在一些实例中，包封料213可以通过但不限于压缩模制、传递模制、液相包封料模制、真空层压、膏印刷或膜辅助模制形成。包封料213的厚度可以在大约1μm到大约10μm的范围内。包封料213可以牢固地包封导电桩212，以减少或防止衬底120在稍后阶段翘曲。
图4J示出了在稍后制造阶段的去除工艺。在图4J所示的实例中，研磨或蚀刻导电桩212以及包封料213的底表面，以通过包封料213的底表面将导电桩212的底表面暴露于外部。在一些实例中，导电桩212的底表面和包封料213的底表面可以形成为共面的。如上文所描述的，在稍后制造阶段，基底结构210可以完成并且互连件150可以在基底结构210下方形成。
图4K示出了在稍后制造阶段形成互连件150的工艺。在图4K所示的实例中，形成互连件150的工艺可以与图2K所示的形成互连件150的工艺基本上相同。
同时，可以去除载体272。如上文所描述的，电子装置130的顶表面可以与半导体装置200上的包封料140的顶表面共面。
总之，一种半导体装置包括：重新分布层(RDL)衬底，所述RDL衬底具有顶表面和底表面，其中所述RDL衬底包括不含填料的介电材料；电子装置，所述电子装置位于所述RDL衬底的所述顶表面上；电互连件，所述电互连件位于所述RDL衬底的所述底表面上并且电耦接到所述电子装置；第一保护材料，所述第一保护材料接触所述电子装置的侧表面和所述RDL衬底的所述顶表面；以及第二保护材料，所述第二保护材料接触所述电互连件的侧表面和所述RDL衬底的所述底表面。
一种用于制造半导体装置的方法包括：形成具有导电桩的基底结构；在所述基底结构上形成重新分布层(RDL)衬底；在所述RDL衬底的顶表面上放置电子装置；以及形成接触所述电子装置的侧表面和所述RDL衬底的所述顶表面的保护材料。
一种用于制造半导体装置的方法包括：在第一载体上形成重新分布层(RDL)衬底，所述RDL衬底具有顶表面和底表面；在所述RDL衬底的所述顶表面上放置电子装置；使用第一模制操作形成第一保护材料，其中所述第一保护材料接触所述电子装置的侧表面和所述RDL衬底的所述顶表面；将第二载体附接到所述第一保护材料；从所述RDL衬底去除所述第一载体；使用第一镀覆操作在所述RDL衬底的所述底表面上形成导电桩；以及使用第二模制操作形成第二保护材料，其中所述第二保护材料接触所述导电桩的侧表面和所述RDL衬底的所述底表面。
本公开包含对某些实例的引用。然而，本领域的技术人员应理解的是，在不脱离本公开的范围的情况下，可以作出各种改变并且可以取代等同物。另外，在不脱离本公开的范围的情况下，可以对所公开的实例进行修改。因此，意图是，本公开不受限于所公开的实例，而本公开将包含落入所附权利要求的范围内的所有实例。

Claims (20)

1.一种半导体装置，其包括：
重新分布层衬底，所述重新分布层衬底具有顶表面和底表面，其中所述重新分布层衬底包括不含填料的介电材料；
电子装置，所述电子装置位于所述重新分布层衬底的所述顶表面上；
电互连件，所述电互连件位于所述重新分布层衬底的所述底表面上并且电耦接到所述电子装置；
第一保护材料，所述第一保护材料接触所述电子装置的侧表面和所述重新分布层衬底的所述顶表面；以及
第二保护材料，所述第二保护材料接触所述电互连件的侧表面和所述重新分布层衬底的所述底表面。
2.根据权利要求1所述的半导体装置，其中所述电互连件包括在所述重新分布层衬底的所述底表面上的导电桩、所述导电桩上的导电柱以及所述导电柱上的互连尖端。
3.根据权利要求2所述的半导体装置，其中所述电互连件进一步包括位于所述导电桩与所述导电柱之间的晶种层。
4.根据权利要求1所述的半导体装置，其中所述电互连件包括在所述重新分布层衬底的所述底表面上的凸点下金属。
5.根据权利要求1所述的半导体装置，其中所述电互连件包括在所述重新分布层衬底的所述底表面上的导电桩和所述导电桩上的焊球。
6.根据权利要求1所述的半导体装置，其中所述重新分布层衬底包括导电层和介电层。
7.根据权利要求6所述的半导体装置，其进一步包括另外的电互连件，所述另外的电互连件位于所述重新分布层衬底的所述顶表面上，所述另外的电互连件用于通过所述导电层将所述电子装置耦接到所述重新分布层衬底的所述底表面上的所述电互连件。
8.根据权利要求1所述的半导体装置，其中所述第一保护材料和所述第二保护材料包括具有相同热膨胀系数的相同材料。
9.根据权利要求1所述的半导体装置，其中所述第一保护材料和所述第二保护材料包括具有相同或类似热膨胀系数的不同材料。
10.根据权利要求1所述的半导体装置，其中所述第一保护材料具有第一热膨胀系数和第一厚度，并且所述第二保护材料具有第二热膨胀系数和第二厚度，使得所述第一保护材料与所述重新分布层衬底之间的翘曲抵消所述第二保护材料与所述重新分布层衬底之间的翘曲。
11.一种用于制造半导体装置的方法，所述方法包括：
形成具有导电桩的基底结构；
在所述基底结构上形成重新分布层衬底；
在所述重新分布层衬底的顶表面上放置电子装置；以及
形成接触所述电子装置的侧表面和所述重新分布层衬底的所述顶表面的保护材料。
12.根据权利要求11所述的方法，其中所述导电桩是使用镀覆操作形成的，并且所述基底结构是在所述镀覆操作之后使用模制操作形成的。
13.根据权利要求11所述的方法，其中所述重新分布层衬底包括不含填料的介电材料，并且所述导电桩是使用镀覆操作形成的，并且所述方法进一步包括使用第二镀覆操作在所述导电桩上形成导电柱并且使用第三镀覆操作在所述导电桩上形成互连尖端。
14.根据权利要求11所述的方法，其中形成所述重新分布层衬底包括：
在所述基底结构上形成第一介电层；
在所述介电层中形成开口以暴露所述导电桩；以及
在所述介电层和所述导电桩上形成导电层。
15.根据权利要求11所述的方法，其中所述基底结构是使用第一模制操作在第一载体上形成的，并且所述保护材料是使用第二模制操作形成的，并且所述方法进一步包括：
在所述保护材料上附接第二载体；
去除所述第一载体；以及
在所述去除所述第一载体之后拆下所述第二载体。
16.一种用于制造半导体装置的方法，所述方法包括：
在第一载体上形成重新分布层衬底，所述重新分布层衬底具有顶表面和底表面；
在所述重新分布层衬底的所述顶表面上放置电子装置；
使用第一模制操作形成第一保护材料，其中所述第一保护材料接触所述电子装置的侧表面和所述重新分布层衬底的所述顶表面；
将第二载体附接到所述第一保护材料；
从所述重新分布层衬底去除所述第一载体；
使用第一镀覆操作在所述重新分布层衬底的所述底表面上形成导电桩；以及
使用第二模制操作形成第二保护材料，其中所述第二保护材料接触所述导电桩的侧表面和所述重新分布层衬底的所述底表面。
17.根据权利要求16所述的方法，其进一步包括使用第二镀覆操作在所述导电桩上形成导电柱并且使用第三镀覆操作在所述导电桩上形成互连尖端。
18.根据权利要求16所述的方法，其进一步包括在所述导电桩上形成焊球。
19.根据权利要求17所述的方法，其进一步包括在所述第三镀覆操作之后去除所述第二载体。
20.根据权利要求16所述的方法，其中所述第一载体是使用研磨或蚀刻操作去除的。
CN202010297973.1A 2019-04-18 2020-04-16 半导体装置及制造半导体装置的方法 Pending CN111834304A (zh)

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