TWI497645B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TWI497645B
TWI497645B TW101127947A TW101127947A TWI497645B TW I497645 B TWI497645 B TW I497645B TW 101127947 A TW101127947 A TW 101127947A TW 101127947 A TW101127947 A TW 101127947A TW I497645 B TWI497645 B TW I497645B
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encapsulant
layer
semiconductor package
forming
semiconductor
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TW201407716A (zh
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許習彰
周信宏
劉鴻汶
廖信一
張江城
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矽品精密工業股份有限公司
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Priority to TW101127947A priority Critical patent/TWI497645B/zh
Priority to CN201210298753.6A priority patent/CN103579022B/zh
Priority to US13/660,223 priority patent/US8766456B2/en
Publication of TW201407716A publication Critical patent/TW201407716A/zh
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Description

半導體封裝件及其製法
本發明係關於半導體封裝件及其製法，特別是關於一種可應用於立體封裝之晶圓級半導體封裝件及其製法。
晶圓級封裝(Wafer Level Packaging,WLP)係為一種半導體封裝方式，其於整片晶圓生產完成後，直接在晶圓上進行封裝測試，完成之後才切割製成單顆尺寸與半導體晶片相仿之WLP封裝件，不須經過打線或填膠，具有較小之封裝尺寸與良好之電性表現，更可符合現今電子元件之微小化(miniaturization)的需求。
傳統之WLP封裝件多採用扇入(Fan in)型態，但伴隨著半導體元件信號輸入/輸出之接腳數目增加，對球距要求趨於嚴格，加上部分元件對於封裝後尺寸以及信號輸出腳位元位置的調整需求，因此變化衍生出扇出(Fan out)，或是扇入及扇出相互運用等各式新型WLP封裝型態，此外，為了因應半導體元件之電路密度持續增加，且封裝體積逐漸縮小之趨勢，更藉由結合導電矽穿孔(Through Silicon Via,TSV)或導電通孔(Pin Through Hole,PTH)之設計，以完成積集度更高之立體晶圓級封裝結構(3D WLP)。
如第1A圖所示，習知半導體封裝件1之製法中，係先於包含有半導體元件10之封裝膠體12中形成穿孔120。
再如第1B圖所示，於穿孔120中電鍍形成導電通孔15。
然後如第1C圖所示，依序形成介電層16、線路層17以及絕緣保護層18。
惟，在形成導電通孔時，上下表面會有過載(overburden)之情況發生，同時在半導體元件所外露之電性接觸墊上亦會形成有金屬，因此必須以化學機械研磨(Chemical Mechanical Polishing,CMP)將突出的金屬磨平，並移除電性接觸墊上的金屬層，以避免電性接觸墊之間短路，此種利用CMP製程的半導體封裝件之製法成本較高。再者，後續製程還需要形成介電層之後才能形成線路層，亦提高製作成本。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種半導體封裝件之製法，係包括：將具有主動面與非主動面之半導體元件以該非主動面接置於承載件上；形成封裝膠體於該承載件上，以包覆該半導體元件之側面，其中，該封裝膠體具有第一表面與相對之第二表面；形成貫通該封裝膠體之至少一穿孔；形成空心之導電通孔於該穿孔中，且同時形成線路層於該外露之半導體元件之主動面與該封裝膠體之第一表面上；形成第一絕緣保護層於該線路層上，且該第一絕緣保護層係填入該空心之導電通孔內；以及移除該承載件。
前述之半導體封裝件之製法中，該封裝膠體之第一表 面可與該半導體元件之主動面齊平。
前述之半導體封裝件之製法中，於形成貫通該封裝膠體之至少一穿孔後，復包括形成圖案化阻層於該半導體元件之主動面與該封裝膠體之第一表面上，並外露出部分該半導體元件之主動面與該封裝膠體之第一表面，再於形成空心之導電通孔於該穿孔中及形成線路層於該外露之半導體元件之主動面與該封裝膠體之第一表面上之後，移除該圖案化阻層。
前述之半導體封裝件之製法中，於形成貫通該封裝膠體之至少一穿孔後，復包括於形成圖案化阻層之前，先於該半導體元件之主動面與該封裝膠體之第一表面上及該穿孔中形成晶種層，且形成該晶種層與該線路層之材料可為銅。
前述之半導體封裝件之製法中，形成該穿孔之方式可為雷射鑽孔，且該第一絕緣保護層可為乾膜，再以壓合之方式將該乾膜壓入該空心之導電通孔內。
前述之半導體封裝件之製法中，於形成該第一絕緣保護層於該線路層上之後，在移除該承載件之前，復包括於該第一絕緣保護層上形成複數第一開孔，以外露部分之該線路層，之後，於該開孔中形成導電元件，其中，該導電元件可為銲錫凸塊或銅柱。
前述之半導體封裝件之製法中，於該第一絕緣保護層上形成該複數第一開孔之後，復包括於該封裝膠體之第二表面上形成線路重佈層；以及於該線路重佈層上形成具有 複數第二開孔之第二絕緣保護層。
本發明復提供一種半導體封裝件，係包括：半導體元件，係具有相對之主動面與非主動面；封裝膠體，係包覆該半導體元件之側面，且該封裝膠體具有第一表面與相對之第二表面；至少一穿孔，係形成於該封裝膠體中且貫通該封裝膠體；空心之導電通孔，係形成於該穿孔中；線路層，係形成於該半導體元件之主動面與該封裝膠體之第一表面上，且該線路層係電性連接該空心之導電通孔；以及第一絕緣保護層，係形成於該線路層上，且該第一絕緣保護層係填入該空心之導電通孔內。
前述之半導體封裝件中，該封裝膠體之第一表面可與該半導體元件之主動面齊平，且該封裝膠體之第二表面可與該半導體元件之非主動面齊平。
前述之半導體封裝件中，復包括形成於該線路層與封裝膠體之間、線路層與半導體元件之間及空心之導電通孔與封裝膠體之間的晶種層。
前述之半導體封裝件中，該第一絕緣保護層可為乾膜，且該第一絕緣保護層具有外露部分該線路層之複數第一開孔，又該半導體封裝件復包括導電元件，可形成於該第一開孔中，以電性連接該線路層。
前述之半導體封裝件中，復可包括線路重佈層，係形成於該封裝膠體之第二表面上；以及具有複數第二開孔之第二絕緣保護層，係形成於該線路重佈層上。
由上可知，本發明之半導體封裝件及其製法，係藉由 先於封裝膠體中形成穿孔，再一次性的形成導電通孔與線路層，省略傳統半導體封裝件中先形成絕緣保護層之重佈線路製程以及CMP製程，故相較於習知技術，本發明之半導體封裝件之製法能有效節省製程步驟，以大幅提升封裝件之生產效率。
以下藉由特定的具體實施例說明本發明之實施方式，熟知本領域技術之人員可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟知本領域技術之人員之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2H圖，係為本發明之半導體封裝件2之製法之剖面示意圖。
如第2A圖所示，將具有主動面20a與非主動面20b之半導體元件20以該非主動面20b接置於承載件21上， 其中，該主動面上可具有電性接觸墊201。
於本實施例中，該半導體元件20係為半導體晶片，且該承載件21之材質係為玻璃纖維板(FR4)、玻璃或金屬。
如第2B圖所示，形成封裝膠體22於該承載件21上，以包覆該半導體元件20之側面，其中，該封裝膠體22具有與該半導體元件20之主動面20a齊平的第一表面22a與相對之第二表面22b。
於本實施例中，該封裝膠體22可為環氧樹脂，其可利用壓合(lamination)或模壓(molding)方式形成。又有關該封裝膠體22之材料並不限於上述。
如第2C圖所示，形成貫通該封裝膠體22之至少一穿孔220。
於本實施例中，形成該穿孔220之方法可為雷射鑽孔。
如第2D圖所示，於該半導體元件20之主動面20a與該封裝膠體22之第一表面22a上及該穿孔220中形成晶種層23。
於本實施例中，形成該晶種層23之材料可為銅，該晶種層23係作為後續電鍍製程時之電流路徑。
如第2E圖所示，形成圖案化阻層24於該半導體元件20之主動面20a與該封裝膠體22之第一表面22a上，並外露出部分該半導體元件之主動面與該封裝膠體之第一表面。
如第2F圖所示，電鍍形成空心之導電通孔25於該穿 孔220中，且同時形成線路層26於該外露之半導體元件20之主動面20a與該封裝膠體22之第一表面22a上。
於本實施例中，形成該線路層之材料可為銅。
如第2G圖所示，移除該圖案化阻層24，再形成第一絕緣保護層27於該線路層26上，接著於該第一絕緣保護層27上形成複數第一開孔270，以外露部分之該線路層26。
於本實施例中，該第一絕緣保護層27可為乾膜，並以壓合之方式將該乾膜壓入該該空心之導電通孔25內。
如第2H圖所示，於該第一開孔270中形成導電元件28，俾使該半導體封裝件2能藉由該些導電元件28接置於如電路板之電子裝置上，再移除該承載件21。
於本實施例中，該導電元件28可為銲錫凸塊或銅柱。
於另一實施例中，如第2H’圖所示之半導體封裝件2’，於形成第一絕緣保護層27於該線路層26上，且於該第一絕緣保護層27上形成該複數第一開孔270之後，先於該第一絕緣保護層27上接置第二承載件21’，再移除承載件21。
接著，於該封裝膠體22之第二表面22b上形成線路重佈層29，其中，該線路重佈層29係由介電層290、導電盲孔291與第二線路層292所組成，再於該線路重佈層29上形成具有複數第二開孔270’之第二絕緣保護層27’，以外露出部份之該第二線路層292。
如第2I’圖所示，移除該第二承載件21’，再於該第一開孔270中形成導電元件28，俾使半導體封裝件2’能藉由該些導電元件28相互堆疊以形成立體封裝結構或接置於 如電路板之電子裝置上。
本發明提供一種半導體封裝件2,2’，係包括：半導體元件20，係具有相對之主動面20a與非主動面20b，其中，該主動面上具有電性接觸墊201；封裝膠體22，係包覆該半導體元件20之側面，且該封裝膠體22具有與該半導體元件20之主動面20a齊平的第一表面22a以及與該半導體元件20之非主動面22b齊平之第二表面22b；至少一穿孔220，係形成於該封裝膠體22中且貫通該封裝膠體22；空心之導電通孔25，係形成於該穿孔220中；線路層26，係形成於該半導體元件20之主動面20a與該封裝膠體22之第一表面22a上，且該線路層26係電性連接該空心之導電通孔25；以及第一絕緣保護層27，係形成於該線路層26上，且該第一絕緣保護層27係填入該空心之導電通孔25內。
所述之半導體封裝件2,2’，復包括晶種層23，係形成於該線路層26與封裝膠體22之間、線路層26與半導體元件20之間及空心之導電通孔25與封裝膠體22之間。
於本實施例中，該第一絕緣保護層27可為乾膜，且該第一絕緣保護層27具有外露部分該線路層26之複數第一開孔270，且該半導體封裝件2,2’復包括導電元件28，係形成於該第一開孔270中，以電性連接該線路層26。
所述之半導體封裝件2’，復包括由介電層290、導電盲孔291與第二線路層292所組成之線路重佈層29，係形成於該封裝膠體22之第二表面22b上；以及具有複數第二 開孔270’之第二絕緣保護層27’，係形成於該線路重佈層29上，以外露出部份之該第二線路層292，俾使該半導體封裝件2’可藉由該導電元件28電性連接外露之該線路層26與該第二線路層292，以形成3D立體封裝件(如第2I’圖所示)。
綜上所述，本發明之半導體封裝件及其製法，主要藉由先於封裝膠體中形成穿孔，然後一次性地形成導電通孔與線路層，省略傳統半導體封裝件中先形成絕緣保護層之重佈線路製程，再者，本發明能避免形成過載，因此可省略CMP製程，故能有效節省製程步驟，以大幅提升能應用於立體封裝之晶圓級封裝件之生產效率及節省成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟知本領域技術之人員均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,2,2’‧‧‧半導體封裝件
10,20‧‧‧半導體元件
12,22‧‧‧封裝膠體
120,220‧‧‧穿孔
15‧‧‧導電通孔
16‧‧‧介電層
17‧‧‧線路層
18‧‧‧絕緣保護層
20a‧‧‧主動面
20b‧‧‧非主動面
201‧‧‧電性接觸墊
21‧‧‧承載件
21’‧‧‧第二承載件
22a‧‧‧第一表面
22b‧‧‧第二表面
23‧‧‧晶種層
24‧‧‧圖案化阻層
25‧‧‧空心之導電通孔
26‧‧‧線路層
27‧‧‧第一絕緣保護層
270‧‧‧第一開孔
27’‧‧‧第二絕緣保護層
270’‧‧‧第二開孔
28‧‧‧導電元件
29‧‧‧線路重佈層
290‧‧‧介電層
291‧‧‧導電盲孔
292‧‧‧第二線路層
第1A至1C圖係為習知半導體封裝件之製法之剖面示意圖；以及第2A至2I’圖係為本發明之半導體封裝件之製法之剖面示意圖；其中，第2A至2H圖係為第一實施例，第2H’至2I’圖係為另一實施例。
20‧‧‧半導體元件
20a‧‧‧主動面
20b‧‧‧非主動面
201‧‧‧電性接觸墊
21‧‧‧承載件
22‧‧‧封裝膠體
22a‧‧‧第一表面
22b‧‧‧第二表面
23‧‧‧晶種層
25‧‧‧空心之導電通孔
26‧‧‧線路層
27‧‧‧第一絕緣保護層
270‧‧‧第一開孔

Claims (20)

  1. 一種半導體封裝件之製法，係包括：將具有主動面與非主動面之半導體元件以該非主動面接置於承載件上；形成封裝膠體於該承載件上，以包覆該半導體元件之側面，其中，該封裝膠體具有第一表面與相對之第二表面；形成貫通該封裝膠體之至少一穿孔；形成空心之導電通孔於該穿孔中，且同時形成線路層於該外露之半導體元件之主動面與該封裝膠體之第一表面上；形成第一絕緣保護層於該線路層上，且該第一絕緣保護層係填入該空心之導電通孔內；以及移除該承載件。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該封裝膠體之第一表面係與該半導體元件之主動面齊平。
  3. 如申請專利範圍第1項所述之半導體封裝件之製法，於形成貫通該封裝膠體之至少一穿孔後，復包括形成圖案化阻層於該半導體元件之主動面與該封裝膠體之第一表面上，並外露出部分該半導體元件之主動面與該封裝膠體之第一表面，再於形成空心之導電通孔於該穿孔中及形成線路層於該外露之半導體元件之主動面與該封裝膠體之第一表面上之後，移除該圖案化阻 層。
  4. 如申請專利範圍第3項所述之半導體封裝件之製法，其中，於形成貫通該封裝膠體之至少一穿孔後，復包括於形成圖案化阻層之前，先於該半導體元件之主動面與該封裝膠體之第一表面上及該穿孔中形成晶種層。
  5. 如申請專利範圍第4項所述之半導體封裝件之製法，其中，形成該晶種層之材料係為銅。
  6. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，形成該穿孔之方式係為雷射鑽孔。
  7. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，形成該線路層之材料係為銅。
  8. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該第一絕緣保護層係為乾膜。
  9. 如申請專利範圍第8項所述之半導體封裝件之製法，係以壓合之方式將該乾膜壓入該空心之導電通孔內。
  10. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，於形成該第一絕緣保護層於該線路層上之後，在移除該承載件之前，復包括於該第一絕緣保護層上形成複數第一開孔，以外露部分之該線路層。
  11. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，於該第一絕緣保護層上形成該複數第一開孔之後，復包括於該第一開孔中形成導電元件。
  12. 如申請專利範圍第11項所述之半導體封裝件之製法， 其中，該導電元件係為銲錫凸塊或銅柱。
  13. 如申請專利範圍第10項所述之半導體封裝件之製法，其中，於於該第一絕緣保護層上形成複數第一開孔之後，復包括：於該封裝膠體之第二表面上形成線路重佈層；以及於該線路重佈層上形成具有複數第二開孔之第二絕緣保護層。
  14. 一種半導體封裝件，係包括：半導體元件，係具有相對之主動面與非主動面；封裝膠體，係包覆該半導體元件之側面，且該封裝膠體具有第一表面以及相對之第二表面；至少一穿孔，係形成於該封裝膠體中且貫通該封裝膠體；空心之導電通孔，係形成於該穿孔中；線路層，係形成於該半導體元件之主動面與該封裝膠體之第一表面上，且該線路層係電性連接該空心之導電通孔；以及第一絕緣保護層，係形成於該線路層上，且該第一絕緣保護層係填入該空心之導電通孔內。
  15. 如申請專利範圍第14項所述之半導體封裝件，其中，該封裝膠體之第一表面係與該半導體元件之主動面齊平。
  16. 如申請專利範圍第14項所述之半導體封裝件，其中， 該封裝膠體之第二表面係與該半導體元件之非主動面齊平。
  17. 如申請專利範圍第14項所述之半導體封裝件，復包括晶種層，係形成於該線路層與封裝膠體之間、線路層與半導體元件之間及空心之導電通孔與封裝膠體之間。
  18. 如申請專利範圍第14項所述之半導體封裝件，其中，該第一絕緣保護層係為乾膜。
  19. 如申請專利範圍第14項所述之半導體封裝件，其中，該第一絕緣保護層具有外露部分該線路層之複數第一開孔，且該半導體封裝件復包括導電元件，係形成於該第一開孔中，以電性連接該線路層。
  20. 如申請專利範圍第14項所述之半導體封裝件，復包括線路重佈層，係形成於該封裝膠體之第二表面上；以及具有複數第二開孔之第二絕緣保護層，係形成於該線路重佈層上。
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