TW201911501A - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
- Publication number
- TW201911501A TW201911501A TW106125280A TW106125280A TW201911501A TW 201911501 A TW201911501 A TW 201911501A TW 106125280 A TW106125280 A TW 106125280A TW 106125280 A TW106125280 A TW 106125280A TW 201911501 A TW201911501 A TW 201911501A
- Authority
- TW
- Taiwan
- Prior art keywords
- packaging
- fan
- redistribution structure
- electronic component
- electronic
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
一種電子封裝件及其製法,係形成一具複數封裝單元之堆疊結構,並於該堆疊結構中形成至少一電性連接各該封裝單元之導電柱,以透過該導電柱達到跳接線路及縮短導通線路的路徑之目的,並能減少佈線所需的線路層之數量與佈線長度。
Description
本發明係有關一種封裝技術,尤指一種堆疊型電子封裝件及其製法。
由於電子產業的蓬勃發展,大部分的電子產品均不斷朝小型化、輕量化和高速化的目標邁進,其中更有不少電子產品需將複數晶片整合在一起,以達到小型化或高速化的目標。
習知多晶片封裝構造已有許多型態,為達到較小表面接合面積,一般常見的多晶片模組封裝(Multi-Chip Module,簡稱MCM),會將多顆晶片並列置放在一載體上,待模壓及整平後,再形成重佈線路層。另外,亦有將複數晶片堆疊之立體態樣。
第1圖係為習知半導體封裝件1之剖面示意圖。如第1圖所示,該半導體封裝件1係包含一線路板10、堆疊設於該線路板10上之半導體晶片11、射頻晶片12與控制晶片13,且該半導體晶片11、射頻晶片12與控制晶片13以複數銲線14電性連接至該線路板10,並以封裝膠體16包 覆該半導體晶片11、射頻晶片12與控制晶片13。
惟,習知半導體封裝件1中,由於該些銲線14之製程限制,使該半導體封裝件1之整體高度難以降低,故該半導體封裝件1無法符合微小化之需求。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑒於上述習知技術之缺失,本發明提供一種電子封裝件,係包括:一具複數封裝單元之堆疊結構,其中,各該封裝單元係包含封裝膠體、埋設於該封裝膠體中之電子元件、及設於該封裝膠體上並電性連接該電子元件之扇出型線路重佈結構,且該扇出型線路重佈結構係包括至少一絕緣部與結合該絕緣部之線路層;以及至少一導電柱,係同時貫穿該複數封裝單元之扇出型線路重佈結構與封裝膠體,使該導電柱至少電性連接兩該線路層,且該導電柱之周面直接接觸該複數封裝單元之扇出型線路重佈結構與封裝膠體。
本發明復提供一種電子封裝件之製法,係包括:形成一具複數封裝單元之堆疊結構,其中,各該封裝單元係包含封裝膠體、埋設於該封裝膠體中之電子元件、及設於該封裝膠體上並電性連接該電子元件之扇出型線路重佈結構,且該扇出型線路重佈結構係包括至少一絕緣部與結合該絕緣部之線路層;形成至少一連通該具複數封裝單元之堆疊結構之穿孔;以及形成導電材於該穿孔中以作為導電 柱,且該導電柱同時貫穿該複數封裝單元之扇出型線路重佈結構與封裝膠體,使該導電柱至少電性連接兩該線路層,且該導電柱之周面直接接觸該複數封裝單元之扇出型線路重佈結構與封裝膠體。
前述之電子封裝件及其製法中,至少兩該封裝單元之厚度不同。
前述之電子封裝件及其製法中,至少兩該封裝單元之電子元件之尺寸不同。
前述之電子封裝件及其製法中,該導電體(或該穿孔)係依序貫穿該些封裝單元之扇出型線路重佈結構與封裝膠體。
前述之電子封裝件及其製法中,該導電柱(或穿孔)係呈現類錐狀。
前述之電子封裝件之製法中,該封裝單元之製程係包括:置放電子元件於承載件上,其中,該電子元件具有相對之作用面與非作用面,並以該作用面接置該承載件;形成封裝膠體於該承載件上並包覆該電子元件;移除該承載件以外露出該電子元件之作用面;以及於該封裝膠體與該電子元件之作用面上形成電性連接該電子元件之扇出型線路重佈結構。
前述之電子封裝件之製法中,形成該具複數封裝單元之堆疊結構之製程係包括:於該扇出型線路重佈結構上置放另一電子元件,其中該另一電子元件具有相對之作用面與非作用面,並以該非作用面接置該扇出型線路重佈結 構;形成另一封裝膠體於該扇出型線路重佈結構上並包覆該另一電子元件;以及於該另一封裝膠體與該另一電子元件之作用面上形成電性連接該另一電子元件之另一扇出型線路重佈結構。
由上可知,本發明之電子封裝件及其製法,主要藉由該穿孔貫穿該些封裝單元,使單一該導電柱可選擇性電性連接各該封裝單元之扇出型線路重佈結構之線路層,故本發明之電子封裝件不僅能達到跳接線路之目的,且能縮短導通線路的路徑,並能有效減少佈線所需的線路層之數量與佈線長度。
再者,相較於習知技術之打線方式,本發明之電子封裝件,其導電柱之延伸長度至多等於該些封裝單元之堆疊高度總和,因而無需考量習知銲線之弧高,進而有效降低整體高度。
1‧‧‧半導體封裝件
10‧‧‧線路板
11‧‧‧半導體晶片
12‧‧‧射頻晶片
13‧‧‧控制晶片
14‧‧‧銲線
16‧‧‧封裝膠體
2‧‧‧電子封裝件
2a‧‧‧封裝單元
20‧‧‧承載件
200‧‧‧黏著層
21‧‧‧電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧電極墊
22‧‧‧封裝膠體
22a‧‧‧第一表面
22b‧‧‧第二表面
23‧‧‧扇出型線路重佈結構
230‧‧‧絕緣部
231‧‧‧線路層
24,34,34’‧‧‧導電柱
24c,34c‧‧‧周面
240,340,340’‧‧‧穿孔
25‧‧‧導電元件
9‧‧‧支撐板
S‧‧‧切割路徑
第1圖係為習知半導體封裝件之剖面示意圖;第2A至2G圖係為本發明之電子封裝件之製法的剖面示意圖;第3A及3B圖係為對應第2F圖之其它實施例之局部剖面示意圖;以及第4A及4B圖係為對應第2F圖之不同實施例之局部上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方 式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示,提供一承載件20,且置放複數電子元件21於該承載件20上。
於本實施例中,該承載件20係為如玻璃之半導體材質之圓形板體,其上以塗佈方式形成有一黏著層200或離形層,以供該些電子元件21設於該黏著層200或離形層上。
再者,該電子元件21係為主動元件、被動元件或其二者組合,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於本實施例中,該電子元件21例如為半導體晶片,其具有相對之作用面21a與非作用面 21b,該作用面21a具有複數電極墊210,且該電子元件21以其作用面21a設著於該黏著層200或離形層上。
如第2B圖所示,形成一封裝膠體22於該承載件20之黏著層200或離形層上,以包覆該電子元件21。
於本實施例中,該封裝膠體22係具有相對之第一表面22a與第二表面22b,且該封裝膠體22係以其第一表面22a結合該承載件20之黏著層200或離形層。
再者,該封裝膠體22係如環氧樹脂或其它適當材質,其可用壓合(lamination)或模壓(molding)之方式形成。
又,可依需求進行整平製程,使該電子元件21之非作用面21b外露於該封裝膠體22之第二表面22b。例如,該整平製程係採用研磨方式移除該封裝膠體22之材質,且可依需求移除該電子元件21之非作用面21b之部分材質。
如第2C圖所示,移除該承載件20及該黏著層200或離形層,以外露出該封裝膠體22之第一表面22a與該電子元件21之作用面21a。
於本實施例中,該封裝膠體22之第一表面22a齊平該電子元件21之作用面21a,該封裝膠體22之第二表面22b齊平該電子元件21之非作用面21b。
如第2D圖所示,藉由線路重佈層(redistribution layer,簡稱RDL)之製程,形成一扇出型(fan out)線路重佈結構(RDL)23於該封裝膠體22之第一表面22a與該電子元件21之作用面21a上,使該扇出型線路重佈結構23電性連接該電子元件21之電極墊210,以製成一封裝單元2a。
於本實施例中,一般線路重佈結構(RDL)之佈設係相對晶片定義有扇入(fan in)與扇出之兩種型式。具體地,縮小晶片線路規格(線寬/線距)之佈線係為扇入型,且放大晶片線路規格(線寬/線距)之佈線係為扇出型。
再者,該扇出型線路重佈結構23係包含至少一絕緣部230與至少一結合該絕緣部230之線路層231。例如,形成該線路層231之材質係為銅,且形成該絕緣部230之材質係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等之介電材。
如第2E圖所示,將前述封裝單元2a置於一支撐板9上,並參照前述製程,重覆於該扇出型線路重佈結構23上設置另一電子元件、形成另一封裝膠體及另一扇出型線路重佈結構,最終於該支撐板9上形成具複數封裝單元2a之堆疊結構,之後,形成複數連通該些封裝單元2a之穿孔240。
於本實施例中,該些封裝單元2a係以相同置放方向相互堆疊。例如,各該封裝單元2a之封裝膠體22之第二表面22b朝下,而該扇出型線路重佈結構23朝上。
此外,至少兩該封裝單元2a之厚度不同,且至少兩該封裝單元2a之電子元件21之尺寸不同。然而,該些封裝單元2a之厚度可依需求相同或不同,且嵌埋於該些封裝單元2a內之電子元件之數量、功能、尺寸及類型亦可依需求相同或不同,而可因應實際需求變化設置。
再者,該些穿孔240係自預定位置以蝕刻、機鑽或雷射等方式進行鑽孔製程,依序貫穿各該封裝單元2a之扇出型線路重佈結構23與封裝膠體22,而不會貫穿該電子元件21。應可理解地,由於最下方封裝單元2a之封裝膠體22中並無電性功能,故該些穿孔240可選擇性延伸(如第2E圖所示)或不延伸(圖未示)至最下方封裝單元2a之封裝膠體22中。
如第2F圖所示,形成導電材於該穿孔240中以作為導電柱24,且單一該導電柱24同時貫穿該複數封裝單元2a之扇出型線路重佈結構23與封裝膠體22,使該單一導電柱24至少電性連接兩該線路層231,且該導電柱24之周面24c直接接觸該複數封裝單元之扇出型線路重佈結構23與封裝膠體22。
於本實施例中,該導電柱24之材質係為導電膠、如銅之金屬材或銲錫材。
再者,該導電柱24可依需求未接觸該線路層231(如第4A圖所示)或接觸該線路層231(如第4B圖所示),以供選擇欲電性連接之線路層231,藉此達到跳接之目的。
如第2G圖所示,沿如第2F圖所示之切割路徑S進行切單製程,且移除該支撐板9,以獲取複數個電子封裝件2,且單一電子封裝件2係將複數電子元件21立體堆疊化整合為三維(3D)堆疊型式。
於本實施例中,可形成複數如銲球之導電元件25於最外側之封裝單元2a之線路層231上,俾供後續接置如電路 板、封裝結構或其它電子裝置(圖略)。
再者,於其它實施例中,如第3A及3B圖所示之導電柱34,34’,依設計需求與導電功效的選擇,該穿孔340,340’可以呈現類錐狀,以令孔端為上大下小(如第3A圖所示)或上小下大(如第3B圖所示)。
因此,本發明之製法係藉由該穿孔240,340,340’同時貫穿不同的封裝單元2a,使單一該導電柱24,34,34’可選擇性電性連接該封裝單元2a之扇出型線路重佈結構23之線路層231,故本發明之電子封裝件2不僅能達到跳接線路之目的,且能縮短導通線路的路徑,並能有效減少佈線所需的線路層之數量與佈線長度。
再者,相較於習知技術之打線方式,本發明之電子封裝件2,其導電柱24,34,34’之延伸長度至多等於該些封裝單元2a之堆疊高度總和,因而無需考量習知銲線之弧高,進而有效降低整體高度。
本發明亦提供一種電子封裝件2,其包括:複數相堆疊之封裝單元2a、以及至少一貫穿各該封裝單元2a之導電柱24,34,34’。
所述之封裝單元2a係包含一封裝膠體22、至少一埋設於該封裝膠體22中之電子元件21、及一設於該封裝膠體23上並電性連接該電子元件21之扇出型線路重佈結構23,且該扇出型線路重佈結構23係包括至少一絕緣部230與結合該絕緣部230之線路層231。
所述之導電柱24,34,34’係同時貫穿該複數封裝單元 2a之扇出型線路重佈結構23與封裝膠體22,使該導電柱24,34,34’至少電性連接兩該線路層231,且該導電柱24,34,34’之周面24c,34c直接接觸該複數封裝單元2a之扇出型線路重佈結構23與封裝膠體22。
於一實施例中,至少兩該封裝單元2a之厚度不同。
於一實施例中,至少兩該封裝單元2a之電子元件21之尺寸不同。
於一實施例中,該導電柱24,34,34’係依序延伸經過該些封裝單元2a之扇出型線路重佈結構23與封裝膠體22。
於一實施例中,該導電柱34,34’係呈現類錐狀。
綜上所述,本發明之電子封裝件及其製法,係藉由該導電柱延伸經過各該封裝單元,以電性連接各該封裝單元之扇出型線路重佈結構,使本發明不僅能達到跳接線路之目的,且能縮短導通線路的路徑,並能有效減少佈線所需的線路層數量與佈線長度, 再者,由於本發明之導電柱之延伸長度至多等於該些封裝單元之堆疊高度總和,故本發明之電子封裝件能有效降低其整體高度。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
Claims (12)
- 一種電子封裝件,係包括:一具複數封裝單元之堆疊結構,其中,各該封裝單元係包含封裝膠體、埋設於該封裝膠體中之電子元件、及設於該封裝膠體上並電性連接該電子元件之扇出型線路重佈結構,且該扇出型線路重佈結構係包括至少一絕緣部與結合該絕緣部之線路層;以及至少一導電柱,係同時貫穿該複數封裝單元之扇出型線路重佈結構與封裝膠體,使該導電柱至少電性連接兩該線路層,且該導電柱之周面直接接觸該複數封裝單元之扇出型線路重佈結構與封裝膠體。
- 如申請專利範圍第1項所述之電子封裝件,其中,至少兩該封裝單元之厚度不同。
- 如申請專利範圍第1項所述之電子封裝件,其中,至少兩該封裝單元之電子元件之尺寸不同。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導電柱係依序延伸經過該些封裝單元之扇出型線路重佈結構與封裝膠體。
- 如申請專利範圍第1項所述之電子封裝件,其中,該導電柱係呈現類錐狀。
- 一種電子封裝件之製法,係包括:形成一具複數封裝單元之堆疊結構,其中,各該封裝單元係包含封裝膠體、埋設於該封裝膠體中之電子元件、及設於該封裝膠體上並電性連接該電子元件之扇 出型線路重佈結構,且該扇出型線路重佈結構係包括至少一絕緣部與結合該絕緣部之線路層;形成至少一連通該具複數封裝單元之堆疊結構之穿孔;以及形成導電材於該穿孔中以作為導電柱,且該導電柱同時貫穿該複數封裝單元之扇出型線路重佈結構與封裝膠體,使該導電柱至少電性連接兩該線路層,且該導電柱之周面直接接觸該複數封裝單元之扇出型線路重佈結構與封裝膠體。
- 如申請專利範圍第6項所述之電子封裝件之製法,其中,至少兩該封裝單元之厚度不同。
- 如申請專利範圍第6項所述之電子封裝件之製法,其中,至少兩該封裝單元之電子元件之尺寸不同。
- 如申請專利範圍第6項所述之電子封裝件之製法,其中,該些穿孔係依序貫穿該些封裝單元之扇出型線路重佈結構與封裝膠體。
- 如申請專利範圍第6項所述之電子封裝件之製法,其中,該穿孔係呈現類錐狀。
- 如申請專利範圍第6項所述之電子封裝件之製法,其中,該封裝單元之製程係包括:置放電子元件於承載件上,其中,該電子元件具有相對之作用面與非作用面,並以該作用面接置該承載件;形成封裝膠體於該承載件上並包覆該電子元件; 移除該承載件以外露出該電子元件之作用面;以及於該封裝膠體與該電子元件之作用面上形成電性連接該電子元件之扇出型線路重佈結構。
- 如申請專利範圍第6項所述之電子封裝件之製法,其中,形成該具複數封裝單元之堆疊結構之製程係包括:於該扇出型線路重佈結構上置放另一電子元件,其中該另一電子元件具有相對之作用面與非作用面,並以該非作用面接置該扇出型線路重佈結構;形成另一封裝膠體於該扇出型線路重佈結構上並包覆該另一電子元件;以及於該另一封裝膠體與該另一電子元件之作用面上形成電性連接該另一電子元件之另一扇出型線路重佈結構。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106125280A TWI622143B (zh) | 2017-07-27 | 2017-07-27 | 電子封裝件及其製法 |
CN201710685224.4A CN109309068A (zh) | 2017-07-27 | 2017-08-11 | 电子封装件及其制法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106125280A TWI622143B (zh) | 2017-07-27 | 2017-07-27 | 電子封裝件及其製法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI622143B TWI622143B (zh) | 2018-04-21 |
TW201911501A true TW201911501A (zh) | 2019-03-16 |
Family
ID=62640054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106125280A TWI622143B (zh) | 2017-07-27 | 2017-07-27 | 電子封裝件及其製法 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN109309068A (zh) |
TW (1) | TWI622143B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111525290A (zh) * | 2020-04-30 | 2020-08-11 | 番禺得意精密电子工业有限公司 | 基板及基板的制作方法 |
CN111816628B (zh) * | 2020-09-11 | 2020-12-04 | 甬矽电子(宁波)股份有限公司 | 半导体封装结构和封装方法 |
CN111933590B (zh) * | 2020-09-11 | 2021-01-01 | 甬矽电子(宁波)股份有限公司 | 封装结构和封装结构制作方法 |
CN112768437B (zh) * | 2021-04-08 | 2021-06-18 | 甬矽电子(宁波)股份有限公司 | 多层堆叠封装结构和多层堆叠封装结构的制备方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100539051C (zh) * | 2006-11-28 | 2009-09-09 | 全懋精密科技股份有限公司 | 半导体元件埋入承载板的叠接结构及其制法 |
KR101465948B1 (ko) * | 2007-12-27 | 2014-12-10 | 삼성전자주식회사 | 웨이퍼 레벨 스택 패키지 및 웨이퍼 레벨 스택 패키지 제조방법 |
TWI491017B (zh) * | 2013-04-25 | 2015-07-01 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
CN103887291B (zh) * | 2014-04-02 | 2017-01-04 | 华进半导体封装先导技术研发中心有限公司 | 三维扇出型PoP封装结构及制造工艺 |
US9589936B2 (en) * | 2014-11-20 | 2017-03-07 | Apple Inc. | 3D integration of fanout wafer level packages |
US9601471B2 (en) * | 2015-04-23 | 2017-03-21 | Apple Inc. | Three layer stack structure |
-
2017
- 2017-07-27 TW TW106125280A patent/TWI622143B/zh active
- 2017-08-11 CN CN201710685224.4A patent/CN109309068A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
TWI622143B (zh) | 2018-04-21 |
CN109309068A (zh) | 2019-02-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI587412B (zh) | 封裝結構及其製法 | |
TWI555098B (zh) | 電子封裝件及其製法 | |
TW201737442A (zh) | 薄型晶片堆疊封裝構造及其製造方法 | |
TWI569390B (zh) | 電子封裝件及其製法 | |
TWI698966B (zh) | 電子封裝件及其製法 | |
TW201933573A (zh) | 電子封裝件及其製法 | |
TWI622143B (zh) | 電子封裝件及其製法 | |
TWI611542B (zh) | 電子封裝結構及其製法 | |
TWI594382B (zh) | 電子封裝件及其製法 | |
US11382214B2 (en) | Electronic package, assemble substrate, and method for fabricating the assemble substrate | |
TW201729359A (zh) | 電子封裝件及其製法 | |
TWI491017B (zh) | 半導體封裝件及其製法 | |
US11923337B2 (en) | Carrying substrate, electronic package having the carrying substrate, and methods for manufacturing the same | |
TW201814854A (zh) | 電子封裝件及其製法 | |
TWI802726B (zh) | 電子封裝件及其承載基板與製法 | |
TWI600132B (zh) | 電子封裝件及其製法 | |
TWI612627B (zh) | 電子封裝件及其製法 | |
TW201843794A (zh) | 封裝結構及其製作方法 | |
TWI614844B (zh) | 封裝堆疊結構及其製法 | |
TWM521807U (zh) | 封裝結構及其中介板 | |
CN106469706B (zh) | 电子封装件及其制法 | |
TWI570856B (zh) | 封裝結構及其製法 | |
TWI839645B (zh) | 電子封裝件及其製法 | |
TWI767770B (zh) | 電子封裝件及其製法 | |
TWI760227B (zh) | 電子封裝件及其製法 |