TW201933573A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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Publication number
TW201933573A
TW201933573A TW107103221A TW107103221A TW201933573A TW 201933573 A TW201933573 A TW 201933573A TW 107103221 A TW107103221 A TW 107103221A TW 107103221 A TW107103221 A TW 107103221A TW 201933573 A TW201933573 A TW 201933573A
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Taiwan
Prior art keywords
circuit structure
electronic component
conductive
electronic
layer
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TW107103221A
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English (en)
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TWI643307B (zh
Inventor
黃陳昱
鄭子企
林長甫
黃公敦
戴瑞豐
馬伯豪
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矽品精密工業股份有限公司
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Priority to TW107103221A priority Critical patent/TWI643307B/zh
Priority to CN201810296185.3A priority patent/CN110098169A/zh
Priority to US15/971,534 priority patent/US10741500B2/en
Application granted granted Critical
Publication of TWI643307B publication Critical patent/TWI643307B/zh
Publication of TW201933573A publication Critical patent/TW201933573A/zh
Priority to US16/919,433 priority patent/US11289346B2/en

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

一種電子封裝件及其製法，係於嵌埋有第一電子元件與複數導電柱之包覆層上形成線路結構，並於該線路結構上接置第二電子元件，藉由該線路結構二側配置有相對之第一電子元件與第二電子元件，以使該電子封裝件具有多功能、高效能之優點。

Description

電子封裝件及其製法
本發明係有關一種封裝製程，特別是關於一種配置多晶片之電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足電子封裝件微型化(miniaturization)的封裝需求，係發展出晶圓級封裝(Wafer Level Packaging，簡稱WLP)技術。
第1A至1E圖係為習知採用晶圓級封裝技竹術之半導體封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離形膠層(thermal release tape)100於一承載件10上。
接著，置放複數半導體元件11於該熱化離形膠層100上，該些半導體元件11具有相對之作用面11a與非作用面11b，各該作用面11a上具有複數電極墊110，且各該作用面11a黏著於該熱化離形膠層100上。
如第1B圖所示，形成一封裝膠體14於該熱化離形膠層100上，以包覆該半導體元件11。
如第1C圖所示，烘烤該封裝膠體14以硬化該熱化離形膠層100，進而移除該熱化離形膠層100與該承載件10，以外露出該半導體元件11之作用面11a。
如第1D圖所示，形成一線路結構16於該封裝膠體14與該半導體元件11之作用面11a上，令該線路結構16電性連接該電極墊110。接著，形成一絕緣保護層18於該線路結構16上，且該絕緣保護層18外露該線路結構16之部分表面，以供結合如銲球之導電元件17。
如第1E圖所示，沿如第1D圖所示之切割路徑L進行切單製程，以獲取複數個半導體封裝件1。
惟，習知半導體封裝件1，僅於該線路結構16單側設置有半導體元件11，使該半導體封裝件1之功能及效能受限，故限制終端電子產品之功能及效能。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明提供一種電子封裝件，係包括：包覆層，係具有相對之第一表面及第二表面；第一電子元件，係嵌埋於該包覆層中；複數導電柱，係嵌埋於該包覆層中；第一線路結構，係設於該包覆層之第一表面上並電性連接該導電柱；複數第一導電元件，係設於該第一線路結構上；第二線路結構，係設於該包覆層之第二表面上並電性連接該導電柱與該第一電子元件；以及第二電子元件，係設於該第二線路結構上並電性連接該 第二線路結構。
本發明復提供一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之包覆層，其嵌埋有第一電子元件與複數導電柱，且於該第一表面上設有電性連接該導電柱之第一線路結構，並於該第一線路結構上設有複數第一導電元件；形成第二線路結構於該包覆層之第二表面上，且令該第二線路結構電性連接該導電柱與該第一電子元件；以及設置第二電子元件於該第二線路結構上，且令該第二電子元件電性連接該第二線路結構。
前述之電子封裝件及其製法中，該導電柱之端面係齊平該包覆層之第一表面或第二表面。
前述之電子封裝件及其製法中，該第一電子元件之表面係齊平該包覆層之第一表面或第二表面。
前述之電子封裝件及其製法中，該第一線路結構係未電性連接該第一電子元件。
前述之電子封裝件及其製法中，該第二電子元件係藉由第二導電元件設於該第二線路結構上，且於該第二電子元件與該第二線路結構之間可形成包覆該第二導電元件之底膠。
前述之電子封裝件及其製法中，復包括形成封裝層於該第二線路結構上，以包覆該第二電子元件。
前述之電子封裝件及其製法中，該第一電子元件係藉由導電體電性連接該第二線路結構。
前述之電子封裝件及其製法中，復包括於設置該第二 電子元件前，設置封裝基板上於該些第一導電元件上。
由上可知，本發明之電子封裝件及其製法中，主要藉由形成該第二線路結構以接置該第二電子元件，故相較於習知技術，本發明之電子封裝件係配置有相對位於上、下位置之第一電子元件與第二電子元件，使該電子封裝件具有多功能、高效能之優點。
1‧‧‧半導體封裝件
10‧‧‧承載件
100‧‧‧熱化離形膠層
11‧‧‧半導體元件
11a,20a‧‧‧作用面
11b,20b‧‧‧非作用面
110,200‧‧‧電極墊
14‧‧‧封裝膠體
16‧‧‧線路結構
17‧‧‧導電元件
18,211‧‧‧絕緣保護層
2,3,4‧‧‧電子封裝件
20‧‧‧第一電子元件
21,31‧‧‧第一線路結構
210,310‧‧‧第一線路重佈層
22‧‧‧第二線路結構
220‧‧‧第二線路重佈層
221‧‧‧絕緣層
23‧‧‧包覆層
23a‧‧‧第一表面
23b‧‧‧第二表面
24‧‧‧導電柱
24a‧‧‧第一端
24b‧‧‧第二端
25,35‧‧‧第一導電元件
26‧‧‧第二電子元件
27‧‧‧第二導電元件
28‧‧‧封裝層
29‧‧‧底膠
30‧‧‧導電體
300‧‧‧黏著層
301‧‧‧保護膜
31a‧‧‧第一側
31b‧‧‧第二側
311‧‧‧第一絕緣層
32‧‧‧凸塊底下金屬層
4a‧‧‧封裝組合
40‧‧‧封裝基板
400‧‧‧電性接觸墊
44‧‧‧強固件
8a‧‧‧第一承載件
8b‧‧‧第二承載件
80,82,90‧‧‧板體
81,83,91‧‧‧結合層
9‧‧‧承載件
L‧‧‧切割路徑
第1A至1E圖係為習知半導體封裝件之製法的剖面示意圖；第2A至2F圖係為本發明之電子封裝件之製法之第一實施例之剖視示意圖；第3A至3D圖係為本發明之電子封裝件之製法之第二實施例之剖視示意圖；以及第4A至4D圖係為本發明之電子封裝件之製法之第三實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝件2之製法之第一實施例的剖視示意圖。
如第2A圖所示，提供一第一承載件8a，且形成複數導電柱24於該第一承載件8a上，並設置至少一第一電子元件20於該第一承載件8a上。接著，形成一包覆層23於該第一承載件8a上，以令該包覆層23包覆各該導電柱24與該第一電子元件20。
於本實施例中，該第一承載件8a係包含如半導體材、介電材、陶瓷材、玻璃或金屬材之板體80，但不限於此，且該第一承載件8a之尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrat)。例如，該第一承載件8a可具有如離型膜或膠材之結合層81，且該結合層81以塗佈或貼合方式形成於該板體80上。
再者，該第一電子元件20係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第一電子元件20係為半導體晶片，其具有相對之作用面20a與非作用面 20b，該作用面20a上具有複數電極墊200，且該第一電子元件20係以其作用面20a結合於該結合層81上。
又，該包覆層23具有相對之第一表面23a及第二表面23b，且該導電柱24具有相對之第一端24a與第二端24b，使該包覆層23之第二表面23b結合至該第一承載件8a之結合層81上，而該些導電柱24之第一端24a係外露於該包覆層23之第一表面23a。具體地，該包覆層23係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(expoxy)之封裝膠體或封裝材(molding compound)。例如，該包覆層23之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression imolding)等方式形成於該結合層81上。
另外，可進行整平製程，使該第一電子元件20之非作用面20b與該些導電柱24之第一端24a齊平該包覆層23之第一表面23a。例如，藉由研磨方式，移除該導電柱24之部分材質、該第一電子元件20之部分材質與該包覆層23之部分材質。
如第2B圖所示，形成一第一線路結構21於該包覆層23之第一表面23a與該第一電子元件20之非作用面20b上，且該第一線路結構21係電性連接該些導電柱24，再形成複數第一導電元件25於該第一線路結構21上。
於本實施例中，該第一線路結構21係包括至少一電性連接該些導電柱24之第一端24a的第一線路重佈層 (redistribution layer，簡稱RDL)210。例如，形成該第一線路重佈層210之材質係為銅。
再者，該第一線路結構21還可包括至少一用以佈設該第一線路重佈層210之絕緣層(圖略)，且形成該絕緣層之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。應可理解地，藉由該絕緣層可形成多層該第一線路重佈層210。進一步，該第一線路結構21還可包括一如防焊層之絕緣保護層211，並令該第一導電元件25外露出該絕緣保護層211。
又，於一實施態樣中，該第一線路重佈層210係接觸但未電性連接該第一電子元件20之非作用面20b。
另外，該第一導電元件25係包含銲錫材料、銅柱或其它導電材，其電性連接該第一線路重佈層210。
如第2C圖所示，設置一第二承載件8b於該第一線路結構21上。接著，移除該第一承載件8a，以外露該包覆層23之第二表面23b、該些導電柱24之第二端24b與該第一電子元件20之作用面20a。
於本實施例中，該第二承載件8b係包含如半導體材、介電材、陶瓷材、玻璃或金屬材之板體82，但不限於此，且該第二承載件8b之尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrat)。
再者，該第二承載件8b復包含如離型膜或膠材之結 合層83，且該結合層83以塗佈或貼合方式形成於該板體82上，並將該結合層83壓合於該第一線路結構21上，使該些第一導電元件25嵌埋於該結合層83中。
又，該第一電子元件20之作用面20a與該些導電柱24之第二端24b係與該包覆層23之第二表面23b共平面(齊平)。
如第2D圖所示，進行線路重佈層(RDL)製程，以形成一第二線路結構22於該包覆層23之第二表面23b上，且該第二線路結構22電性連接該第一電子元件20之電極墊200與該些導電柱24之第二端24b。
於本實施例中，該第二線路結構22係包括至少一絕緣層221及設於該第二絕緣層221上之第二線路重佈層(RDL)220，且最外層之第二絕緣層221可作為防銲層，以令最外層之第二線路重佈層220外露於該防銲層。
再者，形成該第二線路重佈層220之材質係為銅，且形成該第二絕緣層221之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)之介電材。
如第2E圖所示，設置至少一第二電子元件26於該第二線路結構22上，再以封裝層28包覆該第二電子元件26。之後，移除該第二承載件8b以外露出該些第一導電元件25。
於本實施例中，該第二電子元件26係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於一實施態 樣中，該第二電子元件26係例如為圖形處理器(graphics processing unit，簡稱GPU)、高頻寬記憶體(High Bandwidth Memory，簡稱HBM)等半導體晶片，並無特別限制。
再者，該第二電子元件26係以複數如銲錫凸塊、銅凸塊之第二導電元件27電性連接該第二線路重佈層220。另該封裝層28可同時包覆該第二電子元件26與該些第二導電元件27。
又，該封裝層28係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(expoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該第二線路結構22上。應可理解地，形成該封裝層28之材質可相同或不相同該包覆層23之材質。
另外，亦可先形成底膠29於該第二電子元件26與該第二線路結構22之間以包覆該些第二導電元件27，再形成該封裝層28以包覆該底膠29與該第二電子元件26。
如第2F圖所示，進行切單製程，以製成該電子封裝件2，且於後續製程中，該電子封裝件2可透過該第一導電元件25設於一電路板(圖略)上。
因此，本發明之電子封裝件之製法之第一實施例係藉由形成該第二線路結構22，以接置該第二電子元件26，故相較於習知技術，本發明之電子封裝件2係在第二線路結構22二側配置有相對位於上、下位置之第一電子元件20 與第二電子元件26，使該電子封裝件2具有多功能、高效能之優點。
請參閱第3A至3E圖，係為本發明之電子封裝件3之製法之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於製作第一線路結構與第一導電元件之步驟順序。
如第3A圖所示，於一承載件9上結合第一線路結構31，該第一線路結構31具有相對之第一側31a與第二側31b，且該第一線路結構31之第一側31a設有複數第一導電元件35以結合至該承載件9上。接著，於該第二側31b上形成複數電性連接該第一線路結構31之導電柱24，且設置第一電子元件20於該第一線路結構31之第二側31b上。
於本實施例中，該第一線路結構31係包括至少一第一絕緣層311與一設於該第一絕緣層311上之第一線路重佈層(redistribution layer，簡稱RDL)310。例如，形成該第一線路重佈層310之材質係為銅，且形成該第一絕緣層311之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。
再者，該承載件9係包含如半導體材、介電材、陶瓷材、玻璃或金屬材之板體90，但不限於此，且該承載件9之尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrat)。例如，該承 載件9可具有如離型膜或膠材之結合層91，且該結合層91以塗佈或貼合方式形成於該板體90上，使該第一線路結構31壓合於該結合層91上，且令該些第一導電元件35嵌埋於該結合層91中。
又，該導電柱24係設於該第一線路重佈層310上並電性連接該第一線路重佈層310，且形成該導電柱24之材質係為如銅之金屬材或銲錫材。
另外，該第一電子元件20係以其非作用面20b藉由黏著層300黏固於該第一線路結構31之第二側31b上，且於作用面20a上設有一如鈍化材之保護膜301與外露出該保護膜301之複數電極墊200，另於該電極墊200上結合並電性連接複數導電體30並凸出該保護膜301。具體地，該導電體30之構造係呈現如導電線路、銲球等之圓球狀、如銅柱、銲錫凸塊等之金屬柱狀、或銲線機製作之釘狀(stud)，但不限於此。
如第3B圖所示，形成一包覆層23於該第一線路結構31之第二側31b上，以令該包覆層23包覆該第一電子元件20、該些導電體30與該些導電柱24，再藉由整平製程，使該包覆層23之第二表面23b齊平該導電柱24之第二端24b與該導電體30之端面，令該導電柱24之第二端24b與該導電體30之端面外露於該包覆層23。
於本實施例中，該包覆層23係為絕緣材，如環氧樹脂之封裝膠體，其可用壓合(lamination)或模壓(molding)之方式形成於該第一線路結構31之第二側31b上。
再者，該整平製程係藉由研磨方式，移除該導電柱24之部分材質、該導電體30之部分材質與該包覆層23之部分材質。
如第3C圖所示，形成一第二線路結構22於該包覆層23之第二表面23b上，且該第二線路結構23電性連接該些導電柱24與該導電體30。之後，將至少一第二電子元件26透過複數如銲球之第二導電元件27接置於該第二線路結構22上，並以封裝層28包覆該第二電子元件26與該第二導電元件27。
於本實施例中，該第二線路結構22可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)32於最外層之第二線路重佈層220上，以利於結合該導電元件27。
再者，亦可先形成第一實施例的底膠29於該第二電子元件26與該第二線路結構22之間以包覆該些第二導電元件27，再形成該封裝層28以包覆該底膠29與該第二電子元件26。
如第3D圖所示，移除該承載件9，以外露該些第一導電元件35。之後，進行切單製程，以獲取電子封裝件3，且於後續製程中，該電子封裝件3以其第一導電元件35設於一電路板(圖略)上。
因此，本發明之製法之第二實施例係藉由先形成該第一線路結構31與該第一導電元件35，再形成該第二線路結構22以接置該第二電子元件26，故相較於習知技術，本發明之電子封裝件3係於第二線路結構22二側配置有相 對位於上、下位置之第一電子元件20與第二電子元件26，使該電子封裝件3具有多功能、高效能之優點。
請參閱第4A至4D圖，係為本發明之電子封裝件4之製法之第三實施例的剖面示意圖。本實施例與第二實施例之差異在於新增封裝基板之製程。
如第4A圖所示，接續第3B圖之製程，形成一第二線路結構22於包覆層23之第二表面23b上，且該第二線路結構22電性連接該些導電柱24與該些導電體30。
如第4B圖所示，移除該承載件9，以外露該些第一導電元件35，並進行切單製程，以獲取封裝組合4a。
如第4C圖所示，將該封裝組合4a以第一導電元件35接置於一封裝基板40上。
於本實施例中，該封裝基板40具有複數電性接觸墊400以接合該些第一導電元件35。
再者，該封裝基板40上可依需求設置強固件44，如金屬框，以消除應力集中之問題而避免該封裝基板40發生翹曲之情況。
如第4D圖所示，藉由複數第二導電元件27接置至少一第二電子元件26於該第二線路結構22上，並以封裝層28包覆該第二電子元件26，以獲取電子封裝件4，且於後續製程中，該電子封裝件4以其封裝基板40設於一電路板(圖略)上。
於本實施例中，亦可先形成第一實施例的底膠29於該第二電子元件26與該第二線路結構22之間以包覆該些 第二導電元件27，再形成該封裝層28以包覆該底膠29與該第二電子元件26。
因此，本發明之製法之第三實施例係藉由形成第一線路結構31與該第一導電元件35以接置該封裝基板40，再形成該第二線路結構22以接置該第二電子元件26，故相較於習知技術，本發明之電子封裝件4係於第二線路結構22二側配置有相對位於上、下位置之第一電子元件20與第二電子元件26，使該電子封裝件4具有多功能、高效能之優點。
本發明復提供一種電子封裝件2,3,4，係包括：一包覆層23、至少一第一電子元件20、複數導電柱24、一第一線路結構21,31、複數第一導電元件25,35、一第二線路結構22以及至少一第二電子元件26。
所述之包覆層23係具有相對之第一表面23a及第二表面23b。
所述之第一電子元件20係嵌埋於該包覆層23中。
所述之導電柱24係嵌埋於該包覆層23中。
所述之第一線路結構21,31係設於該包覆層23之第一表面23a上並電性連接該導電柱24。
所述之第一導電元件25,35係設於該第一線路結構21,31上。
所述之第二線路結構22係設於該包覆層23之第二表面23b上並電性連接該導電柱24與該第一電子元件20。
所述之第二電子元件26係設於該第二線路結構22上 並電性連接該第二線路結構22。
於一實施例中，該導電柱24具有相對之第一端24a與第二端24b，且該第一端24a之端面係齊平該包覆層23之第一表面23a，或該第二端24b之端面係齊平該包覆層23之第二表面23b。
於一實施例中，該第一電子元件20係具有相對之作用面20a與非作用面20b，該作用面20a係齊平該包覆層23之第一表面23a，或該非作用面20b係齊平該包覆層23之第二表面23b。
於一實施例中，該第一線路結構21,31係電性連接該第一導電元件25,35。
於一實施例中，該第一線路結構21,31係未電性連接該第一電子元件20。
於一實施例中，該第一電子元件20係藉由導電體30電性連接該第二線路結構22。
於一實施例中，該第二電子元件26係藉由第二導電元件27設於該第二線路結構22上。
於一實施例中，所述之電子封裝件2,3,4復包括一封裝層28，係設於該第二線路結構22上以包覆該第二電子元件26。
於一實施例中，所述之電子封裝件4復包括一封裝基板40，係設於該些第一導電元件35上。
綜上所述，本發明之電子封裝件及其製法，係藉由形成該第二線路結構以接置該第二電子元件，故本發明之電 子封裝件係配置有相對位於上、下位置之第一電子元件與第二電子元件，使該電子封裝件具有多功能、高效能之優點。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (18)

  1. 一種電子封裝件，係包括：包覆層，係具有相對之第一表面及第二表面；第一電子元件，係嵌埋於該包覆層中；複數導電柱，係嵌埋於該包覆層中；第一線路結構，係設於該包覆層之第一表面上並電性連接該導電柱；複數第一導電元件，係設於該第一線路結構上；第二線路結構，係設於該包覆層之第二表面上並電性連接該導電柱與該第一電子元件；以及第二電子元件，係設於該第二線路結構上並電性連接該第二線路結構。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該導電柱之端面係齊平該包覆層之第一表面或第二表面。
  3. 如申請專利範圍第1項所述之電子封裝件，其中，該第一電子元件之表面係齊平該包覆層之第一表面或第二表面。
  4. 如申請專利範圍第1項所述之電子封裝件，復包括設於該第二線路結構上以包覆該第二電子元件之封裝層。
  5. 如申請專利範圍第1項所述之電子封裝件，其中，該第一線路結構係未電性連接該第一電子元件。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該第二電子元件係藉由第二導電元件設於該第二線路結構上。
  7. 如申請專利範圍第6項所述之電子封裝件，復包括設於該第二線路結構與該第二電子元件之間且包覆該第二導電元件之底膠。
  8. 如申請專利範圍第1項所述之電子封裝件，其中，該第一電子元件係藉由導電體電性連接該第二線路結構。
  9. 如申請專利範圍第1項所述之電子封裝件，復包括封裝基板，係設於該些第一導電元件上。
  10. 一種電子封裝件之製法，係包括：提供一具有相對之第一表面及第二表面之包覆層，其嵌埋有第一電子元件與複數導電柱，且於該第一表面上設有電性連接該導電柱之第一線路結構，並於該第一線路結構上設有複數第一導電元件；形成第二線路結構於該包覆層之第二表面上，且令該第二線路結構電性連接該導電柱與該第一電子元件；以及設置第二電子元件於該第二線路結構上，且令該第二電子元件電性連接該第二線路結構。
  11. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該導電柱之端面係齊平該包覆層之第一表面或第二表面。
  12. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該第一電子元件之表面係齊平該包覆層之第一表面或第二表面。
  13. 如申請專利範圍第10項所述之電子封裝件之製法，復 包括形成封裝層於該第二線路結構上，以包覆該第二電子元件。
  14. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該第一線路結構係未電性連接該第一電子元件。
  15. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該第二電子元件係藉由第二導電元件設於該第二線路結構上。
  16. 如申請專利範圍第15項所述之電子封裝件之製法，復包括形成底膠於該第二線路結構與該第二電子元件之間且包覆該第二導電元件。
  17. 如申請專利範圍第10項所述之電子封裝件之製法，其中，該第一電子元件係藉由導電體電性連接該第二線路結構。
  18. 如申請專利範圍第10項所述之電子封裝件之製法，復包括於設置該第二電子元件前，設置封裝基板於該些第一導電元件上。
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