CN110098169A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN110098169A
CN110098169A CN201810296185.3A CN201810296185A CN110098169A CN 110098169 A CN110098169 A CN 110098169A CN 201810296185 A CN201810296185 A CN 201810296185A CN 110098169 A CN110098169 A CN 110098169A
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CN
China
Prior art keywords
electronic component
packing piece
electronic
clad
preparation
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CN201810296185.3A
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English (en)
Inventor
黄陈昱
郑子企
林长甫
黄公敦
戴瑞丰
马伯豪
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN110098169A publication Critical patent/CN110098169A/zh
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

一种电子封装件及其制法，通过于嵌埋有第一电子元件与多个导电柱的包覆层上形成线路结构，并于该线路结构上接置第二电子元件，借由该线路结构二侧配置有相对的第一电子元件与第二电子元件，以使该电子封装件具有多功能、高效能的优点。

Description

电子封装件及其制法
技术领域
本发明有关一种封装制程，特别是关于一种配置多晶片的电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了满足电子封装件微型化(miniaturization)的封装需求，发展出晶圆级封装(Wafer LevelPackaging，简称WLP)技术。
图1A至图1E为现有采用晶圆级封装技术的半导体封装件1的制法的剖面示意图。
如图1A所示，形成一热化离形胶层(thermal release tape)100于一承载件10上。
接着，置放多个半导体元件11于该热化离形胶层100上，该些半导体元件11具有相对的作用面11a与非作用面11b，各该作用面11a上具有多个电极垫110，且各该作用面11a粘着于该热化离形胶层100上。
如图1B所示，形成一封装胶体14于该热化离形胶层100上，以包覆该半导体元件11。
如图1C所示，烘烤该封装胶体14以硬化该热化离形胶层100，进而移除该热化离形胶层100与该承载件10，以外露出该半导体元件11的作用面11a。
如图1D所示，形成一线路结构16于该封装胶体14与该半导体元件11的作用面11a上，令该线路结构16电性连接该电极垫110。接着，形成一绝缘保护层18于该线路结构16上，且该绝缘保护层18外露该线路结构16的部分表面，以供结合如焊球的导电元件17。
如图1E所示，沿如图1D所示的切割路径L进行切单制程，以获取多个半导体封装件1。
然而，现有半导体封装件1，仅于该线路结构16单侧设置有半导体元件11，使该半导体封装件1的功能及效能受限，故限制终端电子产品的功能及效能。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其制法，具有多功能、高效能的优点。
本发明的电子封装件，包括：包覆层，其具有相对的第一表面及第二表面；第一电子元件，其嵌埋于该包覆层中；多个导电柱，其嵌埋于该包覆层中；第一线路结构，其设于该包覆层的第一表面上并电性连接该导电柱；多个第一导电元件，其设于该第一线路结构上；第二线路结构，其设于该包覆层的第二表面上并电性连接该导电柱与该第一电子元件；以及第二电子元件，其设于该第二线路结构上并电性连接该第二线路结构。
本发明还提供一种电子封装件的制法，其包括：提供一具有相对的第一表面及第二表面的包覆层，其嵌埋有第一电子元件与多个导电柱，且于该第一表面上设有电性连接该导电柱的第一线路结构，并于该第一线路结构上设有多个第一导电元件；形成第二线路结构于该包覆层的第二表面上，且令该第二线路结构电性连接该导电柱与该第一电子元件；以及设置第二电子元件于该第二线路结构上，且令该第二电子元件电性连接该第二线路结构。
前述的电子封装件及其制法中，该导电柱的端面齐平该包覆层的第一表面或第二表面。
前述的电子封装件及其制法中，该第一电子元件的表面齐平该包覆层的第一表面或第二表面。
前述的电子封装件及其制法中，该第一线路结构未电性连接该第一电子元件。
前述的电子封装件及其制法中，该第二电子元件借由第二导电元件设于该第二线路结构上，且于该第二电子元件与该第二线路结构之 间可形成包覆该第二导电元件的底胶。
前述的电子封装件及其制法中，还包括形成封装层于该第二线路结构上，以包覆该第二电子元件。
前述的电子封装件及其制法中，该第一电子元件借由导电体电性连接该第二线路结构。
前述的电子封装件及其制法中，还包括于设置该第二电子元件前，设置封装基板上于该些第一导电元件上。
由上可知，本发明的电子封装件及其制法中，主要借由形成该第二线路结构以接置该第二电子元件，故相较于现有技术，本发明的电子封装件配置有相对位于上、下位置的第一电子元件与第二电子元件，使该电子封装件具有多功能、高效能的优点。
附图说明
图1A至图1E为现有半导体封装件的制法的剖面示意图；
图2A至图2F为本发明的电子封装件的制法的第一实施例的剖视示意图；
图3A至图3D为本发明的电子封装件的制法的第二实施例的剖视示意图；以及
图4A至图4D为本发明的电子封装件的制法的第三实施例的剖视示意图。
符号说明：
1半导体封装件 10承载件
100热化离形胶层 11半导体元件
11a,20a作用面 11b,20b非作用面
110,200电极垫 14封装胶体
16线路结构 17导电元件
18,211绝缘保护层 2,3,4电子封装件
20第一电子元件 21,31第一线路结构
210,310第一线路重布层 22第二线路结构
220第二线路重布层 221绝缘层
23包覆层 23a第一表面
23b第二表面 24导电柱
24a第一端 24b第二端
25,35第一导电元件 26第二电子元件
27第二导电元件 28封装层
29底胶 30导电体
300粘着层 301保护膜
31a第一侧 31b第二侧
311第一绝缘层 32凸块底下金属层
4a封装组合 40封装基板
400电性接触垫 44强固件
8a第一承载件 8b第二承载件
80,82,90板体 81,83,91结合层
9承载件 L切割路径。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2F为本发明的电子封装件2的制法的第一实施例的剖视示意图。
如图2A所示，提供一第一承载件8a，且形成多个导电柱24于该第一承载件8a上，并设置至少一第一电子元件20于该第一承载件8a 上。接着，形成一包覆层23于该第一承载件8a上，以令该包覆层23包覆各该导电柱24与该第一电子元件20。
于本实施例中，该第一承载件8a包含如半导体材、介电材、陶瓷材、玻璃或金属材的板体80，但不限于此，且该第一承载件8a的尺寸可依需求选择晶圆型基板(Wafer formsubstrate)或一般整版面型基板(Panel form substrat)。例如，该第一承载件8a可具有如离型膜或胶材的结合层81，且该结合层81以涂布或贴合方式形成于该板体80上。
此外，该第一电子元件20为主动元件、被动元件或其二者组合，且该主动元件例如为半导体晶片，而该被动元件例如为电阻、电容及电感。例如，该第一电子元件20为半导体晶片，其具有相对的作用面20a与非作用面20b，该作用面20a上具有多个电极垫200，且该第一电子元件20以其作用面20a结合于该结合层81上。
又，该包覆层23具有相对的第一表面23a及第二表面23b，且该导电柱24具有相对的第一端24a与第二端24b，使该包覆层23的第二表面23b结合至该第一承载件8a的结合层81上，而该些导电柱24的第一端24a外露于该包覆层23的第一表面23a。具体地，该包覆层23为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(expoxy)的封装胶体或封装材(molding compound)。例如，该包覆层23的制程可选择液态封胶(liquidcompound)、喷涂(injection)、压合(lamination)或模压(compression molding)等方式形成于该结合层81上。
另外，可进行整平制程，使该第一电子元件20的非作用面20b与该些导电柱24的第一端24a齐平该包覆层23的第一表面23a。例如，借由研磨方式，移除该导电柱24的部分材质、该第一电子元件20的部分材质与该包覆层23的部分材质。
如图2B所示，形成一第一线路结构21于该包覆层23的第一表面23a与该第一电子元件20的非作用面20b上，且该第一线路结构21电性连接该些导电柱24，再形成多个第一导电元件25于该第一线路结构21上。
于本实施例中，该第一线路结构21包括至少一电性连接该些导电 柱24的第一端24a的第一线路重布层(redistribution layer，简称RDL)210。例如，形成该第一线路重布层210的材质为铜。
此外，该第一线路结构21还可包括至少一用以布设该第一线路重布层210的绝缘层(图略)，且形成该绝缘层的材质为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，借由该绝缘层可形成多层该第一线路重布层210。进一步，该第一线路结构21还可包括一如防焊层的绝缘保护层211，并令该第一导电元件25外露出该绝缘保护层211。
又，于一实施态样中，该第一线路重布层210接触但未电性连接该第一电子元件20的非作用面20b。
另外，该第一导电元件25包含焊锡材料、铜柱或其它导电材，其电性连接该第一线路重布层210。
如图2C所示，设置一第二承载件8b于该第一线路结构21上。接着，移除该第一承载件8a，以外露该包覆层23的第二表面23b、该些导电柱24的第二端24b与该第一电子元件20的作用面20a。
于本实施例中，该第二承载件8b包含如半导体材、介电材、陶瓷材、玻璃或金属材的板体82，但不限于此，且该第二承载件8b的尺寸可依需求选择晶圆型基板(Wafer formsubstrate)或一般整版面型基板(Panel form substrat)。
此外，该第二承载件8b还包含如离型膜或胶材的结合层83，且该结合层83以涂布或贴合方式形成于该板体82上，并将该结合层83压合于该第一线路结构21上，使该些第一导电元件25嵌埋于该结合层83中。
又，该第一电子元件20的作用面20a与该些导电柱24的第二端24b与该包覆层23的第二表面23b共平面(齐平)。
如图2D所示，进行线路重布层(RDL)制程，以形成一第二线路结构22于该包覆层23的第二表面23b上，且该第二线路结构22电性连接该第一电子元件20的电极垫200与该些导电柱24的第二端24b。
于本实施例中，该第二线路结构22包括至少一绝缘层221及设于该第二绝缘层221上的第二线路重布层(RDL)220，且最外层的第二 绝缘层221可作为防焊层，以令最外层的第二线路重布层220外露于该防焊层。
此外，形成该第二线路重布层220的材质为铜，且形成该第二绝缘层221的材质为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)的介电材。
如图2E所示，设置至少一第二电子元件26于该第二线路结构22上，再以封装层28包覆该第二电子元件26。之后，移除该第二承载件8b以外露出该些第一导电元件25。
于本实施例中，该第二电子元件26为主动元件、被动元件或其二者组合，且该主动元件例如为半导体晶片，而该被动元件例如为电阻、电容及电感。于一实施态样中，该第二电子元件26例如为图形处理器(graphics processing unit，简称GPU)、高频宽记忆体(High Bandwidth Memory，简称HBM)等半导体晶片，并无特别限制。
此外，该第二电子元件26以多个如焊锡凸块、铜凸块的第二导电元件27电性连接该第二线路重布层220。另该封装层28可同时包覆该第二电子元件26与该些第二导电元件27。
又，该封装层28为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、如环氧树脂(expoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该第二线路结构22上。应可理解地，形成该封装层28的材质可相同或不相同该包覆层23的材质。
另外，也可先形成底胶29于该第二电子元件26与该第二线路结构22之间以包覆该些第二导电元件27，再形成该封装层28以包覆该底胶29与该第二电子元件26。
如图2F所示，进行切单制程，以制成该电子封装件2，且于后续制程中，该电子封装件2可透过该第一导电元件25设于一电路板(图略)上。
因此，本发明的电子封装件的制法的第一实施例借由形成该第二线路结构22，以接置该第二电子元件26，故相较于现有技术，本发明的电子封装件2在第二线路结构22二侧配置有相对位于上、下位置的第一电子元件20与第二电子元件26，使该电子封装件2具有多功能、 高效能的优点。
请参阅图3A至图3D，其为本发明的电子封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于制作第一线路结构与第一导电元件的步骤顺序。
如图3A所示，于一承载件9上结合第一线路结构31，该第一线路结构31具有相对的第一侧31a与第二侧31b，且该第一线路结构31的第一侧31a设有多个第一导电元件35以结合至该承载件9上。接着，于该第二侧31b上形成多个电性连接该第一线路结构31的导电柱24，且设置第一电子元件20于该第一线路结构31的第二侧31b上。
于本实施例中，该第一线路结构31包括至少一第一绝缘层311与一设于该第一绝缘层311上的第一线路重布层(redistribution layer，简称RDL)310。例如，形成该第一线路重布层310的材质为铜，且形成该第一绝缘层311的材质为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。
此外，该承载件9包含如半导体材、介电材、陶瓷材、玻璃或金属材的板体90，但不限于此，且该承载件9的尺寸可依需求选择晶圆型基板(Wafer form substrate)或一般整版面型基板(Panel form substrat)。例如，该承载件9可具有如离型膜或胶材的结合层91，且该结合层91以涂布或贴合方式形成于该板体90上，使该第一线路结构31压合于该结合层91上，且令该些第一导电元件35嵌埋于该结合层91中。
又，该导电柱24设于该第一线路重布层310上并电性连接该第一线路重布层310，且形成该导电柱24的材质为如铜的金属材或焊锡材。
另外，该第一电子元件20以其非作用面20b借由粘着层300粘固于该第一线路结构31的第二侧31b上，且于作用面20a上设有一如钝化材的保护膜301与外露出该保护膜301的多个电极垫200，另于该电极垫200上结合并电性连接多个导电体30并凸出该保护膜301。具体地，该导电体30的构造为呈现如导电线路、焊球等的圆球状、如铜柱、焊锡凸块等的金属柱状、或焊线机制作的钉状(stud)，但不限于此。
如图3B所示，形成一包覆层23于该第一线路结构31的第二侧31b 上，以令该包覆层23包覆该第一电子元件20、该些导电体30与该些导电柱24，再借由整平制程，使该包覆层23的第二表面23b齐平该导电柱24的第二端24b与该导电体30的端面，令该导电柱24的第二端24b与该导电体30的端面外露于该包覆层23。
于本实施例中，该包覆层23为绝缘材，如环氧树脂的封装胶体，其可用压合(lamination)或模压(molding)的方式形成于该第一线路结构31的第二侧31b上。
此外，该整平制程借由研磨方式，移除该导电柱24的部分材质、该导电体30的部分材质与该包覆层23的部分材质。
如图3C所示，形成一第二线路结构22于该包覆层23的第二表面23b上，且该第二线路结构23电性连接该些导电柱24与该导电体30。之后，将至少一第二电子元件26透过多个如焊球的第二导电元件27接置于该第二线路结构22上，并以封装层28包覆该第二电子元件26与该第二导电元件27。
于本实施例中，该第二线路结构22可形成一凸块底下金属层(Under BumpMetallurgy，简称UBM)32于最外层的第二线路重布层220上，以利于结合该导电元件27。
此外，也可先形成第一实施例的底胶29于该第二电子元件26与该第二线路结构22之间以包覆该些第二导电元件27，再形成该封装层28以包覆该底胶29与该第二电子元件26。
如图3D所示，移除该承载件9，以外露该些第一导电元件35。之后，进行切单制程，以获取电子封装件3，且于后续制程中，该电子封装件3以其第一导电元件35设于一电路板(图略)上。
因此，本发明的制法的第二实施例借由先形成该第一线路结构31与该第一导电元件35，再形成该第二线路结构22以接置该第二电子元件26，故相较于现有技术，本发明的电子封装件3通过于第二线路结构22二侧配置有相对位于上、下位置的第一电子元件20与第二电子元件26，使该电子封装件3具有多功能、高效能的优点。
请参阅图4A至图4D，其为本发明的电子封装件4的制法的第三实施例的剖面示意图。本实施例与第二实施例的差异在于新增封装基板的制程。
如图4A所示，接续图3B的制程，形成一第二线路结构22于包覆层23的第二表面23b上，且该第二线路结构22电性连接该些导电柱24与该些导电体30。
如图4B所示，移除该承载件9，以外露该些第一导电元件35，并进行切单制程，以获取封装组合4a。
如图4C所示，将该封装组合4a以第一导电元件35接置于一封装基板40上。
于本实施例中，该封装基板40具有多个电性接触垫400以接合该些第一导电元件35。
此外，该封装基板40上可依需求设置强固件44，如金属框，以消除应力集中的问题而避免该封装基板40发生翘曲的情况。
如图4D所示，借由多个第二导电元件27接置至少一第二电子元件26于该第二线路结构22上，并以封装层28包覆该第二电子元件26，以获取电子封装件4，且于后续制程中，该电子封装件4以其封装基板40设于一电路板(图略)上。
于本实施例中，也可先形成第一实施例的底胶29于该第二电子元件26与该第二线路结构22之间以包覆该些第二导电元件27，再形成该封装层28以包覆该底胶29与该第二电子元件26。
因此，本发明的制法的第三实施例借由形成第一线路结构31与该第一导电元件35以接置该封装基板40，再形成该第二线路结构22以接置该第二电子元件26，故相较于现有技术，本发明的电子封装件4于第二线路结构22二侧配置有相对位于上、下位置的第一电子元件20与第二电子元件26，使该电子封装件4具有多功能、高效能的优点。
本发明还提供一种电子封装件2,3,4，包括：一包覆层23、至少一第一电子元件20、多个导电柱24、一第一线路结构21,31、多个第一导电元件25,35、一第二线路结构22以及至少一第二电子元件26。
所述的包覆层23具有相对的第一表面23a及第二表面23b。
所述的第一电子元件20嵌埋于该包覆层23中。
所述的导电柱24嵌埋于该包覆层23中。
所述的第一线路结构21,31设于该包覆层23的第一表面23a上并电性连接该导电柱24。
所述的第一导电元件25,35设于该第一线路结构21,31上。
所述的第二线路结构22设于该包覆层23的第二表面23b上并电性连接该导电柱24与该第一电子元件20。
所述的第二电子元件26设于该第二线路结构22上并电性连接该第二线路结构22。
于一实施例中，该导电柱24具有相对的第一端24a与第二端24b，且该第一端24a的端面齐平该包覆层23的第一表面23a，或该第二端24b的端面齐平该包覆层23的第二表面23b。
于一实施例中，该第一电子元件20具有相对的作用面20a与非作用面20b，该作用面20a齐平该包覆层23的第一表面23a，或该非作用面20b齐平该包覆层23的第二表面23b。
于一实施例中，该第一线路结构21,31电性连接该第一导电元件25,35。
于一实施例中，该第一线路结构21,31未电性连接该第一电子元件20。
于一实施例中，该第一电子元件20借由导电体30电性连接该第二线路结构22。
于一实施例中，该第二电子元件26借由第二导电元件27设于该第二线路结构22上。
于一实施例中，所述的电子封装件2,3,4还包括一封装层28，其设于该第二线路结构22上以包覆该第二电子元件26。
于一实施例中，所述的电子封装件4还包括一封装基板40，其设于该些第一导电元件35上。
综上所述，本发明的电子封装件及其制法，其借由形成该第二线路结构以接置该第二电子元件，故本发明的电子封装件配置有相对位于上、下位置的第一电子元件与第二电子元件，使该电子封装件具有多功能、高效能的优点。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (18)

1.一种电子封装件，其特征为，该电子封装件包括：
包覆层，其具有相对的第一表面及第二表面；
第一电子元件，其嵌埋于该包覆层中；
多个导电柱，其嵌埋于该包覆层中；
第一线路结构，其设于该包覆层的第一表面上并电性连接该导电柱；
多个第一导电元件，其设于该第一线路结构上；
第二线路结构，其设于该包覆层的第二表面上并电性连接该导电柱与该第一电子元件；以及
第二电子元件，其设于该第二线路结构上并电性连接该第二线路结构。
2.根据权利要求1所述的电子封装件，其特征为，该导电柱的端面齐平该包覆层的第一表面或第二表面。
3.根据权利要求1所述的电子封装件，其特征为，该第一电子元件的表面齐平该包覆层的第一表面或第二表面。
4.根据权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该第二线路结构上以包覆该第二电子元件的封装层。
5.根据权利要求1所述的电子封装件，其特征为，该第一线路结构未电性连接该第一电子元件。
6.根据权利要求1所述的电子封装件，其特征为，该第二电子元件借由第二导电元件设于该第二线路结构上。
7.根据权利要求6所述的电子封装件，其特征为，该电子封装件还包括设于该第二线路结构与该第二电子元件之间且包覆该第二导电元件的底胶。
8.根据权利要求1所述的电子封装件，其特征为，该第一电子元件借由导电体电性连接该第二线路结构。
9.根据权利要求1所述的电子封装件，还包括封装基板，其设于该些第一导电元件上。
10.一种电子封装件的制法，其特征为，该制法包括：
提供一具有相对的第一表面及第二表面的包覆层，其嵌埋有第一电子元件与多个导电柱，且于该第一表面上设有电性连接该导电柱的第一线路结构，并于该第一线路结构上设有多个第一导电元件；
形成第二线路结构于该包覆层的第二表面上，且令该第二线路结构电性连接该导电柱与该第一电子元件；以及
设置第二电子元件于该第二线路结构上，且令该第二电子元件电性连接该第二线路结构。
11.根据权利要求10所述的电子封装件的制法，其特征为，该导电柱的端面齐平该包覆层的第一表面或第二表面。
12.根据权利要求10所述的电子封装件的制法，其特征为，该第一电子元件的表面齐平该包覆层的第一表面或第二表面。
13.根据权利要求10所述的电子封装件的制法，其特征为，该制法还包括形成封装层于该第二线路结构上，以包覆该第二电子元件。
14.根据权利要求10所述的电子封装件的制法，其特征为，该第一线路结构未电性连接该第一电子元件。
15.根据权利要求10所述的电子封装件的制法，其特征为，该第二电子元件借由第二导电元件设于该第二线路结构上。
16.根据权利要求15所述的电子封装件的制法，其特征为，该制法还包括形成底胶于该第二线路结构与该第二电子元件之间且包覆该第二导电元件。
17.根据权利要求10所述的电子封装件的制法，其特征为，该第一电子元件借由导电体电性连接该第二线路结构。
18.根据权利要求10所述的电子封装件的制法，其特征为，该制法还包括于设置该第二电子元件前，设置封装基板于该些第一导电元件上。
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