CN108666255A - 封装堆叠结构及其制法 - Google Patents

封装堆叠结构及其制法 Download PDF

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Publication number
CN108666255A
CN108666255A CN201710244156.8A CN201710244156A CN108666255A CN 108666255 A CN108666255 A CN 108666255A CN 201710244156 A CN201710244156 A CN 201710244156A CN 108666255 A CN108666255 A CN 108666255A
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CN
China
Prior art keywords
insulating layer
stacking structure
structure according
encapsulation stacking
layer
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Pending
Application number
CN201710244156.8A
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English (en)
Inventor
陈汉宏
许元鸿
林长甫
林荣政
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN108666255A publication Critical patent/CN108666255A/zh
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
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Abstract

一种封装堆叠结构及其制法，用以于设有电子元件的板体上堆叠无核心层(coreless)的线路部，以降低该封装堆叠结构的整体厚度。

Description

封装堆叠结构及其制法
技术领域
本发明有关一种封装结构，尤指一种封装堆叠结构及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，业界遂发展出叠加多个封装结构以形成封装堆叠结构(Package on Package，简称POP)，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子元件，例如记忆体、中央处理器、绘图处理器、影像应用处理器等，通过堆叠设计达到系统的整合，适合应用于轻薄型各种电子产品。
图1A及图1B为现有封装堆叠结构1,1’的不同态样的剖面示意图。
如图1A所示，该封装堆叠结构1包含第一封装基板11及第二封装基板12，该第一封装基板11具有多个线路层110，且该第二封装基板12具有核心层120与多个线路层121，俾供第一半导体元件10以覆晶方式设于该第一封装基板11上，再通过底胶14充填于该第一半导体元件10与第一封装基板11之间，且第二半导体元件15以打线方式结合于该第二封装基板12上，再通过封装胶体16包覆该第二半导体元件15，并以多个焊球13叠设且电性连接该第一封装基板11与该第二封装基板12。
如图1B所示，该封装堆叠结构1’包含第一封装基板11及第二封装基板12，该第一封装基板11具有多个线路层110，且该第二封装基板12具有核心层120与多个线路层121，俾供第一半导体元件10以覆晶方式设于该第一封装基板11上，再通过底胶14充填于该第一半导体元件10与第一封装基板11之间，之后以多个焊球13叠设且电性连接该第一封装基板11与该第二封装基板12，再通过封装胶体16’包覆该些焊球13与第一半导体元件10，后续将第二半导体元件15’以覆晶方式设于该第二封装基板12上。
惟，现有封装堆叠结构1,1’中，其第二封装基板12皆具有核心层120，导致该封装堆叠结构1,1’不符合薄化的需求。
因此，如何克服现有技术中的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种封装堆叠结构及其制法，以降低该封装堆叠结构的整体厚度。
本发明的封装堆叠结构，包括：第一组件，其包含有绝缘层、线路部与多个导电元件，其中，该绝缘层具有相对的第一表面与第二表面，该线路部结合该绝缘层，该导电元件立设于该绝缘层的第一表面上并接触该线路部，且该第一组件不具有核心层；板体，其透过该多个导电元件而堆叠于该绝缘层的第一表面上；以及第一电子元件，其设于该板体上。
前述的封装堆叠结构中，还包括结合于该绝缘层的第二表面上的支撑部。例如，该支撑部包含至少一金属层，并以该金属层结合该绝缘层的第二表面；或者，该支撑部包含多个金属层与多个隔离层，并以该金属层结合该绝缘层的第二表面。
本发明还提供一种封装堆叠结构的制法，包括：提供一包含绝缘层、线路部、多个导电元件与支撑部的第一组件，该绝缘层具有相对的第一表面与第二表面，且该线路部结合该绝缘层，该导电元件立设于该绝缘层的第一表面上并接触该线路部，且该绝缘层藉其第二表面结合该支撑部；将该第一组件接置于第二组件上，其中该第二组件包含有一板体及设于该板体上的第一电子元件，以令该绝缘层、线路部与支撑部透过该些导电元件堆叠于该板体上；以及于该第一组件接置至第二组件后，移除该支撑部。
前述的制法中，该支撑部包含至少一金属层，并以该金属层结合该绝缘层的第二表面。
前述的制法中，该支撑部包含多个金属层与多个隔离层，并以该金属层结合该绝缘层的第二表面。
前述的封装堆叠结构及其制法中，该线路部包含至少一线路层。
前述的封装堆叠结构及其制法中，该线路部的外表面低于该绝缘层的第二表面。
前述的封装堆叠结构及其制法中，该导电元件为焊球、铜核心球或金属件。
前述的封装堆叠结构及其制法中，还包括将第二电子元件设于该绝缘层的第二表面上。
前述的封装堆叠结构及其制法中，还包括将封装材形成于该绝缘层的第一表面与该板体之间。
前述的封装堆叠结构及其制法中，该线路部嵌埋于该绝缘层中。
由上可知，本发明封装堆叠结构及其制法，主要通过先将该第一组件堆叠于该板体上，再移除该支撑部，以提供稳固该第一组件的效果，且可降低该封装堆叠结构的整体厚度。
附图说明
图1A及图1B为现有封装堆叠结构的不同态样的剖视示意图；
图2A至图2D为本发明的封装堆叠结构的第一实施例的制法的剖视示意图；
图3A至图3D为本发明的封装堆叠结构的第二实施例的制法的局部剖视示意图；以及
图4为本发明的封装堆叠结构的第一组件的支撑部的另一实施例的剖面示意图。
符号说明：
1,1’,2,3 封装堆叠结构
10 第一半导体元件
11 第一封装基板
110,121 线路层
12 第二封装基板
120 核心层
13 焊球
14 底胶
15,15’ 第二半导体元件
16,16’ 封装胶体
2a,3a 第一组件
2b 第二组件
20 绝缘层
20a 第一表面
20b 第二表面
21,31 线路部
210 导电盲孔
211 第一线路层
212 第二线路层
22 导电元件
23,33,43 支撑部
231 第一金属层
232 第二金属层
233 第三金属层
24 板体
240 电性接触垫
241 焊锡材
25 第一电子元件
250,270 导电凸块
26 封装材
27 第二电子元件
28 焊球
300 开孔
330 第一隔离层
331 第一金属层
332 第二金属层
333 第二隔离层
h 高度
S 切割路径
t,d,r,L 厚度。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“第三”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2D为本发明的封装堆叠结构2的第一实施例的制法的剖视示意图。
如图2A所示，提供一第一组件2a，其包含一绝缘层20、一线路部21、多个导电元件22与一支撑部23。
所述的绝缘层20具有相对的第一表面20a与第二表面20b，并以该第二表面20b结合该支撑部23。
于本实施例中，形成该绝缘层20的材质可为介电材，如预浸材(prepreg)、封装材(molding compound)或ABF(Ajinomoto Build-up Film)等，且该绝缘层20的厚度t例如为15微米。
所述的线路部21结合该绝缘层20，例如嵌埋于该绝缘层20中。于本实施例中，该线路部21包含一埋设于该第一表面20a的第一线路层211、一埋设于该第二表面20b的第二线路层212、及多个电性连接该第一与第二线路层211,212的导电盲孔210。应可理解地，该第一与第二线路层211,212也可设于该绝缘层20的第一表面20a与第二表面20b之上。
此外，形成该第一线路层211、该第二线路层212及该些导电盲孔210的材质为铜材、镍/金材或其它合适导电材。
所述的导电元件22立设于该绝缘层20的第一表面20a上并接触该线路部21的第一线路层211。
于本实施例中，该导电元件22为焊球(solder ball)、铜核心球、或如铜材或金材的金属件(如柱状、块状或针状)等。
再者，该导电元件22的形状并无限制，如锥柱体(即体积由底端朝顶端渐缩)或其它形状。
又，该导电元件22突出该第一表面20a的高度h例如为165微米。
所述的支撑部23可为已切单的板块或为整版面结构(即包含多个单元)，例如条形(strip form)或晶圆型(wafer form)。
于本实施例中，该支撑部23由第一金属层231、第二金属层232与第三金属层233所构成，并以该第一金属层231结合该绝缘层20的第二表面20b与该第二线路层212。
此外，该第一与第三金属层231,233为铜层，且该第二金属层232为镍层。
又，该第一与第二金属层231,232的厚度d,r例如为3微米，且该第三金属层233的厚度L例如为70微米。
如图2B示，将该第一组件2a接置于第二组件2b上，其中，该第二组件2b包含有板体24以及设于该板体24上的第一电子元件25，以于该绝缘层20的第一表面20a上堆叠该板体24(或于该板体24上堆叠该第一组件2a)。接着，将封装材26形成于该绝缘层20的第一表面20a与该板体24之间，以包覆该第一电子元件25与该导电元件22。
所述的板体24为具有核心层或无核心层(coreless)的线路结构，如封装基板(substrate)，其具有如扇出(fan out)型重布线路层(redistribution layer，简称RDL)的线路配置。应可理解地，该板体亦可为其它承载芯片的板材，如导线架(leadframe)、晶圆(wafer)、或其它具有金属布线(routing)的载板等，并不限于上述。
于本实施例中，该导电元件22熔融接合至该板体24的电性接触垫240上的焊锡材241。
所述的第一电子元件25为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。
于本实施例中，该第一电子元件25通过多个如焊锡材料的导电凸块250以覆晶方式设于该板体24上并电性连接该板体24；或者，该第一电子元件25可通过多个焊线(图略)以打线方式电性连接该板体24；亦或，该第一电子元件25可直接接触该板体24的线路。然而，有关该第一电子元件25电性连接该板体24的方式不限于上述。
所述的封装材26的形成材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或模塑料(molding compound)等，但不限于上述。
如图2C所示，移除该支撑部23，使该第二线路层212外露于该绝缘层20的第二表面20b。
于本实施例中，先以蚀刻制程依序移除第三金属层233与第二金属层232，以得到一平整表面，再微蚀刻第一金属层231并延伸至该绝缘层20的第二表面20b下方3至5微米(即移除部分该第二线路层212)，使该线路部21的第二线路层212的外表面低于该绝缘层20的第二表面20b。
应可理解地，若先移除该支撑部23，再将埋设有线路部21的绝缘层20堆叠于该板体24上，则于移除该支撑部23的过程中会因刚性不足而无法稳固该第一组件2a，致使该第一组件2a会产生位移，导致设备无法取放(pick&place)该绝缘层20。因此，本发明的制法先将该第一组件2a堆叠于该板体24上，再移除该支撑部23，以通过该板体24(及该封装材26)提供稳固该第一组件2a的效果，故于于薄化过程中(即移除该支撑部23)，能避免因刚性不足而无法取放的情况发生。
如图2D所示，沿如图2C所示的切割路径S进行切单制程，之后将第二电子元件27设于该绝缘层20的第二表面20b上，且于该板体24下方植设如焊球28的导电件。
于本实施例中，该第二电子元件27为封装件、主动元件、被动元件或其三者组合等，其中，该封装件为例如芯片级封装(Chip Scale Package，简称CSP)，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该第二电子元件27通过多个如焊锡材料的导电凸块270堆叠于该第二表面20b上并电性连接该第二线路层212；或者，该第二电子元件27可通过多个焊线(图略)以打线方式电性连接该第二线路层212；亦或，该第二电子元件27可直接接触该第二线路层212。然而，有关该第二电子元件27电性连接该第二线路层212的方式不限于上述。
本发明的制法通过先将该第一组件2a堆叠于第二组件2b的板体24上，再移除部分该第一组件2a(即移除该支撑部23)，故相较于现有技术，本发明的制法因该板体24上堆叠无核心层(coreless)的线路部21而能降低该封装堆叠结构2的整体厚度。
图3A至图3D为本发明的封装堆叠结构3的第二实施例的制法的剖视示意图。本实施例与第一实施例的差异在于第一组件的结构不同，其它制程大致相同，故以下仅详细说明相异处，而不再赘述相同处。
如图3A所示，为如图2B所示的制程，将一包含绝缘层20、线路部31、多个导电元件22与一支撑部33的第一组件3a堆叠至第二组件2b的板体24上，且将封装材26形成于该绝缘层20的第一表面20a与该板体24之间。
所述的线路部31为单一线路层，其埋设于该绝缘层20的第一表面20a。
所述的导电元件22立设于该绝缘层20的第一表面20a上并接触该线路部31且熔融接合至该板体24上。
所述的支撑部33包含第一与第二金属层331,332及第一与第二隔离层330,333，并以该第一金属层331结合该绝缘层20的第二表面20b。
于本实施例中，形成该绝缘层20与该第二隔离层333的材质为ABF(AjinomotoBuild-up Film)，且形成该第一与第二金属层331,332的材质为铜层，而该第一隔离层330作为核心层。应可理解地，该第一组件3a为相对核心层对称布设的构造，该绝缘层20与该第二隔离层333的材质可相同或不相同，且该第一组件3a的构造不限于上述。
如图3B所示，以研磨方式移除该支撑部33，以外露出该绝缘层20的第二表面20b。
如图3C所示，以例如雷射钻孔方式，形成多个开孔300于该绝缘层20的第二表面20b上，使该线路部31的部分表面外露于该绝缘层20的第二表面20b。
如图3D所示，于该板体24下方植设焊球28，并进行切单制程，且将第二电子元件27设于该绝缘层20的第二表面20b上，并以形成于该些开孔300中的导电凸块270电性连接该线路部31。
本发明的制法通过先将该第一组件3a堆叠于该板体24上，再移除部分该第一组件3a(即移除该支撑部33)，故相较于现有技术，本发明的制法不仅能提供稳固该第一组件3a的效果，以避免于薄化过程中(即移除该支撑部33)因刚性不足而无法取放的情况发生，且因该板体24上堆叠无核心层的线路部31而能降低该封装堆叠结构3的整体厚度。
再者，如图4所示，该第一组件的支撑部43亦可为单一金属层，如铜、铁或不锈钢，并于制程中以蚀刻或研磨移除。
本发明还提供一种封装堆叠结构2,3，其包括：一绝缘层20、一线路部21,31、多个导电元件22、一板体24以及至少一第一电子元件25。
所述的绝缘层20具有相对的第一表面20a与第二表面20b。
所述的线路部21,31结合该绝缘层20，例如，该线路部21,31嵌埋于该绝缘层20中。
所述的导电元件22立设于该绝缘层20的第一表面20a上并接触该线路部21,31。
所述的板体24接置于该些导电元件22上以堆叠于该绝缘层20的第一表面20a上。
所述的第一电子元件25设于该板体24上。
于一实施例中，该线路部21,31包含至少一线路层。
于一实施例中，该线路部31的外表面低于该绝缘层20的第二表面20b。
于一实施例中，该导电元件22为焊球、铜核心球或金属件。
于一实施例中，该封装堆叠结构2,3还包括第二电子元件27，设于该绝缘层20的第二表面20b上。
于一实施例中，该封装堆叠结构2,3还包括封装材26，形成于该绝缘层20的第一表面20a与该板体24之间。
于一实施例中，该封装堆叠结构2,3还包括结合于该绝缘层20的第二表面20b上的支撑部23,33,43。例如，该支撑部23,43包含至少一金属层(例如第一至第三金属层231,232,233)，并以该金属层结合该绝缘层20的第二表面20b；或者，该支撑部33包含多个金属层(例如第一及第二金属层331,332)与多个隔离层(例如第一及第二隔离层330,333)，并以该金属层结合该绝缘层20的第二表面20b。
综上所述，本发明封装堆叠结构及其制法，通过先将该第一组件堆叠于该第二组件的板体上，再移除该支撑部，以提供稳固该第一组件的效果，且能降低该封装堆叠结构的整体厚度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种封装堆叠结构，其特征为，该结构包括：
第一组件，其包含有绝缘层、线路部与多个导电元件，其中，该绝缘层具有相对的第一表面与第二表面，该线路部结合该绝缘层，该导电元件立设于该绝缘层的第一表面上并接触该线路部，且该第一组件不具有核心层；
板体，其透过该多个导电元件而堆叠于该绝缘层的第一表面上；以及
第一电子元件，其设于该板体上。
2.根据权利要求1所述的封装堆叠结构，其特征为，该线路部包含至少一线路层。
3.根据权利要求1所述的封装堆叠结构，其特征为，该线路部的外表面低于该绝缘层的第二表面。
4.根据权利要求1所述的封装堆叠结构，其特征为，该导电元件为焊球、铜核心球或金属件。
5.根据权利要求1所述的封装堆叠结构，其特征为，该结构还包括设于该绝缘层的第二表面上的第二电子元件。
6.根据权利要求1所述的封装堆叠结构，其特征为，该结构还包括形成于该绝缘层的第一表面与该板体之间的封装材。
7.根据权利要求1所述的封装堆叠结构，其特征为，该结构还包括结合于该绝缘层的第二表面上的支撑部。
8.根据权利要求7所述的封装堆叠结构，其特征为，该支撑部包含至少一金属层，并以该金属层结合该绝缘层的第二表面。
9.根据权利要求7所述的封装堆叠结构，其特征为，该支撑部包含多个金属层与多个隔离层，并以该金属层结合该绝缘层的第二表面。
10.根据权利要求1所述的封装堆叠结构，其特征为，该线路部嵌埋于该绝缘层中。
11.一种封装堆叠结构的制法，其特征为，该制法包括：
提供一包含绝缘层、线路部、支撑部与多个导电元件的第一组件，其中，该绝缘层具有相对的第一表面与第二表面，该线路部结合该绝缘层，该导电元件立设于该绝缘层的第一表面上并接触该线路部，且该绝缘层以其第二表面结合该支撑部；
将该第一组件接置于第二组件上，其中，该第二组件包含有一板体及设于该板体上的第一电子元件，以令该绝缘层、线路部与支撑部透过该多个导电元件堆叠于该板体上；以及
于该第一组件接置至该第二组件后，移除该支撑部。
12.根据权利要求11所述的封装堆叠结构的制法，其特征为，该支撑部包含至少一金属层，并以该金属层结合该绝缘层的第二表面。
13.根据权利要求11所述的封装堆叠结构的制法，其特征为，该支撑部包含多个金属层与多个隔离层，并以该金属层结合该绝缘层的第二表面。
14.根据权利要求11所述的封装堆叠结构的制法，其特征为，该线路部包含至少一线路层。
15.根据权利要求11所述的封装堆叠结构的制法，其特征为，于移除该支撑部后，令该线路部的外表面外露出该绝缘层的第二表面。
16.根据权利要求15所述的封装堆叠结构的制法，其特征为，该线路部的外表面低于该绝缘层的第二表面。
17.根据权利要求11所述的封装堆叠结构的制法，其特征为，该导电元件为焊球、铜核心球或金属件。
18.根据权利要求11所述的封装堆叠结构的制法，其特征为，该制法还包括于该绝缘层的第二表面上接置第二电子元件。
19.根据权利要求11所述的封装堆叠结构的制法，其特征为，该制法还包括于该绝缘层的第一表面与该板体之间形成封装材。
20.根据权利要求11所述的封装堆叠结构的制法，其特征为，该线路部嵌埋于该绝缘层中。
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