CN110233112A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

Info

Publication number
CN110233112A
CN110233112A CN201810378273.8A CN201810378273A CN110233112A CN 110233112 A CN110233112 A CN 110233112A CN 201810378273 A CN201810378273 A CN 201810378273A CN 110233112 A CN110233112 A CN 110233112A
Authority
CN
China
Prior art keywords
packing piece
electronic component
electronic
encapsulated layer
piece according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810378273.8A
Other languages
English (en)
Inventor
邱志贤
陈嘉扬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN110233112A publication Critical patent/CN110233112A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

一种电子封装件及其制法，用于将电子元件与多个导电柱设于承载结构上，并以封装层包覆该电子元件与导电柱，其中，该导电柱的周面的宽度小于该导电柱的两端面的宽度，以使该封装层与该导电柱之间具有较佳的固定效果。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体封装制程，尤指一种电子封装件及其制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductor device)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂叠加多个封装结构以形成封装堆叠结构(Package on Package，简称POP)，此种封装方式能发挥系统封装(SiP)异质整合特性，可将不同功用的电子元件，例如：存储器、中央处理器、绘图处理器、影像应用处理器等，借由堆叠设计达到系统的整合，适合应用于轻薄型各种电子产品。
图1为悉知封装堆叠结构1的剖面示意图。如图1所示，该封装堆叠结构1包含第一封装基板11及第二封装基板12。该第一封装基板11具有相对的第一表面11a及第二表面11b，且于该第一表面11a上设有电性连接该第一封装基板11的第一半导体元件10，而该第二表面11b上具有植球垫112以供结合焊球17。该第二封装基板12具有相对的第三表面12a及第四表面12b，且该第三表面12a设有多个电性接触垫120，又该第三表面12a及第四表面12b上具有防焊层123，并形成有多个开孔以外露该些电性接触垫120。
于制作时，先将该第一半导体元件10以覆晶方式电性连接该第一封装基板11，且借由底胶16充填于该第一半导体元件10与第一封装基板11之间，并于该第一封装基板11的第一表面11a上形成多个焊锡球13，再令该第二封装基板12以其第四表面12b借由该焊锡球13叠设且电性连接于该第一封装基板11上。接着，形成封装胶体14于该第一封装基板11的第一表面11a与该第二封装基板12的第四表面12b之间，以包覆该第一半导体元件10及焊锡球13。之后，以覆晶方式设置多个第二半导体元件15于该第三表面12a上以电性连接该些电性接触垫120，且借由底胶16充填于该第二半导体元件15与第二封装基板12之间。
然而，悉知封装堆叠结构1的制法中，由于第一封装基板11与第二封装基板12间以该焊锡球13作为支撑与电性连接的元件，且该焊锡球13具有一定的宽度，故随着电子产品的接点(即I/O)数量愈来愈多，在封装件的尺寸大小不变的情况下，各该焊锡球13间的间距需缩小，致使容易发生桥接(bridge)的现象，而造成产品良率过低及可靠度不佳等问题，因而该焊锡球13无法达到细间距(fine pitch)的需求。
此外，该焊锡球13以植球或网印(screen printing)的方式形成于该第一封装基板11上，且于回焊后的体积及高度的公差大，不仅接点容易产生缺陷，导致电性连接品质不良，而且该焊锡球13所排列成的栅状阵列(grid array)容易产生共面性(coplanarity)不良，导致接点应力(stress)不平衡而容易造成该第一封装基板11与第二封装基板12之间呈倾斜接置，甚至产生接点偏移的问题。
因此，如何克服悉知技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述悉知技术的缺失，本发明提供一种电子封装件及其制法，以使封装层与导电柱之间具有较佳的固定效果。
本发明的电子封装件，包括：承载结构；电子元件，其设于该承载结构上且电性连接该承载结构；多个导电柱，其设于该承载结构上，其中，该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度；以及封装层，其包覆该电子元件与该导电柱。
本发明还提供一种电子封装件的制法，包括：将导电架及至少一电子元件设于一承载结构上，其中，该导电架包含有板体与多个连接该板体的导电柱，并以该导电柱结合于该承载结构上，又该导电柱具有相对的两端面及邻接该两端面的周面，该周面的宽度小于该两端面的宽度；以封装层包覆该电子元件与该导电柱；以及移除该板体。
前述的制法中，该导电架的制作为移除金属板的部分材质，以形成用以间隔各该导电柱的凹部。
前述的电子封装件及其制法中，该导电柱电性连接该承载结构。
前述的电子封装件及其制法中，该导电柱借由导电体结合至该承载结构上。
前述的电子封装件及其制法中，该承载结构具有相对的第一侧与第二侧，且该第一侧与该第二侧上均布设有该电子元件或该封装层。
前述的电子封装件及其制法中，该电子元件的部分表面外露出该封装层的表面。
前述的电子封装件及其制法中，该导电架还包含有结合垫，且该结合垫对应该电子元件的位置并至少部分外露出该封装层。
前述的电子封装件及其制法中，还包括形成屏蔽件以遮盖该电子元件。
前述的电子封装件及其制法中，还包括于移除该板体后，形成布线结构于该封装层上，且该布线结构电性连接该导电柱或该电子元件。
由上可知，本发明的电子封装件及其制法，主要借由该导电架的导电柱取代悉知焊锡球，以依需求调整各该导电柱之间的间距，故相较于悉知技术，该些导电柱之间不会发生桥接的问题，因而能有效提高产品良率及可靠度，以达到细间距的需求。
此外，本发明的电子封装件的制法为先制作该导电架，再将该导电架设于该承载结构上，故相较于悉知技术，本发明的制法可使该些导电柱的高度一致，使该些导电柱所排列成的栅状阵列的共面性良好，因而能避免于后续制程中产生接点偏移的问题。
又，该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度，使该导电柱的侧壁内凹，而可容纳该封装层，以提供较佳的固定效果，故可避免因该封装层与该导电柱的结合性不佳而于后续制程发生脱层的问题。
附图说明
图1为悉知封装堆叠结构的剖视示意图；
图2A至图2E为本发明的电子封装件的制法的第一实施例的剖视示意图；
图3A至图3C为本发明的电子封装件的制法的第二实施例的剖视示意图；
图4A至图4B为本发明的电子封装件的制法的第三实施例的不同实施例的剖视示意图；
图5A至图5D为本发明的电子封装件的制法的第四实施例的剖视示意图；其中，图5D’为图5D的另一实施例；
图6A至图6E为本发明的电子封装件的制法的第五实施例的剖视示意图；其中，图6C’为图6C的另一步骤；以及
图7A至图7C为本发明的电子封装件的制法的第六实施例的剖视示意图。
符号说明
1 封装堆叠结构 10 第一半导体元件
11 第一封装基板 11a 第一表面
11b 第二表面 112 植球垫
12 第二封装基板 12a 第三表面
12b 第四表面 120 电性接触垫
123,202 防焊层 13 焊锡球
14 封装胶体 15 第二半导体元件
16 底胶 17 焊球
2,3,4,5,6,7 电子封装件 2a,5a 导电架
20,30 承载结构 20a,30a 第一侧
20b,30b 第二侧 200 线路层
201 绝缘层 21 第一电子元件
21a 作用面 21b 非作用面
210,220 导电凸块 22 第二电子元件
23 导电柱 23a,23b 端面
23c 周面 230 导电体
24 板体 240 凹部
25,55 第一封装层 25a 第一表面
25b,55b 第二表面 25c,26c 侧面
26 第二封装层 26a 顶面
27,77,80 导电元件 51 结合层
53 结合垫 68 屏蔽件
71 粘着层 79 布线结构
790 介电层 791 线路重布层
8 电子装置 9 支撑板
90 离形膜 S 切割路径
W 宽度。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2E，其为本发明的电子封装件2的制法的第一实施例的剖视示意图。
如图2A所示，提供一导电架2a，其包含一板体24及多个分离设于该板体24上的导电柱23，其中，该导电柱23具有相对的两端面23a,23b及邻接该两端面23a,23b的周面23c，且该周面23c的宽度小于该两端面23a,23b的宽度W。
于本实施例中，该导电柱23的周面23c为相对两端面23a,23b呈凹状，使该两端面23a,23b的宽度W大于该周面23c的宽度，且该板体24与导电柱23为一体成形。例如，以蚀刻、激光或其它方式移除一金属板的部分材质，以形成该导电架2a。具体地，该金属板为经由蚀刻方式形成用以间隔各该导电柱23的底切型凹部240，使该导电柱23的周面23c呈内凹弧形。
如图2B所示，将该导电架2a设置于一承载结构20上，且设置至少一第一电子元件21于该承载结构20上。
于本实施例中，该承载结构20具有相对的第一侧20a与第二侧20b，且该承载结构20例如为具有核心层与线路部的封装基板(substrate)或具有线路部的无核心层(coreless)式封装基板，其线路部具有至少一绝缘层201与设于该绝缘层201上的线路层200，该线路层200例如为扇出(fan out)型重布线路层(redistribution layer，简称RDL)，并可依需求形成防焊层202于该第一侧20a与第二侧20b上。另外，形成该线路层200的材质例如为铜，且形成该绝缘层201的材质例如为聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，该承载结构也可为其它可供承载如晶片等电子元件的承载单元，例如导线架(leadframe)或硅中介板(silicon interposer)，并不限于上述。
此外，该第一电子元件21设于该承载结构20的第一侧20a上，且该第一电子元件21为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体晶片，且该被动元件例如为电阻、电容及电感。例如，该第一电子元件21具有相对的作用面21a与非作用面21b，其作用面21a借由多个如焊锡材料的导电凸块210以覆晶方式设于该线路层200上并电性连接该线路层200；或者，该第一电子元件21可借由多个焊线(图略)以打线方式电性连接该线路层200。然而，有关该第一电子元件电性连接该承载结构的方式不限于上述。
又，该导电架2a以其导电柱23的端面23a借由如焊锡材的导电体230结合至该承载结构20的第一侧20a的线路层200上。
如图2C所示，形成第一封装层25于该承载结构20的第一侧20a上，以包覆该第一电子元件21与该些导电柱23及导电体230，且令该导电架2a的板体24外露出该第一封装层25。
于本实施例中，该第一封装层25具有相对的第一表面25a与第二表面25b，且其以第一表面25a结合于该承载结构20的第一侧20a上，并令该板体24外露出该第一封装层25的第二表面25b。
此外，形成于该第一封装层25的材质例如为聚酰亚胺(PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound)，但不限于上述。
如图2D所示，进行整平制程，以移除该导电架2a的板体24及部分该第一封装层25，令该导电柱23的端面23b与该第一封装层25的第二表面25b共平面(齐平)，使该导电柱23的端面23b外露出该第一封装层25的第二表面25b。
于本实施例中，为采用研磨、蚀刻、烧灼、切除或其它适合方式移除该板体24及部分该第一封装层25，使该导电柱23的端面23b外露出该第一封装层25，以供后续进行电子电路的相关导路配置，如图2E所示的借由如焊球的导电元件80外接如封装结构或半导体晶片的其它电子装置8。
此外，该第一封装层25填入该第一电子元件21与该承载结构20的第一侧20a之间以包覆该些导电凸块210；或者，可先填充底胶(图略)于该第一电子元件21与该承载结构20的第一侧20a之间以包覆该些导电凸块210，再使该第一封装层25包覆该底胶。
如图2E所示，结合多个如焊球的导电元件27于该承载结构20的第二侧20b的线路层200上，以供后续接置电路板(图未示)。
请参阅图3A至图3C，其为本发明的电子封装件3的制法的第二实施例的剖视示意图。本实施例与第一实施例的差异在于提供不同型式的承载结构30，其它制程则大致相同。
如图3A所示，于一支撑板9上进行RDL制程以形成线路部，并使该线路部作为承载结构30。接着，将导电架2a与多个第一电子元件21设于该承载结构30的第一侧30a上。
于本实施例中，该支撑板9上设有离形膜90，以利于后续分离该承载结构30。
此外，该承载结构30为具有线路部的无核心层式封装基板，其线路部具有至少一绝缘层201与设于该绝缘层201上的线路层200。
如图3B所示，形成第一封装层25于该承载结构30的第一侧30a上，以包覆该些第一电子元件21与该些导电柱23。接着，进行整平制程，使该导电柱23的端面23b外露出该第一封装层25的第二表面25b。
如图3C所示，移除该支撑板9及其离形膜90，以外露该承载结构30的第二侧30b，再结合多个如焊球的导电元件27于该承载结构30的第二侧30b的线路层200上。
请参阅图4A及图4B，其为本发明的电子封装件4的第三实施例的剖面示意图。本实施例与上述实施例的差异在于该承载结构20的第二侧20b的布设。
如图4A所示，于形成第一封装层25之前，先设置第二电子元件22于该承载结构20的第二侧20b上，再进行双侧模封(double side molding)制程，形成该第一封装层25于该承载结构20的第一侧20a与第二侧20b上以包覆该第一电子元件21与第二电子元件22。之后，于该些导电柱23的外露表面(端面23b)上形成有如焊球的导电元件27，以供接置如电路板的电子装置(图未示)。
于本实施例中，该第二电子元件22为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体晶片，且该被动元件例如为电阻、电容及电感。例如，该第二电子元件22借由多个如焊锡材料的导电凸块220以覆晶方式设于该线路层200上；或者，该第二电子元件22可借由多个焊线(图略)以打线方式电性连接该线路层200；抑或，该第二电子元件22可直接接触该线路层200。然而，有关该第二电子元件电性连接该承载结构的方式不限于上述。
此外，该第一电子元件21的非作用面21b可选择性不外露出该第一封装层25的第二表面25b；或者，如图4B所示，该第一电子元件21的非作用面21b可外露出该第一封装层25的第二表面25b。
请参阅图5A至图5D，其为本发明的电子封装件5的第四实施例的剖面示意图。本实施例与第三实施例的差异在于该导电架5a的结构及制程步骤。
如图5A所示，该导电架5a包含一板体24、相分离设于该板体24上的多个导电柱23与至少一结合垫53。
于本实施例中，该板体24、导电柱23与结合垫53为一体成形。例如，以蚀刻、激光或其它方式移除一金属板上的部分材质，以形成该导电架5a。
如图5B所示，将该导电架5a透过其导电柱23与导电体230设于承载结构20的第一侧20a上，且第一电子元件21的非作用面21b可借由结合层51结合至该结合垫53，并使该结合垫53作为散热用。
于本实施例中，该结合层51例如为薄膜(film)、环氧树脂(epoxy)或热介面材料(thermal interface material，简称TIM)。
此外，该承载结构20的第二侧20b设有第二电子元件22，且于形成该第一封装层25之前，形成第二封装层26于该承载结构20的第二侧20b上以包覆该第二电子元件22。例如，形成该第二封装层26的材质为聚酰亚胺(PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound)，但不限于上述。
如图5C所示，形成第一封装层55于该承载结构20的第一侧20a与该板体24之间，使该第一封装层55包覆该第一电子元件21、结合层51、结合垫53、导电体230与该些导电柱23。之后，移除该板体24，使该些导电柱23的端面23b与该结合垫53外露出该第一封装层55的第二表面55b。
于本实施例中，该第一封装层55的材质与该第二封装层26的材质可相同(图略)或不相同(如图5C所示)，抑或可同时形成该第一封装层55与该第二封装层26。
如图5D所示，于该些导电柱23的端面23b上形成有如焊球的导电元件27，以供接置如电路板的电子装置(图略)。
于本实施例中，可依据散热需求，该第一电子元件21与该结合垫53之间也可免用该结合层51，如图5D’所示。
此外，可借由该结合垫53的表面与该第一封装层55的第二表面55b共平面(齐平)，使该结合垫53外露出该第一封装层55的第二表面55b，如图5D所示；或者，可借由形成开口(图未示)于该第一封装层55的第二表面55b的方式，使该结合垫53外露出该开口。
请参阅图6A至图6E，其为本发明的电子封装件6的第五实施例的剖面示意图。本实施例与第四实施例的差异在于第一与第二封装层25,26的制程顺序。
如图6A所示，接续图2C所示的结构的制程，即已形成第一封装层25于承载结构20的第一侧20a上。
如图6B所示，设置第二电子元件22于承载结构20的第二侧20b上，再形成第二封装层26于该承载结构20的第二侧20b上，使该第二封装层26包覆该第二电子元件22。
于本实施例中，该第一封装层25的材质与该第二封装层26的材质可相同或不相同(图略)。
如图6C所示，进行整平制程，以移除部分该板体24、部分该第一封装层25的材质及该第一电子元件21的部分材质，使该导电柱23的端面23b与该第一封装层25的第二表面25b共平面(齐平)。
于本实施例中，是以切除方式一次整平；也可如图6C’所示，先以蚀刻方式移除部分该板体24、该第一封装层25的第二表面25b的部分材质，再以该研磨方式移除该第一电子元件21的非作用面21b的部分材质，使该第一电子元件21的非作用面21b与该第一封装层25的第二表面25b共平面(如图6C所示)。
如图6D所示，沿如图6C所示的切割路径S进行切单制程。
如图6E所示，形成一屏蔽件68于该第二封装层26的顶面26a与侧面26c及该第一封装层25的侧面25c，使该屏蔽件68接触及电性连接该承载结构20的线路层200，以避免外界电磁干扰(Electro-Magnetic Interference，简称EMI)该第一电子元件21与第二电子元件22。
于本实施例中，可借由溅镀(sputtering)、蒸镀(vaporing)、电镀、化镀或贴膜(foiling)等方式制作该屏蔽件68。
此外，于该些导电柱23的端面23b上形成有如焊球的导电元件27，以供接置如电路板或另一线路板的电子装置(图略)。
请参阅图7A至图7C，其为本发明的电子封装件7的第六实施例的剖面示意图。本实施例与第二实施例的差异在于第一电子元件21的设置方式。
如图7A所示，将第一电子元件21以其非作用面21b借由粘着层71结合承载结构30的第一侧30a，并于该第一电子元件21的作用面21a上设有多个导电凸块210，且令导电架2a设于该承载结构30的第一侧30a上。
如图7B所示，形成第一封装层25于该承载结构30的第一侧30a上，再进行整平制程，使该第一电子元件21的导电凸块210与该导电柱23的端面23b外露出该第一封装层25的第二表面25b。
如图7C所示，形成布线结构79于该第一封装层25的第二表面25b上，且该布线结构79电性连接该些导电柱23与该第一电子元件21。之后，移除该支撑板9及其离形膜90，以外露该承载结构30的第二侧30b。
于本实施例中，该布线结构79包括多个介电层790、及设于该介电层790上的多个线路重布层(RDL)791，且该线路重布层791电性连接该些导电柱23与该第一电子元件21的导电凸块210。例如，形成该线路重布层791的材质为铜，且形成该介电层790的材质为聚对二唑苯(PBO)、聚酰亚胺(PI)或预浸材(PP)。
此外，可形成多个如焊球的导电元件77于最外层的线路重布层791上，以供后续接置如封装结构或其它结构(如另一封装件或晶片)的电子装置(图略)。
又，可依需求形成防焊层202于该第二侧20b上，且可形成多个如焊球的导电元件27于该承载结构20的第二侧20b的线路层200上，以供后续接置如封装结构或半导体晶片的电子装置8。
综上，本发明的电子封装件的制法借由该导电架2a,5a的导电柱23取代悉知焊锡球，以依需求调整各该导电柱23之间的间距，故相较于悉知技术，该些导电柱23之间不会发生桥接的问题，因而能有效提高产品良率及可靠度，以达到细间距(fine pitch)的需求。
此外，本发明的导电架2a,5a的制作移除金属板的部分材质，以形成用以间隔各该导电柱23的凹部240，再将该导电架2a,5a设于该承载结构20,30上，故相较于悉知技术，本发明的制法可使该些导电柱23的高度一致，使该些导电柱23所排列成的栅状阵列的共面性良好，因而能避免于后续制程中产生接点偏移的问题。
又，该导电柱23具有相对的两端面23a,23b及邻接该两端面23a,23b的周面23c，且该周面23c的宽度小于该两端面23a,23b的宽度W，使该导电柱23的侧壁内凹，而能容纳该第一封装层25,55，以提供该第一封装层25,55与该导电柱23之间较佳的固定效果，故本发明的制法能避免因该第一封装层25,55与该导电柱23的结合性不佳而于后续制程发生脱层的问题。
本发明还提供一种电子封装件2,3,4,5,6,7，包括：一承载结构20,30、第一与第二电子元件21,22、多个导电柱23以及第一与第二封装层25,55,26。
所述的承载结构20,30具有相对的第一侧20a,30a与第二侧20b,30b。
所述的第一电子元件21与第二电子元件22设于该承载结构20,30的第一侧20a,30a与第二侧20b,30b上且电性连接该承载结构20,30。
所述的导电柱23设于该承载结构20,30的第一侧20a,30a上，其中，该导电柱23具有相对的两端面23a,23b及邻接该两端面23a,23b的周面23c，且该周面23c的宽度小于该两端面23a,23b的宽度W。
所述的第一封装层25,55包覆该第一电子元件21与该导电柱23。
所述的第二封装层26包覆该第二电子元件22。
于一实施例中，该导电柱23电性连接该承载结构20,30。
于一实施例中，该导电柱23借由导电体230结合至该承载结构20,30上。
于一实施例中，该第一封装层25具有相对的第一表面25a与第二表面25b，且其以第一表面25a结合于该承载结构20的第一侧20a上，并令该第一电子元件21的部分表面(非作用面21b)外露出该第一封装层25的第二表面25b。
于一实施例中，所述的电子封装件5还包括结合垫53，其嵌埋于该第一封装层55中且对应该第一电子元件21的位置并部分外露出该第一封装层55的第二表面55b。
于一实施例中，所述的电子封装件6还包括屏蔽件68，其遮盖该第一电子元件21与第二电子元件22。
于一实施例中，所述的电子封装件7还包括布线结构79，其设于该第一封装层25的第二表面25b上并电性连接该导电柱23与该第一电子元件21。
综上所述，本发明的电子封装件及其制法，可依需求调整各该导电柱之间的间距，故该些导电柱之间不会发生桥接的问题，因而能有效提高产品良率及可靠度，以达到细间距的需求。
此外，借由先制作该导电架，再将该导电架设于该承载结构上，故相较于悉知技术，本发明的制法可使该些导电柱的高度一致，使该些导电柱所排列成的栅状阵列的共面性良好，因而能避免于后续制程中产生接点偏移的问题。
又，该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度，使该导电柱的侧壁内凹，而可容纳该封装层，以提供较佳的固定效果，故能避免因该封装层与该导电柱的结合性不佳而于后续制程发生脱层的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (21)

1.一种电子封装件，其特征为，该电子封装件包括：
承载结构；
电子元件，其设于该承载结构上且电性连接该承载结构；
多个导电柱，其设于该承载结构上，其中，该导电柱具有相对的两端面及邻接该两端面的周面，且该周面的宽度小于该两端面的宽度；以及
封装层，其包覆该电子元件与该导电柱。
2.根据权利要求1所述的电子封装件，其特征为，该导电柱电性连接该承载结构。
3.根据权利要求1所述的电子封装件，其特征为，该导电柱借由导电体结合至该承载结构上。
4.根据权利要求1所述的电子封装件，其特征为，该承载结构具有相对的第一侧与第二侧，且该第一侧与该第二侧上均布设有该电子元件。
5.根据权利要求1所述的电子封装件，其特征为，该承载结构具有相对的第一侧与第二侧，且该第一侧与该第二侧上均布设有该封装层。
6.根据权利要求1所述的电子封装件，其特征为，该电子元件的部分表面外露出该封装层的表面。
7.根据权利要求1所述的电子封装件，其特征为，该电子封装件还包括结合垫，其嵌埋于该封装层中且对应该电子元件的位置并至少部分外露出该封装层的表面。
8.根据权利要求1所述的电子封装件，其特征为，该电子封装件还包括遮盖该电子元件的屏蔽件。
9.根据权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该封装层上并电性连接该导电柱的布线结构。
10.根据权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该封装层上并电性连接该电子元件的布线结构。
11.一种电子封装件的制法，其特征为，该制法包括：
将导电架及至少一电子元件设于一承载结构上，其中，该导电架包含有板体与多个连接该板体的导电柱，并以该导电柱结合于该承载结构上，且该导电柱具有相对的两端面及邻接该两端面的周面，而该周面的宽度小于该两端面的宽度；
以封装层包覆该电子元件与该导电柱；以及
移除该板体。
12.根据权利要求11所述的电子封装件的制法，其特征为，该导电柱电性连接该承载结构。
13.根据权利要求11所述的电子封装件的制法，其特征为，该导电柱借由导电体结合至该承载结构上。
14.根据权利要求11所述的电子封装件的制法，其特征为，该导电架的制作为移除金属板的部分材质，以形成用以间隔各该导电柱的凹部。
15.根据权利要求11所述的电子封装件的制法，其特征为，该承载结构具有相对的第一侧与第二侧，且该第一侧与该第二侧上均布设有该电子元件。
16.根据权利要求11所述的电子封装件的制法，其特征为，该承载结构具有相对的第一侧与第二侧，且该第一侧与该第二侧上均布设有该封装层。
17.根据权利要求11所述的电子封装件的制法，其特征为，该电子元件的部分表面外露出该封装层的表面。
18.根据权利要求11所述的电子封装件的制法，其特征为，该导电架还包含有结合垫，且该结合垫对应该电子元件的位置并至少部分外露出该封装层。
19.根据权利要求11所述的电子封装件的制法，其特征为，该制法还包括形成屏蔽件以遮盖该电子元件。
20.根据权利要求11所述的电子封装件的制法，其特征为，该制法还包括于移除该板体后，于该封装层上形成电性连接该导电柱的布线结构。
21.根据权利要求11所述的电子封装件的制法，其特征为，该制法还包括于移除该板体后，于该封装层上形成电性连接该电子元件的布线结构。
CN201810378273.8A 2018-03-06 2018-04-25 电子封装件及其制法 Pending CN110233112A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW107107457A TWI645527B (zh) 2018-03-06 2018-03-06 電子封裝件及其製法
TW107107457 2018-03-06

Publications (1)

Publication Number Publication Date
CN110233112A true CN110233112A (zh) 2019-09-13

Family

ID=65431538

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810378273.8A Pending CN110233112A (zh) 2018-03-06 2018-04-25 电子封装件及其制法

Country Status (3)

Country Link
US (1) US10410970B1 (zh)
CN (1) CN110233112A (zh)
TW (1) TWI645527B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017189224A1 (en) 2016-04-26 2017-11-02 Linear Technology Corporation Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
TWI700796B (zh) * 2019-05-23 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI791881B (zh) * 2019-08-16 2023-02-11 矽品精密工業股份有限公司 電子封裝件及其組合式基板與製法
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
KR20220000273A (ko) * 2020-06-25 2022-01-03 삼성전자주식회사 반도체 패키지
TWI731737B (zh) * 2020-07-03 2021-06-21 財團法人工業技術研究院 導線架封裝結構
TWI723932B (zh) * 2020-08-06 2021-04-01 強茂股份有限公司 側面可潤濕封裝元件及其製法
US20220084914A1 (en) * 2020-09-16 2022-03-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure
KR20220093507A (ko) * 2020-12-28 2022-07-05 삼성전기주식회사 패키지 내장기판
CN115472574A (zh) * 2021-06-10 2022-12-13 矽品精密工业股份有限公司 电子封装件及其制法
US20230093681A1 (en) * 2021-09-20 2023-03-23 Qualcomm Incorporated Package comprising a substrate with high density interconnects
US20230230854A1 (en) * 2022-01-18 2023-07-20 Wenkai Wu Power module packaging systems and fabrication methods
TWI807665B (zh) * 2022-03-03 2023-07-01 復盛精密工業股份有限公司 預成型導電柱結構及其製作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090011198A (ko) * 2007-07-25 2009-02-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그의 제조 방법
US20100052164A1 (en) * 2008-09-03 2010-03-04 Samsung Electro-Mechanics Co., Ltd. Wafer level package and method of manufacturing the same
US20100289126A1 (en) * 2009-05-18 2010-11-18 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame
US20110266668A1 (en) * 2005-02-25 2011-11-03 Tessera, Inc. Microelectronic assemblies having compliancy
US20110291249A1 (en) * 2010-05-26 2011-12-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe
CN103247578A (zh) * 2012-02-01 2013-08-14 矽品精密工业股份有限公司 半导体承载件暨封装件及其制法
CN203351587U (zh) * 2012-09-17 2013-12-18 新科金朋有限公司 半导体器件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8105872B2 (en) * 2010-06-02 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die
US8409922B2 (en) * 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US9991190B2 (en) * 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
TWI533421B (zh) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 半導體封裝結構及半導體製程
TWI571185B (zh) * 2014-10-15 2017-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
US10115647B2 (en) * 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US9875970B2 (en) * 2016-04-25 2018-01-23 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US9922896B1 (en) * 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110266668A1 (en) * 2005-02-25 2011-11-03 Tessera, Inc. Microelectronic assemblies having compliancy
KR20090011198A (ko) * 2007-07-25 2009-02-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그의 제조 방법
US20100052164A1 (en) * 2008-09-03 2010-03-04 Samsung Electro-Mechanics Co., Ltd. Wafer level package and method of manufacturing the same
US20100289126A1 (en) * 2009-05-18 2010-11-18 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame
US20110291249A1 (en) * 2010-05-26 2011-12-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe
CN103247578A (zh) * 2012-02-01 2013-08-14 矽品精密工业股份有限公司 半导体承载件暨封装件及其制法
CN203351587U (zh) * 2012-09-17 2013-12-18 新科金朋有限公司 半导体器件

Also Published As

Publication number Publication date
US10410970B1 (en) 2019-09-10
TWI645527B (zh) 2018-12-21
US20190279937A1 (en) 2019-09-12
TW201939696A (zh) 2019-10-01

Similar Documents

Publication Publication Date Title
CN110233112A (zh) 电子封装件及其制法
US11469201B2 (en) Semiconductor package and method for fabricating base for semiconductor package
US9177899B2 (en) Semiconductor package and method for fabricating base for semiconductor package
TWI587412B (zh) 封裝結構及其製法
TWI556400B (zh) 堆疊式扇出半導體晶片
TWI418003B (zh) 嵌埋電子元件之封裝結構及其製法
KR101478875B1 (ko) 반도체 다이를 패키징하는 패키지 온 패키지 장치 및 방법
CN110098169A (zh) 电子封装件及其制法
TWI544599B (zh) 封裝結構之製法
CN106328632B (zh) 电子封装件及其制法
CN107785334B (zh) 电子封装结构及其制法
US9595509B1 (en) Stacked microelectronic package assemblies and methods for the fabrication thereof
CN109390306A (zh) 电子封装件
JP2005150748A (ja) デカップリングコンデンサを有する半導体チップパッケージ及びその製造方法
US8791501B1 (en) Integrated passive device structure and method
US20150325509A1 (en) SUBSTRATE BLOCK FOR PoP PACKAGE
JP2009141169A (ja) 半導体装置
WO2013101243A1 (en) High density package interconnects
CN108630646A (zh) 电子封装件及其基板构造
CN108962840A (zh) 电子封装件及其制法
CN107403785B (zh) 电子封装件及其制法
TWI780081B (zh) 半導體元件及其製造方法
TWI636537B (zh) 扇出型多晶片堆疊封裝之電子裝置及形成該裝置之方法
TWI723414B (zh) 電子封裝件及其製法
TWI520278B (zh) 嵌埋有晶片之封裝結構的製法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20190913