TWI418003B - 嵌埋電子元件之封裝結構及其製法 - Google Patents

嵌埋電子元件之封裝結構及其製法 Download PDF

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TWI418003B
TWI418003B TW100114827A TW100114827A TWI418003B TW I418003 B TWI418003 B TW I418003B TW 100114827 A TW100114827 A TW 100114827A TW 100114827 A TW100114827 A TW 100114827A TW I418003 B TWI418003 B TW I418003B
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layer
opening
solder
package structure
electronic component
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TW201244034A (en
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Zhao Chong Zhng
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Unimicron Technology Corp
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Priority to CN2011103038632A priority patent/CN102760715A/zh
Priority to US13/352,664 priority patent/US8884429B2/en
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Priority to US14/314,242 priority patent/US9129870B2/en

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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L2924/11—Device type
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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Description

嵌埋電子元件之封裝結構及其製法
　　本發明係有關一種封裝結構，尤指一種嵌埋電子元件之封裝結構及其製法。
　　隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為滿足封裝結構高積集度(Integration)以及微型化(Miniaturization)的封裝需求，封裝形式遂發展出打線式(Wire bonding)或覆晶式(Flip Chip)封裝形態，其主要係將晶片藉由金線電性連接導線架、或將晶片藉由焊錫凸塊電性連接封裝基板。
　　如第1圖所示，係為一習知覆晶式封裝結構之剖面圖，該封裝結構1係包括：一封裝基板10，係具有覆晶面10a與植球面10b，該覆晶面10a上具有焊錫凸塊100；晶片11，係藉由錫球110對應覆晶結合於該焊錫凸塊100上；以及焊球16，係形成於該植球面10b上。
　　然，習知覆晶封裝結構1中，該封裝基板10之線路係微小等級，使該晶片11之錫球110的間距無法縮小，而使該封裝結構1難以滿足微型化之需求。
　　再者，於覆晶製程中，該封裝基板10需形成焊錫凸塊100，且該晶片11需形成錫球110，使得當封裝結構1作用時，該晶片11與封裝基板10之間的訊號傳輸路徑過長，且傳輸時需經過不同介質（焊錫凸塊100與錫球110），因而導致訊號容易損失。
　　因此，如何克服上述習知技術中之種種問題，實已成目前亟欲解決的課題。
　　鑑於上述習知技術之缺失，本發明提供一種嵌埋電子元件之封裝結構，係包括：承載板，係具有開口與金屬層，且令該金屬層覆蓋於該開口之一端；晶片，係收納於該開口中，且具有相對之作用面與非作用面，該作用面上具有複數電極墊，且各該電極墊上具有焊錫凸塊，而該非作用面係接置於該金屬層上；介電層，係覆於該承載板及晶片上且包覆該焊錫凸塊，並填入該晶片與該開口壁面之間，又該介電層具有複數通孔，以對應外露該焊錫凸塊；線路層，係設於該介電層上，且具有複數電性接觸墊；絕緣保護層，係敷設於該介電層與線路層上，且具有複數第一開孔，令該第一開孔連通該通孔而外露該焊錫凸塊；以及焊錫材，係填充於該第一開孔與該通孔中，以電性連接該線路層與該焊錫凸塊。
　　前述之封裝基板中，該絕緣保護層復具有複數第二開孔，令該些電性接觸墊對應外露各該第二開孔，俾供設置焊球。
　　本發明復提供一種嵌埋電子元件之封裝結構，係包括：承載板，係具有開口與金屬層，且令該金屬層覆蓋於該開口之一端；晶片，係收納於該開口中，且具有相對之作用面與非作用面，該作用面上具有複數電極墊，且各該電極墊上具有焊錫凸塊，而該非作用面係接置於該金屬層上；介電層，係覆於該承載板及晶片上且包覆該焊錫凸塊，並填入該晶片與該開口壁面之間；線路層，係設於該介電層上，且具有複數電性接觸墊及位於該介電層中並電性連接該焊錫凸塊之導電盲孔；以及絕緣保護層，係敷設於該介電層與線路層上，且具有複數開孔，以令該電性接觸墊對應外露於各該開孔中。
　　前述之兩種封裝基板中，該金屬層可為銅層。
　　由上可知，本發明嵌埋電子元件之封裝結構，係藉由將晶片收納於該承載板之開口中，使該焊錫材或導電盲孔可電性連接該線路層與該晶片上之焊錫凸塊，以縮短該晶片與承載板之間的訊號傳輸路徑，且傳輸時經過相同介質，故可避免訊號損失。
　　再者，因該晶片嵌埋於該承載板中，故該導電盲孔或焊錫材之間距可配合該晶片上之焊錫凸塊之間距，使該焊錫凸塊的間距可依需求而縮小，且該線路層之間的間距亦可一併縮小，因而可滿足微型化之需求。
　　另外，本發明復提供一種嵌埋電子元件之封裝結構之製法，如後所述。
　　以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
　　須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
　　請參閱第2A至2G圖，係為本發明嵌埋電子元件之封裝結構之製法剖面示意圖。
　　如第2A圖所示，首先，提供一具有開口200之承載板20，該承載板20復具有覆蓋於該開口200之一側之金屬層201。於本實施例中，該承載板20係為銅箔基板，該金屬層201係為銅層。
　　如第2B圖所示，提供一具有相對之作用面21a與非作用面21b之晶片21，該作用面21a上具有複數電極墊210，且於各該電極墊210上具有焊錫凸塊211，將該晶片21收納於該開口200中，且該非作用面21b藉由一黏著層212結合於該金屬層201上。於本實施例中，該作用面21a上敷設一保護層213，以覆蓋該電極墊210且與該焊錫凸塊211齊平。
　　如第2C圖所示，於該承載板20及晶片21上形成一介電層22，以包覆該焊錫凸塊211，且該介電層22復填入於該晶片21與該開口200壁面之間。
　　如第2D圖所示，於該介電層22上沉積銅層，再藉由圖案化製程，使該銅層形成具有複數電性接觸墊230之線路層23。
　　如第2E圖所示，於該介電層22上藉由雷射方式形成複數通孔220，以對應外露該些焊錫凸塊211，且該些通孔220之孔緣係連接該線路層23。
　　如第2F圖所示，於該介電層22與線路層23上形成一絕緣保護層24，該絕緣保護層24並形成有複數第一開孔240，以令該第一開孔240連通該通孔220而外露該焊錫凸塊211。於本實施例中，該絕緣保護層24復具有複數第二開孔241，以令該些電性接觸墊230對應外露各該第二開孔241。
　　如第2G圖所示，於該第一開孔240與該通孔220中填充焊錫材25，以電性連接該線路層23與該焊錫凸塊211，且將複數焊球26植接於各該電性接觸墊230上。
　　如第2F'及2G'圖所示，該第一開孔240'係可連通該第二開孔241'，使該些焊球26'接觸該焊錫材25'。
　　本發明之製法，係先將該晶片21收納於該承載板20之開口200中，再形成線路層23，接著藉由焊錫材25電性連接該線路層23與該焊錫凸塊211，以縮短該晶片21與承載板20之間的訊號傳輸路徑，且傳輸時僅經過一種介質（即焊錫材25），故可避免訊號損失。
　　再者，因該晶片21嵌埋於該承載板20中，故該通孔220之間距係可配合該焊錫凸塊211之間距，使該焊錫凸塊211的間距可依需求縮小，而該晶片21之體積將可更薄小，以滿足微型化之需求。
　　又，該線路層23之間的間距亦可一併縮小。
　　請參閱第3A至3C圖，係為本發明之另一種製法之剖面示意圖。本實施例係接續上述實施例之第2C圖的製程，且兩者相異處在於電性連接焊錫凸塊與線路層之方式，故有關本發明封裝結構之相同製程將不再贅述，以下僅說明相異處之製程。
　　如第3A圖所示，於該介電層32中形成複數盲孔320，以對應外露該晶片21之焊錫凸塊211。
　　如第3B圖所示，於該介電層32上形成具有電性接觸墊330之線路層33，且於該盲孔320中形成導電盲孔331以電性連接該線路層33與焊錫凸塊211。
　　如第3C圖所示，於該介電層32與線路層33上形成絕緣保護層34，該絕緣保護層34並形成有複數開孔340，以令該電性接觸墊330對應外露於該開孔340中，再將複數焊球26植接於各該電性接觸墊330上。
　　本發明之製法，係藉由導電盲孔331電性連接該線路層33與該焊錫凸塊211，以縮短該晶片21與承載板20之間的訊號傳輸路徑，且傳輸時僅經過一種介質（即導電盲孔331），故可避免訊號損失。
　　再者，該線路層33與該導電盲孔331係為相同材質，例如銅，故可減少焊錫材料之使用量，因而節省製作成本。
　　綜上所述，本發明嵌埋電子元件之封裝結構，主要藉由該焊錫材或導電盲孔可電性連接該線路層與該晶片，以縮短該晶片與承載板之間的訊號傳輸路徑，故可避免訊號損失。
　　再者，因該晶片嵌埋於該承載板中，故該導電盲孔或焊錫材之間距可配合該焊錫凸塊之間距，使該焊錫凸塊的間距可依需求縮小，因而可滿足微型化之需求。
　　上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1‧‧‧封裝結構
10‧‧‧封裝基板
10a‧‧‧覆晶面
10b‧‧‧植球面
100、211‧‧‧焊錫凸塊
11、21‧‧‧晶片
110‧‧‧錫球
16、26、26’‧‧‧焊球
20‧‧‧承載板
200‧‧‧開口
201‧‧‧金屬層
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧電極墊
212‧‧‧黏著層
213‧‧‧保護層
22、32‧‧‧介電層
220‧‧‧通孔
23、33‧‧‧線路層
230、330‧‧‧電性接觸墊
24、34‧‧‧絕緣保護層
240、240’‧‧‧第一開孔
241、241’‧‧‧第二開孔
25、25’‧‧‧焊錫材
320‧‧‧盲孔
331‧‧‧導電盲孔
340‧‧‧開孔
　　第1圖係為習知覆晶式封裝結構之剖面圖；
　　第2A至2G圖係為本發明嵌埋電子元件之封裝結構之製法的剖面示意圖；其中，第2F'及2G'圖係為第2F及2G圖之另一實施態樣；以及
　　第3A至3C圖係為本發明嵌埋電子元件之封裝結構之製法之另一實施例的剖面示意圖。
20‧‧‧承載板
200‧‧‧開口
201‧‧‧金屬層
21‧‧‧晶片
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧電極墊
211‧‧‧焊錫凸塊
22‧‧‧介電層
220‧‧‧通孔
23‧‧‧線路層
230‧‧‧電性接觸墊
24‧‧‧絕緣保護層
240‧‧‧第一開孔
241‧‧‧第二開孔
25‧‧‧焊錫材
26‧‧‧焊球

Claims (9)

  1. 一種嵌埋電子元件之封裝結構，係包括：承載板，係具有開口與金屬層，且令該金屬層覆蓋於該開口之一端；晶片，係收納於該開口中，且具有相對之作用面與非作用面，該作用面上具有複數電極墊，且各該電極墊上具有焊錫凸塊，而該非作用面係接置於該金屬層上；介電層，係覆於該承載板及晶片上且包覆該焊錫凸塊，並填入該晶片與該開口壁面之間，又該介電層具有複數通孔，以對應外露該焊錫凸塊；線路層，係設於該介電層上，且具有複數電性接觸墊；絕緣保護層，係敷設於該介電層與線路層上，且具有複數第一開孔，令該第一開孔連通該通孔而外露該焊錫凸塊；以及焊錫材，係填充於該第一開孔與該通孔中，以電性連接該線路層與該焊錫凸塊。
  2. 如申請專利範圍第1項所述之嵌埋電子元件之封裝結構，其中，該金屬層係為銅層。
  3. 如申請專利範圍第1項所述之嵌埋電子元件之封裝結構，其中，該絕緣保護層復具有複數第二開孔，令該些電性接觸墊對應外露各該第二開孔，俾供設置焊球。
  4. 如申請專利範圍第3項所述之嵌埋電子元件之封裝結構，其中，該第一開孔係連通該第二開孔，以使該些焊 球接觸該焊錫材。
  5. 一種嵌埋電子元件之封裝結構之製法，係包括：提供一具有開口之承載板，該承載板復具有覆蓋於該開口之一側之金屬層；將一具有相對之作用面與非作用面之晶片收納於該開口中，使該非作用面接置於該金屬層上，該晶片之作用面上並具有複數電極墊，且各該電極墊上具有焊錫凸塊；於該承載板及晶片上形成介電層，以包覆該焊錫凸塊，且該介電層復填入於該晶片與該開口壁面之間；於該介電層上形成具有複數電性接觸墊之線路層；於該介電層上形成複數通孔，以對應外露各該焊錫凸塊，且該通孔之孔緣連接該線路層；於該介電層與線路層上形成絕緣保護層，該絕緣保護層並形成有複數第一開孔，以令該第一開孔連通該通孔而外露該焊錫凸塊；以及於該第一開孔與該通孔中填充焊錫材，以電性連接該線路層與該焊錫凸塊。
  6. 如申請專利範圍第5項所述之嵌埋電子元件之封裝結構之製法，其中，該承載板係為銅箔基板，且該金屬層係為銅層。
  7. 如申請專利範圍第5項所述之嵌埋電子元件之封裝結構之製法，其中，該絕緣保護層復具有複數第二開孔，以令該些電性接觸墊對應外露於各該第二開孔中。
  8. 如申請專利範圍第7項所述之嵌埋電子元件之封裝結構之製法，復包括於該電性接觸墊上形成焊球。
  9. 如申請專利範圍第8項所述之嵌埋電子元件之封裝結構之製法，其中，該第一開孔係連通該第二開孔，以使該些焊球接觸該焊錫材。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US8633588B2 (en) 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
US9659893B2 (en) 2011-12-21 2017-05-23 Mediatek Inc. Semiconductor package
KR102033788B1 (ko) * 2013-06-13 2019-10-17 에스케이하이닉스 주식회사 칩 내장형 패키지 및 그 제조방법
EP3036766A4 (en) 2013-08-21 2017-09-06 Intel Corporation Bumpless die-package interface for bumpless build-up layer (bbul)
CN107658284B (zh) * 2013-10-25 2020-07-14 日月光半导体制造股份有限公司 半导体封装件及其制造方法
TWI556395B (zh) * 2015-03-25 2016-11-01 恆勁科技股份有限公司 電子封裝件及其製法
TWI591768B (zh) * 2015-11-30 2017-07-11 矽品精密工業股份有限公司 封裝結構及其製法
KR102595276B1 (ko) 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
CN106971993B (zh) 2016-01-14 2021-10-15 三星电子株式会社 半导体封装件
US9887167B1 (en) * 2016-09-19 2018-02-06 Advanced Semiconductor Engineering, Inc. Embedded component package structure and method of manufacturing the same
CN107170731A (zh) * 2017-05-05 2017-09-15 华为技术有限公司 嵌入式基板及其制造方法
KR101901712B1 (ko) * 2017-10-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지
EP3522685B1 (en) 2018-02-05 2021-12-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Metallic layer as carrier for component embedded in cavity of component carrier
EP3723459A1 (en) 2019-04-10 2020-10-14 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with high passive intermodulation (pim) performance
US11462509B2 (en) * 2019-10-29 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with electronic device in cavity substrate and method for forming the same
EP3866187A1 (en) * 2020-02-12 2021-08-18 Infineon Technologies Austria AG A semiconductor device comprising an embedded semiconductor die and a method for fabricating the same
CN115763400A (zh) * 2022-11-24 2023-03-07 成都海光集成电路设计有限公司 一种芯片扇出封装方法及芯片扇出封装件
CN118039597A (zh) * 2024-01-17 2024-05-14 苏州纳芯微电子股份有限公司 一种埋嵌芯片基板结构及制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080029895A1 (en) * 2006-08-02 2008-02-07 Phoenix Precision Technology Corporation Carrier board structure with embedded semiconductor chip and fabrication method thereof
TW200947646A (en) * 2008-05-05 2009-11-16 Phoenix Prec Technology Corp Package substrate having semiconductor component embedded therein and fabrication method thereof
TW201001662A (en) * 2008-06-19 2010-01-01 Phoenix Prec Technology Corp Substrate having semiconductor chip embedded therein and fabrication method thereof
US7705446B2 (en) * 2006-07-25 2010-04-27 Phoenix Precision Technology Corporation Package structure having semiconductor chip embedded therein and method for fabricating the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW546800B (en) * 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
TWI260079B (en) * 2004-09-01 2006-08-11 Phoenix Prec Technology Corp Micro-electronic package structure and method for fabricating the same
TWI283050B (en) * 2005-02-04 2007-06-21 Phoenix Prec Technology Corp Substrate structure embedded method with semiconductor chip and the method for making the same
KR101058621B1 (ko) * 2009-07-23 2011-08-22 삼성전기주식회사 반도체 패키지 및 이의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7705446B2 (en) * 2006-07-25 2010-04-27 Phoenix Precision Technology Corporation Package structure having semiconductor chip embedded therein and method for fabricating the same
US20080029895A1 (en) * 2006-08-02 2008-02-07 Phoenix Precision Technology Corporation Carrier board structure with embedded semiconductor chip and fabrication method thereof
TW200947646A (en) * 2008-05-05 2009-11-16 Phoenix Prec Technology Corp Package substrate having semiconductor component embedded therein and fabrication method thereof
TW201001662A (en) * 2008-06-19 2010-01-01 Phoenix Prec Technology Corp Substrate having semiconductor chip embedded therein and fabrication method thereof

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