TWI760629B - 電子封裝件及其導電基材與製法 - Google Patents

電子封裝件及其導電基材與製法 Download PDF

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TWI760629B
TWI760629B TW108124913A TW108124913A TWI760629B TW I760629 B TWI760629 B TW I760629B TW 108124913 A TW108124913 A TW 108124913A TW 108124913 A TW108124913 A TW 108124913A TW I760629 B TWI760629 B TW I760629B
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insulating film
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林偉勝
陳漢宏
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矽品精密工業股份有限公司
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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Abstract

一種導電基材，係於一絕緣膜中配置複數外露之導電元件，以於封裝製程中，只需將半導體晶片與封裝基板分別設於該絕緣膜之相對兩表面上，即可使該半導體晶片藉由該導電元件電性連接該封裝基板，以完成封裝製程，而無需先於半導體晶片上形成銲錫凸塊，故本發明無需採買植設銲錫凸塊之機台，有效降低製作電子封裝件之成本。

Description

電子封裝件及其導電基材與製法
本發明係有關一種半導體封裝技術，尤指一種電子封裝件及其導電基材與製法。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)以及微型化(Miniaturization)需求，除傳統打線式(Wire bonding)之半導體封裝技術外，業界主要藉由覆晶(Flip chip)方式，以提升半導體裝置之佈線密度。
第1A至1B圖係為習知覆晶式封裝結構1之製法之剖視示意圖。如第1A圖所示，先將一半導體晶片11藉由複數銲錫凸塊13結合至一封裝基板10之電性接觸墊100上，再回銲該銲錫凸塊13。接著，如第1B圖所示，形成底膠14於該半導體晶片11與該封裝基板10之間，以包覆該些銲錫凸塊13。
於結合該銲錫凸塊13至該電性接觸墊100之前，該銲錫凸塊13之外表面上通常會形成氧化層，故於回銲該銲錫凸塊13的過程中，需使用助銲劑(圖略)移除該氧化物。
然而，習知覆晶式封裝結構1之製法中，需先於該半導體晶片11(或該封裝基板10)上形成該複數銲錫凸塊13，而用於植設該複數銲錫凸塊13之機台昂貴，故習知製法之成本難以降低。
再者，由於需使用助銲劑，因而於回銲過程中會殘留助銲劑之部分材料於該封裝結構1上，進而產生粗大銲接空隙，致使該銲錫凸塊13與該電性接觸墊100之間的接合失效，造成該封裝結構1的可靠性不佳。
又，若該銲錫凸塊13之直徑極小，則在沾附助銲劑時，部分該銲錫凸塊13會有沾附不完全的問題。
因此，如何克服上述習知技術之種種問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明提供一種導電基材，係包括：一絕緣膜，係具有相對之第一表面與第二表面；以及複數導電元件，係配置於該絕緣膜中且外露於該絕緣膜之第一表面與第二表面。
前述之導電基材中，該絕緣膜係設有複數供置放該複數導電元件之開孔。
本發明復提供一種導電基材之製法，係包括：提供一具有複數開孔之絕緣膜；以及設置導電元件於該開孔中。
前述之導電基材及其製法中，復包括形成助銲材於該開孔中，以令該助銲材包覆該導電元件，使該導電元件表面係覆蓋有助銲材。
前述之導電基材及其製法中，該導電元件係為銲錫結構、金屬柱或導電塊體。
前述之導電基材及其製法中，復包括於該絕緣膜中配置支撐件。例如，形成該支撐件之材質係為導電材。或者，該支撐件係與該導電元件之構造相同。
本發明亦提供一種電子封裝件，係包括：如前述之導電基材；承載結構，係設於該絕緣膜之第二表面上；以及電子元件，係設於該絕緣膜之第一表面上，使該電子元件藉由該導電元件電性連接該承載結構。
由上可知，本發明之電子封裝件及其導電基材與製法中，主要藉由在絕緣膜之開孔中設置導電元件以構成導電基材之設計，以於電子元件接合承載結構時，只需將該電子元件與該承載結構分別設於該絕緣膜之第一表面與第二表面上，即可使該電子元件藉由該導電元件電性連接該承載結構，以完成封裝製程，因而無需先於該電子元件或該承載結構上形成習知銲錫凸塊，故相較於習知技術，本發明之製法無需採買植設銲錫凸塊之機台，因而可有效降低製作該電子封裝件之成本。
再者，藉由將該助銲材設於該開孔中，使該開孔限制該助銲材之佈設範圍，以令該助銲材不會溢流出預定區域，因而於回銲該導電元件後，該助銲材與該導電元件會於該開孔中相融合，故相較於習知技術，本發明可避免該助銲材殘留於該電子封裝件上，因而不會產生粗大銲 接空隙，進而可避免該導電元件的接合失效之問題，以達到提升該電子封裝件的可靠性之目的。
又，當該導電元件之最大寬度很小時，於回銲該導電元件後，該助銲材與該導電元件會於該開孔中相融合，故相較於習知技術，本發明可避免該導電元件沾附不完全的問題。
1‧‧‧封裝結構
10‧‧‧封裝基板
100‧‧‧電性接觸墊
11‧‧‧半導體晶片
13‧‧‧銲錫凸塊
14‧‧‧底膠
2‧‧‧電子封裝件
2a,2b,2c‧‧‧導電基材
20‧‧‧承載結構
200‧‧‧電性接點
21‧‧‧電子元件
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧電極墊
23,23’‧‧‧導電元件
23”‧‧‧支撐件
24‧‧‧絕緣膜
24a‧‧‧第一表面
24b‧‧‧第二表面
240‧‧‧開孔
25‧‧‧助銲材
d‧‧‧寬度
第1A至1B圖係為習知覆晶式封裝結構之製法的剖視示意圖。
第2A至2E圖係為本發明之電子封裝件之製法之剖視示意圖。
第2E’及2E”圖係為第2E圖之不同實施例之剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、“上”、及 “一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之電子封裝件2之製法之剖視示意圖。
如第2A圖所示，提供一具有複數開孔240之絕緣膜24，其具有相對之第一表面24a與第二表面24b，以令該開孔240貫穿該絕緣膜24而連通該第一表面24a與第二表面24b。
於本實施例中，該絕緣膜24係為膠帶或其它黏性件，且利用雷射、機鑽或其它方式形成該開孔240。
如第2B圖所示，設置導電元件23於各該開孔240中。
於本實施例中，該導電元件23係例如為銲錫凸塊或銲球，並利用例如真空吸附方式，將該些導電元件23置放於各該開孔240中。
如第2C圖所示，形成助銲材25於各該開孔240中，以令該助銲材25包覆該導電元件23，俾形成一導電基材2a。
如第2D圖所示，提供一電子元件21及一具有複數電性接點200之承載結構20。
於本實施例中，該承載結構20係為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構，如封裝基板，其係於介電材上形成線路層，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。具體地，該電性接點200係設於該承載結構20之置晶側。應可理解地，該承載結構20亦可為其它可供承載如晶片等電子元件之承載單元，例如導線架(lead-frame)或矽中介板(silicon interposer)等載件，並不限於上述。
再者，該電子元件21係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。本實施例中，該電子元件21係為半導體晶片，其具有作用面21a與相對該作用面21a之非作用面21b，該作用面21a上具有複數電極墊210。
如第2E圖所示，將該電子元件21以其作用面21a黏貼於該絕緣膜24之第一表面24a上，且該絕緣膜24之第二表面24b係黏貼該承載結構20，以令該電極墊210與該電性接點200均對應接觸該導電元件23，使該電子元件21藉由該導電基材2a覆晶接合於該承載結構20上。
於本實施例中，回銲該導電元件23與助銲材25，使該導電元件23凸出該絕緣膜24之第一表面24a與第二表面24b，以利於該導電元件23電性連接該電極墊210與該電性接點200。
再者，於另一實施例中，如第2E’圖所示之導電基材2b，其導電元件23’係為金屬柱(如銅柱)或其它導電塊體(如銅核心球，其係由銲錫凸塊包覆銅塊體所構成)，且免用助銲材25。例如，於該開孔240中電鍍或沉積金屬材，以形成金屬柱，俾作為該導電元件23’；或者，利用真空吸附方式，將銅核心球置放於各該開孔240中。
又，於其它實施例中，如第2E”圖所示之導電基材2c，其絕緣膜24中可配置有至少一支撐件23”，其接觸支撐該電子元件21與該承載結構20，而未電性連接該電子元件21(或該電極墊210)與該承載結構20(或該電性接點200)。具體地，該支撐件23”係為銲錫結構、金屬柱或其它導電塊體，其於進行回銲作業時呈虛銲狀態，且該支撐件23”接觸該電子元件21與該承載結構20，故能避免空氣殘存於該絕緣膜24中、爬膠、溢膠等問題。例如，該支撐件23”係與該導電元件23一同製作，即該 支撐件23”係與該導電元件23之構造相同。應可理解地，該支撐件23”與該導電元件23之構造亦可不相同。
因此，本發明之製法係藉由該導電基材2a,2b,2c之設計，以於該電子元件21接合該承載結構20時，只需將該電子元件21與該承載結構20分別設於該絕緣膜24之第一表面24a與第二表面24b上，即可使該電子元件21藉由該導電元件23,23’電性連接該承載結構20，以完成封裝製程，因而無需先於該電子元件21上(或該承載結構20上)形成習知銲錫凸塊，故相較於習知技術，本發明之製法無需採買植設銲錫凸塊之機台，因而能有效降低製作該電子封裝件2之成本。
再者，藉由將該助銲材25設於該開孔240中，使該開孔240限制該助銲材25之範圍，以令該助銲材25不會溢流出預定區域，因而於回銲該導電元件23後，該助銲材25與該導電元件23會於該開孔240中相融合，故相較於習知技術，本發明之製法能避免該助銲材25殘留於該電子封裝件2上，因而不會產生粗大銲接空隙，進而能避免該導電元件23與該電性接點200(或該電極墊210)之間的接合失效之問題，以達到提升該電子封裝件2的可靠性之目的。
又，當該導電元件23之最大寬度d(如第2B圖所示之直徑)很小(如小於25微米)時，於回銲該導電元件23後，該助銲材25與該導電元件23會於該開孔240中相融合，使該導電元件23與該電性接點200(或該電極墊210)之間完整結合，故相較於習知技術，本發明之製法能避免該導電元件23沾附不完全的問題。
本發明提供一種電子封裝件2，係包括：一導電基材2a,2b,2c、一承載結構20以及一電子元件21。
所述之導電基材2a,2b,2c係包括：一絕緣膜24以及複數配置於該絕緣膜24中之導電元件23,23’，且該絕緣膜24係具有相對之第一表面24a與第二表面24b，以令該複數導電元件23,23’外露於該絕緣膜24之第一表面24a與第二表面24b。
所述之承載結構20係設於該絕緣膜24之第二表面24b上。
所述之電子元件21係設於該絕緣膜24之第一表面24a上，使該電子元件21藉由該導電元件23,23’電性連接該承載結構20。
於一實施例中，該絕緣膜24係具有複數置放該些導電元件23,23’之開孔240。
於一實施例中，該導電元件23表面係覆蓋有助銲材25。
於一實施例中，該導電元件23,23’係為銲錫結構、金屬柱或導電塊體。
於一實施例中，所述之導電基材2c復包括至少一配置於該絕緣膜24中之支撐件23”。例如，形成該支撐件23”之材質係為導電材。 或者，該支撐件23”係與該導電元件23,23’之構造相同。
綜上所述，本發明之電子封裝件及其導電基材與製法中，藉由在絕緣膜之開孔中設置導電元件以構成導電基材之設計，可避免該導電元件與承載結構之電性接點或電子元件之電極墊之間的接合不佳之問題，故本發明能提高產品之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
2a‧‧‧導電基材
20‧‧‧承載結構
21‧‧‧電子元件
21a‧‧‧作用面
210‧‧‧電極墊
23‧‧‧導電元件
24‧‧‧絕緣膜
24a‧‧‧第一表面
24b‧‧‧第二表面
25‧‧‧助銲材

Claims (10)

  1. 一種導電基材，係包括：一絕緣膜，係具有相對之第一表面與第二表面，且該絕緣膜係設有複數開孔，以令該複數開孔貫穿該絕緣膜而連通該第一表面與第二表面；複數導電元件，係配置於該絕緣膜之該複數開孔中且外露於該絕緣膜之第一表面與第二表面；以及助銲材，係形成於該複數開孔中，以令該助銲材包覆該複數導電元件。
  2. 如申請專利範圍第1項所述之導電基材，其中，該導電元件係為銲錫結構、金屬柱或導電塊體。
  3. 如申請專利範圍第1項所述之導電基材，復包括配置於該絕緣膜中之支撐件。
  4. 如申請專利範圍第3項所述之導電基材，其中，形成該支撐件之材質係為導電材。
  5. 如申請專利範圍第3項所述之導電基材，其中，該支撐件係與該導電元件之構造相同。
  6. 一種電子封裝件之製法，係包括：提供一具有複數開孔之絕緣膜；設置複數導電元件於該開孔中；形成助銲材於該開孔中，以令該助銲材包覆該導電元件，以形成一導電基材；以及將電子元件設於該導電基材的該絕緣膜之其中一表面上，且該導電基材的該絕緣膜之另一表面係設置承載結構，並使該助銲材與該導電元件於該開孔中 相融合，以令該電子元件與該承載結構均對應接觸該導電元件，使該電子元件藉由該複數導電元件電性連接該承載結構。
  7. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該導電元件係為銲錫結構、金屬柱或導電塊體。
  8. 如申請專利範圍第6項所述之電子封裝件之製法，復包括於該絕緣膜中配置支撐件。
  9. 如申請專利範圍第8項所述之電子封裝件之製法，其中，形成該支撐件之材質係為導電材。
  10. 如申請專利範圍第8項所述之電子封裝件之製法，其中，該支撐件係與該導電元件之構造相同。
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