TW201637139A - 電子封裝結構及電子封裝件之製法 - Google Patents

電子封裝結構及電子封裝件之製法 Download PDF

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TW201637139A
TW201637139A TW104111896A TW104111896A TW201637139A TW 201637139 A TW201637139 A TW 201637139A TW 104111896 A TW104111896 A TW 104111896A TW 104111896 A TW104111896 A TW 104111896A TW 201637139 A TW201637139 A TW 201637139A
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electronic
glass carrier
electronic package
line portion
manufacturing
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TW104111896A
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陳賢文
陳仕卿
黃曉君
馬光華
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矽品精密工業股份有限公司
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Priority to TW104111896A priority Critical patent/TW201637139A/zh
Priority to CN201510303966.7A priority patent/CN106206477A/zh
Priority to US14/981,588 priority patent/US20160307833A1/en
Publication of TW201637139A publication Critical patent/TW201637139A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

一種電子封裝結構，係包括：線路部、設於該線路部上側之電子元件、以及設於該線路部下側上之玻璃承載件，故能利用離形膜將該玻璃承載件結合至該線路部上，而無需使用黏著層，以利於後續製程中能快速移除該玻璃承載件，因而節省製程時間，俾增加產能。本發明復提供電子封裝件之製法。

Description

電子封裝結構及電子封裝件之製法
本發明係有關一種電子封裝件之製法，尤指一種提升產能之電子封裝件之製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。目前應用於晶片封裝領域之技術，包括例如晶圓尺寸構裝(Wafer Scale Package，簡稱CSP)、晶片直接貼附封裝(Direct Chip Attached，簡稱DCA)或多晶片模組封裝(Multi-Chip Module，簡稱MCM)等覆晶型態的封裝模組。
第1A至1F圖係為習知半導體封裝件1之製法的剖面示意圖。
如第1A圖所示，提供一半導體結構，該半導體結構包含一具有如氧化材之黏著層100之矽晶圓10、形成於該黏著層100上之一線路部11、覆晶結合於該線路部11上之複數半導體晶片12、及形成於該線路部11與各該半導體晶片12之間的底膠13。
如第1B圖所示，形成一封裝膠體14於該線路部11 上以包覆各該半導體晶片12與該底膠13。
如第1C圖所示，移除該封裝膠體14之頂部材質以外露出該半導體晶片12。
如第1D圖所示，薄化該矽晶圓10，即形成較薄之矽晶圓10’，例如，該矽晶圓10未研磨前的厚度h約700微米(um)(如第1C圖所示)，而研磨後的矽晶圓10’之厚度h’為50微米。具體地，一般會以機械研磨方式使該該矽晶圓10’之厚度h’剩下50微米。
如第1E圖所示，蝕刻移除剩餘之矽晶圓10’，再形成複數開孔15於該黏著層100上，以外露該線路部11之電性接觸墊110。接著，形成一如聚對二唑苯(Polybenzoxazole，簡稱PBO)之絕緣保護層17於該線路部11上，且該絕緣保護層17外露部分該線路部11，以形成凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)180於該電性接觸墊110上，俾供結合複數如銲球之導電元件18。
如第1F圖所示，沿如第1E圖所示之切割路徑S進行切單製程，以獲得複數半導體封裝件1。
惟，習知半導體封裝件1之製法中，以化學蝕刻方式移除剩下之矽晶圓10’，將耗費大量時間，致使產能(throughput)大幅下降，而提高生產成本。
再者，於移除該矽晶圓10’後，該黏著層100仍覆蓋該些電性接觸墊110，故需以化學方式移除部分該黏著層100之材質而形成開孔15，才能植設該導電元件18或連接 其它裝置，致使產能大幅下降，因而提高生產成本。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝結構，係包括：線路部，係具有相對之第一側與第二側；至少一電子元件，係設於該線路部之第一側上；以及玻璃承載件，係設於該線路部之第二側上。
前述之電子封裝結構中，復包括封裝層，係形成於該線路部之第一側以包覆該電子元件。
本發明復提供一種電子封裝件之製法，係包括：提供一電子結構，該電子結構包含玻璃承載件、設於該玻璃承載件上之線路部、及結合於該線路部上之至少一電子元件；形成封裝層於該線路部之第一側上以包覆該電子元件；以及移除該玻璃承載件。
前述之製法中，復包括於移除該玻璃承載件後，形成複數導電元件於該線路部上。
前述之製法中，復包括於移除該玻璃承載件後，進行切單製程。
前述之電子封裝結構及電子封裝件之製法中，該電子結構復包含形成於該線路部與該電子元件之間的底膠。
前述之電子封裝結構及電子封裝件之製法中，該玻璃承載件藉由離形膜結合於該線路部之第二側上，以藉由該離形膜移除該玻璃承載件。
前述之電子封裝結構及電子封裝件之製法中，復包括移除該封裝層之部分材質，以外露出該電子元件。
由上可知，本發明之電子封裝結構及電子封裝件之製法，主要藉由玻璃承載件取代矽晶圓，以避免使用黏著層，故利於移除該玻璃承載件，以節省大量時間，使產能增加，而降低生產成本。
再者，於移除該玻璃承載件後，會外露該線路部之第二側，故可於該線路部之第二側上直接植設銲球或連接其它裝置，使產能大幅提升，因而降低生產成本。
1‧‧‧半導體封裝件
10,10’‧‧‧矽晶圓
100‧‧‧黏著層
11,21‧‧‧線路部
110,212‧‧‧電性接觸墊
12‧‧‧半導體晶片
13,23‧‧‧底膠
14‧‧‧封裝膠體
15,270‧‧‧開孔
17,27‧‧‧絕緣保護層
18,28‧‧‧導電元件
180‧‧‧凸塊底下金屬層
2‧‧‧電子封裝結構
2’‧‧‧電子封裝件
2a‧‧‧電子結構
20‧‧‧玻璃承載件
200‧‧‧離形膜
21a‧‧‧第一側
21b‧‧‧第二側
210‧‧‧介電層
211‧‧‧線路層
22‧‧‧電子元件
22a‧‧‧作用面
22b‧‧‧非作用面
220‧‧‧導電凸塊
24‧‧‧封裝層
h,h’‧‧‧厚度
S‧‧‧切割路徑
第1A至1F圖係為習知半導體封裝件之製法之剖面示意圖；以及第2A至2F圖係為本發明之電子封裝件之製法之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術 內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，提供一電子結構2a，該電子結構2a包含一具有離形膜200之玻璃承載件20、形成於該離形膜200上之一線路部21、結合於該線路部21上之複數電子元件22、及形成於該線路部21與各該電子元件22之間的底膠23。
於本實施例中，該電子元件22係為主動元件、被動元件或其組合者，該主動元件例如為半導體晶片，而該被動元件係例如電阻、電容及電感。於此該電子元件22係為主動元件，且其具有相對之作用面22a與非作用面22b。
再者，該線路部21係包含相疊之複數介電層210與複數線路層211，並具有相對之第一側21a與第二側21b，使該些電子元件22之作用面22a藉由複數導電凸塊220覆晶結合於該線路部21之第一側21a之線路層211上，而該底膠23係包覆該些導電凸塊220，且該線路部21之第二側21b係具有複數電性接觸墊212並結合至該玻璃承載件20上。
另外，該線路層211係為晶圓級線路，而非封裝基板 級線路。目前封裝基板級線路之最小之線寬與線距為12μm，而半導體製程能製作出3μm以下之線寬與線距的晶圓級線路。
如第2B圖所示，形成封裝層24於該線路部21之第一側21a上以包覆各該電子元件22與該底膠23。
如第2C圖所示，選擇性地移除該封裝層24之頂部材質以外露出該電子元件22，以獲得複數電子封裝結構2。於其它實施例中，該電子封裝結構2可不外露出該電子元件22。
如第2D圖所示，藉由離形膜200移除該玻璃承載件20，以外露該線路部21之第二側21b及該電性接觸墊212。
如第2E圖所示，形成複數如銲球之導電元件28於該線路部21之第二側21b上。
於本實施例中，係可選擇性形成一如防銲材、PBO等之絕緣保護層27於該線路部21之第二側21b，且該絕緣保護層27形成有複數開孔270，令該些電性接觸墊212外露於各該開孔270，以供結合該些導電元件28。
如第2F圖所示，沿如第2E圖所示之切割路徑S進行切單製程，以獲得複數電子封裝件2’。
再者，於其它實施例中，亦可先進行切單製程，再形成該絕緣保護層27與該些導電元件28。
另外，於後續製程中，該電子封裝件2’可藉由該些導電元件28結合至一如電路板之電子裝置(圖略)上，並以底膠(圖略)固定與保護該些導電元件28。
本發明之製法中，藉由該玻璃承載件20取代習知矽晶圓，因而能利用該離形膜200將該玻璃承載件20結合至該線路部21之第二側21b上，而無需使用習知黏著層，故相較於習知技術，本發明藉由該離形膜200移除該玻璃承載件20，能快速移除該玻璃承載件20，因而能節省大量時間(如省略機械研磨、化學蝕刻等製程)，進而能增加產能，以降低生產成本。
再者，因藉由該離形膜200移除該玻璃承載件20，故於移除該玻璃承載件20後，會外露該線路部21之第二側21b，因而無需於該離形膜200上製作開孔，即可於該電性接觸墊212上直接植設導電元件28或連接其它裝置，因而能節省大量時間(如省略黏著層上開孔之製程)。因此，本發明之製法能提升產能，且能降低生產成本。
本發明係提供一種電子封裝結構2，係包括：具有相對之第一側21a與第二側21b之一線路部21、設於該線路部21之第一側21a的至少一電子元件22、以及設於該線路部21之第二側21b上的玻璃承載件20。
所述之玻璃承載件20藉由離形膜200結合於該線路部21之第二側21b上。
於一實施例中，所述之電子封裝結構2復包括底膠23，其形成於該線路部21之第一側21a與該電子元件22之間。
於一實施例中，所述之電子封裝結構2復包括封裝層24，形成於該線路部21之第一側21a以包覆該電子元件 22。可選擇性地，使該電子元件22外露於該封裝層24。
綜上所述，本發明之電子封裝結構及電子封裝件之製法中，係藉由該玻璃承載件之設計，以利用該離形膜將該玻璃承載件結合至該線路部之第二側上，而無需使用習知黏著層，故能快速移除該玻璃承載件，以能節省大量時間，因而能增加產能，以降低生產成本。
再者，於移除該玻璃承載件後，無需再於該離形膜上製作開孔，即可直接於該電性接觸墊上植設導電元件或連接其它裝置，故能提升產能，且能降低生產成本。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝結構
20‧‧‧玻璃承載件
200‧‧‧離形膜
21‧‧‧線路部
21a‧‧‧第一側
21b‧‧‧第二側
22‧‧‧電子元件
23‧‧‧底膠
24‧‧‧封裝層

Claims (12)

  1. 一種電子封裝結構，係包括：線路部，係具有相對之第一側與第二側；至少一電子元件，係設於該線路部之第一側上；以及玻璃承載件，係設於該線路部之第二側上。
  2. 如申請專利範圍第1項所述之電子封裝結構，其中，該玻璃承載件藉由離形膜結合於該線路部之第二側上。
  3. 如申請專利範圍第1項所述之電子封裝結構，復包括底膠，係形成於該線路部之第一側與該電子元件之間。
  4. 如申請專利範圍第1項所述之電子封裝結構，復包括封裝層，係形成於該線路部之第一側以包覆該電子元件。
  5. 如申請專利範圍第4項所述之電子封裝結構，其中，該電子元件外露於該封裝層。
  6. 一種電子封裝件之製法，係包括：提供一電子結構，該電子結構包含玻璃承載件、設於該玻璃承載件上之線路部、及結合於該線路部上之至少一電子元件；形成封裝層於該線路部之第一側上以包覆該電子元件；以及移除該玻璃承載件。
  7. 如申請專利範圍第6項所述之電子封裝件之製法，其 中，該電子結構復包含形成於該線路部與該電子元件之間的底膠。
  8. 如申請專利範圍第6項所述之電子封裝件之製法，其中，該玻璃承載件藉由離形膜結合於該線路部之第二側上。
  9. 如申請專利範圍第8項所述之電子封裝件之製法，復包括藉由該離形膜移除該玻璃承載件。
  10. 如申請專利範圍第6項所述之電子封裝件之製法，復包括移除該封裝層之部分材質，以外露出該電子元件。
  11. 如申請專利範圍第6項所述之電子封裝件之製法，復包括於移除該玻璃承載件後，形成複數導電元件於該線路部上。
  12. 如申請專利範圍第6項所述之電子封裝件之製法，復包括於移除該玻璃承載件後，進行切單製程。
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