TW201834159A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

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TW201834159A
TW201834159A TW106106981A TW106106981A TW201834159A TW 201834159 A TW201834159 A TW 201834159A TW 106106981 A TW106106981 A TW 106106981A TW 106106981 A TW106106981 A TW 106106981A TW 201834159 A TW201834159 A TW 201834159A
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TWI652774B (zh
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賴杰隆
陳正逸
盧俊宏
葉懋華
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矽品精密工業股份有限公司
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Priority to CN201710169092.XA priority patent/CN108538731B/zh
Priority to US15/635,446 priority patent/US10679914B2/en
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Priority to US16/862,024 priority patent/US11081415B2/en

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Abstract

一種電子封裝件與製法，係以封裝層包覆電子元件，並形成線路結構於該封裝層之上表面上以電性連接該電子元件，且形成應力平衡層於該封裝層之部分下表面上，以藉由該應力平衡層之設計，而平衡該封裝層上、下表面所受之應力，故能降低該電子封裝件之整體結構之翹曲，使後續製程能順利進行。

Description

電子封裝件及其製法
本發明係有關一種封裝製程，尤指一種電子封裝件及其製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出晶片尺寸封裝件(Chip Scale Package，簡稱CSP)的技術，其特徵在於該晶片尺寸封裝件僅具有與晶片尺寸相等或略大的尺寸。
請參閱第1A至1D圖，係為習知晶片尺寸封裝件1之製法之剖面示意圖。
如第1A圖所示，形成一熱化離型膠層(thermal release tape)11於一承載件10上。
接著，置放複數半導體元件12於該熱化離型膠層11上，該些半導體元件12具有相對之作用面12a與非作用面12b，各該作用面12a上具有複數電極墊120，且該半導體元件12係以該作用面12a黏著於該熱化離型膠層11上。
如第1B圖所示，形成一封裝膠體13於該熱化離型膠 層11上，以包覆該半導體元件12。
如第1C圖所示，進行烘烤製程以硬化該封裝膠體13，而同時該熱化離型膠層11因受熱後會失去黏性，故可一併移除該熱化離型膠層11與該承載件10，以外露該半導體元件12之作用面12a。
如第1D圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，形成一具有介電層140及線路層141之線路結構14於該封裝膠體13與該半導體元件12之作用面12a上，且令該線路結構14電性連接該半導體元件12之電極墊120。
接著，形成一絕緣保護層15於該線路結構14上，且令該絕緣保護層15外露該線路結構14之部分表面，以供結合如銲球之導電元件16。
惟，習知晶片尺寸封裝件1之製法中，由於該封裝膠體13之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)與該線路結構14之介電層140的CTE不同且差異甚大，導致兩者CTE不匹配(mismatch)，而產生諸多問題。例如，該封裝膠體13之CTE約為30ppm/℃，該線路結構14之介電層140的CTE約為60ppm/℃，故於高溫製程時，由於CTE不匹配會使該半導體元件12大幅朝向該介電層140之方向彎曲(特別是隨著該介電層140之層數增加之情況下彎曲幅度更大)，而使該晶片尺寸封裝件1發生翹曲(warpage)，如第1C圖所示之上凸情況(即該封裝膠體13’之虛線輪廓)，導致該晶片尺寸封裝件1之平 面度不佳。
再者，過大之翹曲亦會使該半導體元件12與該線路結構14之線路層141之間的電性連接可靠度(reliability)下降，因而造成良率過低及產品可靠度不佳等問題。例如，該線路結構14與該半導體元件12之電極墊120之間的連接處受損，且當該承載件10之尺寸越大時，各該半導體元件12間之位置公差亦隨之加大，而當偏移公差過大時，將使該線路結構14之線路層141無法與該電極墊120連接。
又，翹曲的情況亦會造成該半導體元件12發生碎裂，致使產品良率降低。
另外，過大之翹曲會使該晶片尺寸封裝件1於製程中發生停擺，甚至後續產品發生可靠度之問題。例如，無法將該晶片尺寸封裝件1放入機台開口中，而造成機台操控管理與產量受阻等問題。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：封裝層，係具有相對之第一表面與第二表面；至少一電子元件，係嵌埋於該封裝層中；線路結構，係形成於該封裝層之第一表面上且電性連接該電子元件；以及應力平衡層，係形成於該封裝層之部分第二表面上。
本發明復提供一種電子封裝件之製法，係包括：將至 少一電子元件接置於一承載件上；形成封裝層於該承載件上以包覆該電子元件，且該封裝層具有相對之第一表面與第二表面，並以其第一表面結合該承載件；形成應力平衡層於該封裝層之部分第二表面上；移除該承載件；以及形成線路結構於該封裝層之第一表面上以電性連接該電子元件。
前述之電子封裝件及其製法中，該電子元件具有相對之作用面與非作用面，該作用面具有複數電性連接該線路結構之電極墊，該非作用面可選擇外露出該封裝層。
前述之電子封裝件及其製法中，該應力平衡層佔用該封裝層之第二表面之面積之百分比係為1%至99%，較佳為10%至90%。
前述之電子封裝件及其製法中，該應力平衡層係形成於該封裝層之部分第二表面之多個區域上。
前述之電子封裝件及其製法中，該應力平衡層復結合於該電子元件上。
前述之電子封裝件及其製法中，復包括形成用以包覆該應力平衡層之包覆層。例如，該包覆層與該封裝層之間具有交界面、或者該包覆層與該封裝層係成為一體。
前述之電子封裝件之製法中，復包括進行切單製程。
由上可知，本發明之電子封裝件及其製法，主要藉由將該應力平衡層形成於該封裝層之部分第二表面上，以平衡該封裝層相對兩側之應力，故相較於習知技術，本發明能大幅降低該電子封裝件之整體結構之翹曲，使後續製程 可順利進行。
再者，由於該電子封裝件之整體結構之翹曲程度大幅降低，故相較於習知技術，本發明能避免該電子元件與該線路結構之間的電性連接可靠度下降，且能避免該電子元件發生碎裂，因而能提升製程良率及可靠度。
1‧‧‧晶片尺寸封裝件
10,20‧‧‧承載件
11‧‧‧熱化離型膠層
12‧‧‧半導體元件
12a,22a‧‧‧作用面
12b,22b‧‧‧非作用面
120,220‧‧‧電極墊
13,13’‧‧‧封裝膠體
14,24‧‧‧線路結構
140,240‧‧‧介電層
141,241‧‧‧線路層
15,25‧‧‧絕緣保護層
16,26‧‧‧導電元件
2,2’,3a,3b,3c,3d‧‧‧電子封裝件
21‧‧‧黏著層
22,22’‧‧‧電子元件
23‧‧‧封裝層
23a‧‧‧第一表面
23b‧‧‧第二表面
242‧‧‧導電盲孔
243‧‧‧電性接觸墊
27,27’‧‧‧包覆層
28,38,38’‧‧‧應力平衡層
S‧‧‧切割路徑
L‧‧‧交界面
第1A至1D圖係為習知晶片尺寸封裝件之製法之剖面示意圖；第2A至2E圖係為本發明之電子封裝件之製法之剖面示意圖；第2A’圖係為對應第2A圖之另一實施例，第2E’圖係為對應第2E圖之另一實施例，第2E”圖係為對應第2E’圖之另一實施例；第3A至3D圖係為對應第2E圖之其它實施例之剖面示意圖；以及第4A至4F圖係為對應第2B圖之不同態樣之上視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例 關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2E圖，係為本發明之電子封裝件2之製法的剖面示意圖。
如第2A圖所示，設置複數電子元件22於一承載件20上，再形成一封裝層23於該承載件20上，以包覆該些電子元件22。
於本實施例中，該承載件20係為如晶圓、矽板之半導體基板或玻璃基板等，且該承載件20藉由其表面上之黏著層21，以結合該些電子元件22與該封裝層23。例如，該黏著層21係為熱化離型膠層(thermal release tape)。
再者，該電子元件22係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件22具有相對之作用面22a與非作用面22b，該作用面22a上具有複數電極墊220，且該電子元件22以其作用面22a結合該黏著層21。
又，該封裝層23係具有相對之第一表面23a與第二表面23b，並以其第一表面23a結合該承載件20上之黏著層 21。例如，該封裝層23係以壓合(Lamination)或模封(Molding)方式形成於該承載件20上，且該封裝層23之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)。
另外，如第2A’圖所示，可透過例如研磨等方式令該電子元件22'之非作用面22b外露於該封裝層23之第二表面23b。
如第2B圖所示，接續第2A圖之製程，形成一應力平衡層28於該封裝層23之部分第二表面23b上。
於本實施例中，該應力平衡層28之熱膨脹係數(Coefficient of thermal expansion，簡稱CTE)與該封裝層23之熱膨脹係數(CTE)不相同。例如，形成該應力平衡層28之材質係為金屬材(鋁、鉛、銅、鐵、金、鎳、銀等)或絕緣材，並無特別限制。
再者，可先以如旋塗(spin coating)或貼膜等圖案化方式將應力緩衝材形成於該封裝層23之全部第二表面23b上，再移除部分應力緩衝材，並保留部分應力緩衝材，以構成該應力平衡層28；或者，亦可直接將圖案化之應力平衡層28以貼膜方式形成於該封裝層23之部分第二表面23b上；亦或，可直接於該封裝層23之部分第二表面23b上進行圖案化鍍製或塗佈應力緩衝材以構成該應力平衡層28。因此，有關該應力平衡層28之形成方式繁多，可依需求採用，並不限於上述。
又，該應力平衡層28佔用該封裝層23之第二表面23b 之面積之百分比係為1%至99%。具體地，如第4A至4F圖所示，該應力平衡層28,38之佈設面積A與該第二表面23b之面積B的面積比(A/B)，較佳約為10%至90%。
另外，該應力平衡層28,38之圖案種類可依需求變化，如第4B至4F圖所示之矩形、圓形、環狀或其它形狀等之各種圖形，且可於該封裝層23之部分第二表面23b之單一區域或複數區域存設該應力平衡層28,38，僅不要覆蓋全部第二表面23b即可，並無特別限制。
如第2C圖所示，移除該承載件20及該黏著層21，以外露該電子元件22之作用面22a與該封裝層23之第一表面23a。
於本實施例中，由於該黏著層21係為熱化離型膠層(thermal release tape)，故進行烘烤製程以硬化該封裝層23，該黏著層21因受熱而會失去黏性，藉此以移除該黏著層21與該承載件20。
如第2D圖所示，進行線路重佈層(Redistribution layer，簡稱RDL)製程，即形成一線路結構24於該封裝層23之第一表面23a與該些電子元件22之作用面22a上，且該線路結構24電性連接該電子元件22之電極墊220。
於本實施例中，該線路結構24係包含相疊之至少一介電層240與至少一線路層241，該介電層240係形成於該封裝層23之第一表面23a上方，且該線路層241係藉由複數導電盲孔242電性連接該電子元件22之電極墊220。
再者，復可形成一絕緣保護層25於該線路結構24上， 且該絕緣保護層25外露該線路層241之部分表面，俾供作為電性接觸墊243，以形成複數如銲球或金屬凸塊之導電元件26於該些電性接觸墊243上。
如第2E圖所示，沿第2D圖所示之切割路徑S進行切單製程，以獲取複數個電子封裝件2。
於本實施例中，如第2E’圖所示，於移除該承載件20及該黏著層21後(亦可於形成該線路結構24後，或於切單製程後，亦或形成該應力平衡層28後)，可形成一用以包覆該應力平衡層28之包覆層27。例如，形成該包覆層27之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)。具體地，該包覆層27之材質與該封裝層23之材質可相同或不相同，且該包覆層27與該封裝層23之間具有一交界面L，但從外觀視之，該包覆層27與該封裝層23不易察覺，需以剖面視出該交界面L；或者，如第2E”圖所示，藉由製程加工(如熱熔再固化或其它方式)，使該包覆層27’與該封裝層23成為一體，亦即該包覆層27’與該封裝層23之間沒有交界面。
再者，於第2E及2E’圖所示之電子封裝件2,2’中，該應力平衡層28係形成於該封裝層23之部分第二表面23b之單一區域上，使單一該電子元件22對應單一區域之應力平衡層28；於其它實施例中，如第3A圖所示之電子封裝件3a，該應力平衡層28係形成於該封裝層23之部分第二表面23b之多個區域上，令單一該電子元件22對應多個區 域之應力平衡層38；或者，如第3B圖所示之電子封裝件3b，令多個該電子元件22對應多個區域之該應力平衡層38；亦或，如第3C圖所示之電子封裝件3c，令多個該電子元件22對應單一區域之應力平衡層38’。
又，若依據第2A’圖所示之狀態進行後續製程，該應力平衡層28將接觸結合於該電子元件22’之非作用面22b上，如第3D圖所示。應可理解地，第3A至3C圖所示之電子封裝件3a,3b,3c之應力平衡層38,38’亦可依需求接觸該電子元件22之非作用面22b。
本發明之製法中，主要利用該應力平衡層28,38,38’形成於該封裝層23之部分第二表面23b上，以彈性調整該應力平衡層28,38,38’之佈設位置(針對應力易於集中之處)及使用不同CTE之材料，而能依需求平衡該封裝層23之第一表面23a所受之應力與該第二表面23b所受之應力，故相較於習知技術，本發明之製法能大幅降低該電子封裝件2,2’,3a,3b,3c,3d之整體結構之翹曲，使得後續製程能順利進行。
再者，本發明之電子封裝件2,2’,2”,3a,3b,3c,3d能藉由調整該應力平衡層28,38,38’之厚度、佈設面積、圖案或CTE等方式，使該封裝層23能保持應力平衡而不易翹曲。例如，該應力平衡層28,38,38’之條件(如針對CTE大小之材質選用)係配合該介電層240之材質與層數。
又，由於該電子封裝件2,2’,2”,3a,3b,3c,3d之整體結構之翹曲程度大幅降低，故能避免該電子元件22,22’與該 線路結構24之線路層241之間的電性連接可靠度(reliability)下降，進而避免良率過低及產品可靠度不佳等問題。因此，當該承載件20之尺寸越大時，各該電子元件22,22’間之位置公差不會隨之加大，故該導電盲孔242與該電極墊220間之電性連接能有效對接，而能提高良率及提升產品可靠度。
另外，由於該電子封裝件2,2’,2”,3a,3b,3c,3d之整體結構之翹曲程度大幅降低，故亦可避免該電子元件22,22’發生碎裂，因而能有效提升產品良率。
本發明亦提供一種電子封裝件2,2’,2”,3a,3b,3c,3d，係包括：一封裝層23、至少一電子元件22,22’、一線路結構24以及一應力平衡層28,38,38’。
所述之封裝層23係具有相對之第一表面23a與第二表面23b。
所述之電子元件22,22’係嵌埋於該封裝層23中。
所述之線路結構24係形成於該封裝層23之第一表面23a上且電性連接該電子元件22,22’。
所述之應力平衡層28,38,38’係形成於該封裝層23之部分第二表面23b上。
於一實施例中，該電子元件22,22’具有相對之作用面22a與非作用面22b，該作用面22a具有複數電極墊220。另該電子元件22’之非作用面22b可外露出該封裝層23。
於一實施例中，該應力平衡層28,38,38’佔用該封裝層23之第二表面23b之面積之百分比係為1%至99%，較 佳為10%至90%。
於一實施例中，該應力平衡層38係形成於該封裝層23之部分第二表面23b之多個區域上。
於一實施例中，該應力平衡層28復結合於該電子元件22’上。
於一實施例中，所述之電子封裝件2’,2”復包括一用以包覆該應力平衡層28之包覆層27,27’。例如，該包覆層27與該封裝層23之間具有交界面L；或者，該包覆層27’與該封裝層23係成為一體。
綜上所述，本發明之電子封裝件及其製法，係藉由該應力平衡層形成於該封裝層之部分第二表面上之設計，以有效平衡該封裝層之應力，故能降低該電子封裝件之整體結構之翹曲，使後續製程能順利進行。
再者，由於該電子封裝件之整體結構之翹曲程度大幅降低，故能避免該電子元件與該線路結構之線路層之間的電性連接可靠度下降，且能避免該電子元件發生碎裂，因而能提升產生良率及可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改或對該些實施例所揭露之內容進行組合應用。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。

Claims (21)

  1. 一種電子封裝件，係包括：封裝層，係具有相對之第一表面與第二表面；至少一電子元件，係嵌埋於該封裝層中；線路結構，係形成於該封裝層之第一表面上且電性連接該電子元件；以及應力平衡層，係形成於該封裝層之部分第二表面上。
  2. 如申請專利範圍第1項所述之電子封裝件，其中，該電子元件具有相對之作用面與非作用面，該作用面具有複數電性連接該線路結構之電極墊。
  3. 如申請專利範圍第2項所述之電子封裝件，其中，該非作用面外露出該封裝層。
  4. 如申請專利範圍第1項所述之電子封裝件，其中，該應力平衡層佔用該封裝層之第二表面之面積之百分比係為1%至99%。
  5. 如申請專利範圍第4項所述之電子封裝件，其中，該應力平衡層佔用該封裝層之第二表面之面積之百分比係為10%至90%。
  6. 如申請專利範圍第1項所述之電子封裝件，其中，該應力平衡層係形成於該封裝層之部分第二表面之多個區域上。
  7. 如申請專利範圍第1項所述之電子封裝件，其中，該應力平衡層復結合於該電子元件上。
  8. 如申請專利範圍第1項所述之電子封裝件，復包括包覆該應力平衡層之包覆層。
  9. 如申請專利範圍第8項所述之電子封裝件，其中，該包覆層與該封裝層之間具有交界面。
  10. 如申請專利範圍第8項所述之電子封裝件，其中，該包覆層與該封裝層係成為一體。
  11. 一種電子封裝件之製法，係包括：將至少一電子元件接置於一承載件上；形成封裝層於該承載件上以包覆該電子元件，且該封裝層係具有相對之第一表面與第二表面，並以其第一表面結合該承載件；形成應力平衡層於該封裝層之部分第二表面上；移除該承載件；以及形成線路結構於該封裝層之第一表面上以電性連接該電子元件。
  12. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該電子元件具有相對之作用面與非作用面，該作用面具有複數電性連接該線路結構之電極墊。
  13. 如申請專利範圍第12項所述之電子封裝件之製法，其中，該非作用面外露出該封裝層。
  14. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該應力平衡層佔用該封裝層之第二表面之面積之百分比係為1%至99%。
  15. 如申請專利範圍第14項所述之電子封裝件之製法，其 中，該應力平衡層佔用該封裝層之第二表面之面積之百分比係為10%至90%。
  16. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該應力平衡層係形成於該封裝層之部分第二表面之多個區域上。
  17. 如申請專利範圍第11項所述之電子封裝件之製法，其中，該應力平衡層復結合於該電子元件上。
  18. 如申請專利範圍第11項所述之電子封裝件之製法，復包括形成包覆該應力平衡層之包覆層。
  19. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該包覆層與該封裝層之間具有交界面。
  20. 如申請專利範圍第18項所述之電子封裝件之製法，其中，該包覆層與該封裝層係成為一體。
  21. 如申請專利範圍第11項所述之電子封裝件之製法，復包括進行切單製程。
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