CN108538731B - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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CN108538731B
CN108538731B CN201710169092.XA CN201710169092A CN108538731B CN 108538731 B CN108538731 B CN 108538731B CN 201710169092 A CN201710169092 A CN 201710169092A CN 108538731 B CN108538731 B CN 108538731B
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package
stress balance
electronic package
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赖杰隆
陈正逸
卢俊宏
叶懋华
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法，以封装层包覆电子元件，并形成线路结构于该封装层的上表面上以电性连接该电子元件，且形成应力平衡层于该封装层的部分下表面上，以通过该应力平衡层的设计，而平衡该封装层上、下表面所受的应力，故能降低该电子封装件的整体结构的翘曲，使后续制程能顺利进行。

Description

电子封装件及其制法
技术领域
本发明有关一种封装制程，尤指一种电子封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了满足半导体封装件微型化(miniaturization)的封装需求，发展出芯片尺寸封装件(Chip ScalePackage，简称CSP)的技术，其特征在于该芯片尺寸封装件仅具有与芯片尺寸相等或略大的尺寸。
请参阅图1A至图1D，为现有芯片尺寸封装件1的制法的剖面示意图。
如图1A所示，形成一热化离型胶层(thermal release tape)11于一承载件10上。
接着，置放多个半导体元件12于该热化离型胶层11上，该些半导体元件12具有相对的作用面12a与非作用面12b，各该作用面12a上具有多个电极垫120，且该半导体元件12以该作用面12a黏着于该热化离型胶层11上。
如图1B所示，形成一封装胶体13于该热化离型胶层11上，以包覆该半导体元件12。
如图1C所示，进行烘烤制程以硬化该封装胶体13，而同时该热化离型胶层11因受热后会失去黏性，故可一并移除该热化离型胶层11与该承载件10，以外露该半导体元件12的作用面12a。
如图1D所示，进行线路重布层(Redistribution layer，简称RDL)制程，形成一具有介电层140及线路层141的线路结构14于该封装胶体13与该半导体元件12的作用面12a上，且令该线路结构14电性连接该半导体元件12的电极垫120。
接着，形成一绝缘保护层15于该线路结构14上，且令该绝缘保护层15外露该线路结构14的部分表面，以供结合如焊球的导电元件16。
然而，现有芯片尺寸封装件1的制法中，由于该封装胶体13的热膨胀系数(Coefficient of thermal expansion，简称CTE)与该线路结构14的介电层140的CTE不同且差异甚大，导致两者CTE不匹配(mismatch)，而产生诸多问题。例如，该封装胶体13的CTE约为30ppm/℃，该线路结构14的介电层140的CTE约为60ppm/℃，故于高温制程时，由于CTE不匹配会使该半导体元件12大幅朝向该介电层140的方向弯曲(特别是随着该介电层140的层数增加的情况下弯曲幅度更大)，而使该芯片尺寸封装件1发生翘曲(warpage)，如图1C所示的上凸情况(即该封装胶体13’的虚线轮廓)，导致该芯片尺寸封装件1的平面度不佳。
此外，过大的翘曲也会使该半导体元件12与该线路结构14的线路层141之间的电性连接可靠度(reliability)下降，因而造成良率过低及产品可靠度不佳等问题。例如，该线路结构14与该半导体元件12的电极垫120之间的连接处受损，且当该承载件10的尺寸越大时，各该半导体元件12间的位置公差亦随之加大，而当偏移公差过大时，将使该线路结构14的线路层141无法与该电极垫120连接。
又，翘曲的情况也会造成该半导体元件12发生碎裂，致使产品良率降低。
另外，过大的翘曲会使该芯片尺寸封装件1于制程中发生停摆，甚至后续产品发生可靠度的问题。例如，无法将该芯片尺寸封装件1放入机台开口中，而造成机台操控管理与产量受阻等问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其制法，能降低该电子封装件的整体结构的翘曲，使后续制程能顺利进行。
本发明的电子封装件，包括：封装层，其具有相对的第一表面与第二表面；至少一电子元件，其嵌埋于该封装层中；线路结构，其形成于该封装层的第一表面上且电性连接该电子元件；以及应力平衡层，其形成于该封装层的部分第二表面上。
本发明还提供一种电子封装件的制法，包括：将至少一电子元件接置于一承载件上；形成封装层于该承载件上以包覆该电子元件，且该封装层具有相对的第一表面与第二表面，并以其第一表面结合该承载件；形成应力平衡层于该封装层的部分第二表面上；移除该承载件；以及形成线路结构于该封装层的第一表面上以电性连接该电子元件。
前述的电子封装件及其制法中，该电子元件具有相对的作用面与非作用面，该作用面具有多个电性连接该线路结构的电极垫，该非作用面可选择外露出该封装层。
前述的电子封装件及其制法中，该应力平衡层占用该封装层的第二表面的面积的百分比为1％至99％，较佳为10％至90％。
前述的电子封装件及其制法中，该应力平衡层形成于该封装层的部分第二表面的多个区域上。
前述的电子封装件及其制法中，该应力平衡层还结合于该电子元件上。
前述的电子封装件及其制法中，还包括形成用以包覆该应力平衡层的包覆层。例如，该包覆层与该封装层之间具有交界面、或者该包覆层与该封装层成为一体。
前述的电子封装件的制法中，还包括进行切单制程。
由上可知，本发明的电子封装件及其制法，主要通过将该应力平衡层形成于该封装层的部分第二表面上，以平衡该封装层相对两侧的应力，故相比于现有技术，本发明能大幅降低该电子封装件的整体结构的翘曲，使后续制程可顺利进行。
此外，由于该电子封装件的整体结构的翘曲程度大幅降低，故相比于现有技术，本发明能避免该电子元件与该线路结构之间的电性连接可靠度下降，且能避免该电子元件发生碎裂，因而能提升制程良率及可靠度。
附图说明
图1A至图1D为现有芯片尺寸封装件的制法的剖面示意图；
图2A至图2E为本发明的电子封装件的制法的剖面示意图；
图2A’为对应图2A的另一实施例，图2E’为对应图2E的另一实施例，图2E”为对应图2E’的另一实施例；
图3A至图3D为对应图2E的其它实施例的剖面示意图；以及
图4A至图4F为对应图2B的不同实施例的上视示意图。
符号说明：
1 芯片尺寸封装件
10,20 承载件
11 热化离型胶层
12 半导体元件
12a,22a 作用面
12b,22b 非作用面
120,220 电极垫
13,13’ 封装胶体
14,24 线路结构
140,240 介电层
141,241 线路层
15,25 绝缘保护层
16,26 导电元件
2,2’,3a,3b,3c,3d 电子封装件
21 黏着层
22,22’ 电子元件
23 封装层
23a 第一表面
23b 第二表面
242 导电盲孔
243 电性接触垫
27,27’ 包覆层
28,38,38’ 应力平衡层
S 切割路径
L 交界面。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2E，其为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，设置多个电子元件22于一承载件20上，再形成一封装层23于该承载件20上，以包覆该些电子元件22。
于本实施例中，该承载件20为如晶圆、硅板的半导体基板或玻璃基板等，且该承载件20通过其表面上的黏着层21，以结合该些电子元件22与该封装层23。例如，该黏着层21为热化离型胶层(thermal release tape)。
此外，该电子元件22为主动元件、被动元件或其二者组合等，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件22具有相对的作用面22a与非作用面22b，该作用面22a上具有多个电极垫220，且该电子元件22以其作用面22a结合该黏着层21。
又，该封装层23具有相对的第一表面23a与第二表面23b，并以其第一表面23a结合该承载件20上的黏着层21。例如，该封装层23以压合(Lamination)或模封(Molding)方式形成于该承载件20上，且该封装层23的材质为聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、环氧树脂(epoxy)或封装材(molding compound)。
另外，如图2A’所示，可透过例如研磨等方式令该电子元件22'的非作用面22b外露于该封装层23的第二表面23b。
如图2B所示，接续图2A的制程，形成一应力平衡层28于该封装层23的部分第二表面23b上。
于本实施例中，该应力平衡层28的热膨胀系数(Coefficient of thermalexpansion，简称CTE)与该封装层23的热膨胀系数(CTE)不相同。例如，形成该应力平衡层28的材质为金属材(铝、铅、铜、铁、金、镍、银等)或绝缘材，并无特别限制。
此外，可先以如旋涂(spin coating)或贴膜等图案化方式将应力缓冲材形成于该封装层23的全部第二表面23b上，再移除部分应力缓冲材，并保留部分应力缓冲材，以构成该应力平衡层28；或者，亦可直接将图案化的应力平衡层28以贴膜方式形成于该封装层23的部分第二表面23b上；抑或，可直接于该封装层23的部分第二表面23b上进行图案化镀制或涂布应力缓冲材以构成该应力平衡层28。因此，有关该应力平衡层28的形成方式繁多，可依需求采用，并不限于上述。
又，该应力平衡层28占用该封装层23的第二表面23b的面积的百分比为1％至99％。具体地，如图4A至图4F所示，该应力平衡层28,38的布设面积A与该第二表面23b的面积B的面积比(A/B)，较佳约为10％至90％。
另外，该应力平衡层28,38的图案种类可依需求变化，如图4B至图4F所示的矩形、圆形、环状或其它形状等的各种图形，且可于该封装层23的部分第二表面23b的单一区域或多个区域存设该应力平衡层28,38，仅不要覆盖全部第二表面23b即可，并无特别限制。
如图2C所示，移除该承载件20及该黏着层21，以外露该电子元件22的作用面22a与该封装层23的第一表面23a。
于本实施例中，由于该黏着层21为热化离型胶层(thermal release tape)，故进行烘烤制程以硬化该封装层23，该黏着层21因受热而会失去黏性，藉此以移除该黏着层21与该承载件20。
如图2D所示，进行线路重布层(Redistribution layer，简称RDL)制程，即形成一线路结构24于该封装层23的第一表面23a与该些电子元件22的作用面22a上，且该线路结构24电性连接该电子元件22的电极垫220。
于本实施例中，该线路结构24包含相迭的至少一介电层240与至少一线路层241，该介电层240形成于该封装层23的第一表面23a上方，且该线路层241通过多个导电盲孔242电性连接该电子元件22的电极垫220。
此外，还可形成一绝缘保护层25于该线路结构24上，且该绝缘保护层25外露该线路层241的部分表面，俾供作为电性接触垫243，以形成多个如焊球或金属凸块的导电元件26于该些电性接触垫243上。
如图2E所示，沿图2D所示的切割路径S进行切单制程，以获取多个电子封装件2。
于本实施例中，如图2E’所示，于移除该承载件20及该黏着层21后(亦可于形成该线路结构24后，或于切单制程后，抑或形成该应力平衡层28后)，可形成一用以包覆该应力平衡层28的包覆层27。例如，形成该包覆层27的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound)。具体地，该包覆层27的材质与该封装层23的材质可相同或不相同，且该包覆层27与该封装层23之间具有一交界面L，但从外观视之，该包覆层27与该封装层23不易察觉，需以剖面视出该交界面L；或者，如图2E”所示，通过制程加工(如热熔再固化或其它方式)，使该包覆层27’与该封装层23成为一体，也就是该包覆层27’与该封装层23之间没有交界面。
此外，于图2E及图2E’所示的电子封装件2,2’中，该应力平衡层28形成于该封装层23的部分第二表面23b的单一区域上，使单一该电子元件22对应单一区域的应力平衡层28；于其它实施例中，如图3A所示的电子封装件3a，该应力平衡层28形成于该封装层23的部分第二表面23b的多个区域上，令单一该电子元件22对应多个区域的应力平衡层38；或者，如图3B所示的电子封装件3b，令多个该电子元件22对应多个区域的该应力平衡层38；抑或，如图3C所示的电子封装件3c，令多个该电子元件22对应单一区域的应力平衡层38’。
又，若依据图2A’所示的状态进行后续制程，该应力平衡层28将接触结合于该电子元件22’的非作用面22b上，如图3D所示。应可理解地，图3A至图3C所示的电子封装件3a,3b,3c的应力平衡层38,38’亦可依需求接触该电子元件22的非作用面22b。
本发明的制法中，主要利用该应力平衡层28,38,38’形成于该封装层23的部分第二表面23b上，以弹性调整该应力平衡层28,38,38’的布设位置(针对应力易于集中之处)及使用不同CTE的材料，而能依需求平衡该封装层23的第一表面23a所受的应力与该第二表面23b所受的应力，故相比于现有技术，本发明的制法能大幅降低该电子封装件2,2’,3a,3b,3c,3d的整体结构的翘曲，使得后续制程能顺利进行。
此外，本发明的电子封装件2,2’,2”,3a,3b,3c,3d能通过调整该应力平衡层28,38,38’的厚度、布设面积、图案或CTE等方式，使该封装层23能保持应力平衡而不易翘曲。例如，该应力平衡层28,38,38’的条件(如针对CTE大小的材质选用)配合该介电层240的材质与层数。
又，由于该电子封装件2,2’,2”,3a,3b,3c,3d的整体结构的翘曲程度大幅降低，故能避免该电子元件22,22’与该线路结构24的线路层241之间的电性连接可靠度(reliability)下降，进而避免良率过低及产品可靠度不佳等问题。因此，当该承载件20的尺寸越大时，各该电子元件22,22’间的位置公差不会随之加大，故该导电盲孔242与该电极垫220间的电性连接能有效对接，而能提高良率及提升产品可靠度。
另外，由于该电子封装件2,2’,2”,3a,3b,3c,3d的整体结构的翘曲程度大幅降低，故亦可避免该电子元件22,22’发生碎裂，因而能有效提升产品良率。
本发明还提供一种电子封装件2,2’,2”,3a,3b,3c,3d，包括：一封装层23、至少一电子元件22,22’、一线路结构24以及一应力平衡层28,38,38’。
所述的封装层23具有相对的第一表面23a与第二表面23b。
所述的电子元件22,22’嵌埋于该封装层23中。
所述的线路结构24形成于该封装层23的第一表面23a上且电性连接该电子元件22,22’。
所述的应力平衡层28,38,38’形成于该封装层23的部分第二表面23b上。
于一实施例中，该电子元件22,22’具有相对的作用面22a与非作用面22b，该作用面22a具有多个电极垫220。另该电子元件22’的非作用面22b可外露出该封装层23。
于一实施例中，该应力平衡层28,38,38’占用该封装层23的第二表面23b的面积的百分比为1％至99％，较佳为10％至90％。
于一实施例中，该应力平衡层38形成于该封装层23的部分第二表面23b的多个区域上。
于一实施例中，该应力平衡层28还结合于该电子元件22’上。
于一实施例中，所述的电子封装件2’,2”还包括一用以包覆该应力平衡层28的包覆层27,27’。例如，该包覆层27与该封装层23之间具有交界面L；或者，该包覆层27’与该封装层23成为一体。
综上所述，本发明的电子封装件及其制法，通过该应力平衡层形成于该封装层的部分第二表面上的设计，以有效平衡该封装层的应力，故能降低该电子封装件的整体结构的翘曲，使后续制程能顺利进行。
再者，由于该电子封装件的整体结构的翘曲程度大幅降低，故能避免该电子元件与该线路结构的线路层之间的电性连接可靠度下降，且能避免该电子元件发生碎裂，因而能提升产生良率及可靠度。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改或对该些实施例所揭露的内容进行组合应用。因此本发明的权利保护范围，应如权利要求书所列。

Claims (15)

1.一种电子封装件，其特征为，该电子封装件包括：
封装层，其具有相对的第一表面与第二表面；
至少一电子元件，其嵌埋于该封装层中；
线路结构，其形成于该封装层的第一表面上且电性连接该电子元件；以及
应力平衡层，其形成于该封装层的部分第二表面上；以及
包覆层，其包覆该应力平衡层，且该包覆层与该封装层成为一体。
2.根据权利要求1所述的电子封装件，其特征为，该电子元件具有相对的作用面与非作用面，该作用面具有多个电性连接该线路结构的电极垫。
3.根据权利要求2所述的电子封装件，其特征为，该非作用面外露出该封装层。
4.一种电子封装件，其特征为，该电子封装件包括：
封装层，其具有相对的第一表面与第二表面；
至少一电子元件，其嵌埋于该封装层中；
线路结构，其形成于该封装层的第一表面上且电性连接该电子元件；以及
应力平衡层，其形成于该封装层的部分第二表面的多个区域上。
5.根据权利要求1或4所述的电子封装件，其特征为，该应力平衡层还结合于该电子元件上。
6.根据权利要求1或4所述的电子封装件，其特征为，该应力平衡层占用该封装层的第二表面的面积的百分比为1％至99％。
7.根据权利要求6所述的电子封装件，其特征为，该应力平衡层占用该封装层的第二表面的面积的百分比为10％至90％。
8.一种电子封装件的制法，其特征为，该制法包括：
将至少一电子元件接置于一承载件上；
形成封装层于该承载件上以包覆该电子元件，且该封装层具有相对的第一表面与第二表面，并以其第一表面结合该承载件；
形成应力平衡层于该封装层的部分第二表面上；
移除该承载件；以及
形成线路结构于该封装层的第一表面上以电性连接该电子元件；以及
形成包覆该应力平衡层的包覆层，该包覆层与该封装层成为一体。
9.根据权利要求8所述的电子封装件的制法，其特征为，该电子元件具有相对的作用面与非作用面，该作用面具有多个电性连接该线路结构的电极垫。
10.根据权利要求9所述的电子封装件的制法，其特征为，该非作用面外露出该封装层。
11.一种电子封装件的制法，其特征为，该制法包括：
将至少一电子元件接置于一承载件上；
形成封装层于该承载件上以包覆该电子元件，且该封装层具有相对的第一表面与第二表面，并以其第一表面结合该承载件；
形成应力平衡层于该封装层的部分第二表面的多个区域上；
移除该承载件；以及
形成线路结构于该封装层的第一表面上以电性连接该电子元件。
12.根据权利要求8或11所述的电子封装件的制法，其特征为，该应力平衡层还结合于该电子元件上。
13.根据权利要求8或11所述的电子封装件的制法，其特征为，该应力平衡层占用该封装层的第二表面的面积的百分比为1％至99％。
14.根据权利要求13所述的电子封装件的制法，其特征为，该应力平衡层占用该封装层的第二表面的面积的百分比为10％至90％。
15.根据权利要求8或11所述的电子封装件的制法，其特征为，该制法还包括进行切单制程。
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