CN111952274A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN111952274A
CN111952274A CN201910504912.5A CN201910504912A CN111952274A CN 111952274 A CN111952274 A CN 111952274A CN 201910504912 A CN201910504912 A CN 201910504912A CN 111952274 A CN111952274 A CN 111952274A
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conductive
layer
circuit structure
electronic
interposer
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CN111952274B (zh
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苏品境
张正楷
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法，以包覆层包覆一具有导电穿孔的中介板与多个导电柱，且将电子元件设于该包覆层上且电性连接该导电柱与该导电穿孔，经由该导电柱作为电子元件的部分电性功能的电性传输路径，减少该导电穿孔的制作数量，进而减少制程时间及化学药剂的成本，且能制作小尺寸的中介板以取代现有大面积硅中介板，进而提高良率。

Description

电子封装件及其制法
技术领域
本发明有关一种封装结构，尤指一种电子封装件及其承载基板与制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于芯片封装领域的技术，包含有例如芯片尺寸构装(Chip Scale Package，简称CSP)、芯片直接贴附封装(Direct Chip Attached，简称DCA)或多芯片模组封装(Multi-Chip Module，简称MCM)等覆晶型态的封装模组，或将芯片立体堆叠化整合为三维积体电路(3D IC)芯片堆叠技术等。
图1为现有3D芯片堆叠的封装结构1的剖面示意图。如图1所示，该封装结构1包括一硅中介板(Through Silicon interposer，简称TSI)1a，其具有一硅板体10及多个形成于其中的导电硅穿孔(Through-silicon via，简称TSV)101，且该硅板体10的表面上形成有一电性连接该导电硅穿孔101的线路重布结构(Redistribution layer，简称RDL)。具体地，该线路重布结构包含一介电层11及一形成于该介电层11上的线路层12，且该线路层12电性连接该导电硅穿孔101，并形成一绝缘保护层13于该介电层11与该线路层12上，且该绝缘保护层13外露部分该线路层11，以结合多个如焊锡凸块的第一导电元件14。
此外，可先形成另一绝缘保护层15于该硅板体10上，且该绝缘保护层15外露该些导电硅穿孔101的端面，以结合多个第二导电元件16于该些导电硅穿孔101的端面上，且该第二导电元件16电性连接该导电硅穿孔101，其中，该第二导电元件16含有焊锡材料或铜凸块，且可选择性于该导电硅穿孔101的端面上形成供接置该第二导电元件16的凸块底下金属层(Under Bump Metallurgy，简称UBM)160。
另外，该封装结构1还包括一封装基板19，供该硅中介板1a经由该些第二导电元件16设于其上，使该封装基板19电性连接该些导电硅穿孔101，且以底胶191包覆该些第二导电元件16。
另外，该封装结构1还包括多个半导体芯片17，其设于该些第一导电元件14上，使该半导体芯片17电性连接该线路层12，其中，该半导体芯片17以覆晶方式结合该些第一导电元件14，且以底胶171包覆该些第一导电元件14，并形成封装材18于该封装基板19上，以令该封装材18包覆该半导体芯片17与该硅中介板1a。
于后续应用中，该封装结构1可形成多个焊球192于该封装基板19的下侧，以接置于一如电路板的电子装置(图略)上。
然而，现今终端产品的电性功能越加发达，故接置于该硅中介板1a上的电子元件半导体芯片17越来越多，使该硅中介板1a的结合面积亦会越来越大，因而该导电硅穿孔101的布设数量亦会增多，导致于制程上会产生以下缺陷，造成该封装结构1的良率下降。
第一点：该硅中介板1a的体积越来越大，则该底胶171及该封装材18等胶材与该封装基板19、硅中介板1a及半导体芯片17之间的热膨胀系数(CTE)不匹配(mismatch)，因而容易发生热应力不均匀的情况，致使热循环(thermal cycle)时，该硅中介板1a产生极大的翘曲(warpage)，以致于发生植球状况不佳(即该第二导电元件16掉落而电性断路)、第二导电元件16不沾锡(non-wetting)或该封装基板19分裂等可靠度问题，进而导致应用该封装结构1的终端电子产品(如电脑、手机等)产生可靠度问题。
第二点：该半导体芯片17的电性功能一定要通过该硅中介板1a才能连接到该封装基板19，且该半导体芯片17的信号(signal)电性功能的传输速度为高速需求，以提升终端产品效能，但该半导体芯片17的部分电性功能(如电源或接地)的传输速度需求不高，故若该电源或接地的电性功能仍通过该导电硅穿孔101进行传输，将导致制作成本的浪费。例如，需制作该电源或接地的电性功能所用的导电硅穿孔101，因而需增加该硅板体10的面积，且于制作该导电硅穿孔101，因需具备一定深宽比的控制(即该导电硅穿孔101的深宽比)，才能制作出适用的硅中介板1a，因而往往需耗费大量制程时间及化学药剂的成本，进而提高制程难度及制作成本。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，能避免发生植球状况不佳等可靠度问题。
本发明的电子封装件，包括：一包覆层；至少一中介板，其嵌埋于该包覆层中且具有多个导电穿孔；多个导电柱，其形成于该包覆层中；以及电子元件，其设于该包覆层上且电性连接该导电柱与该导电穿孔。
前述的电子封装件中，该包覆层的表面齐平该中介板的表面。
前述的电子封装件中，该包覆层的表面齐平该导电柱的端面。
前述的电子封装件中，该导电穿孔外露于该包覆层的表面。
前述的电子封装件中，该导电柱的端面外露于该包覆层的表面。
前述的电子封装件中，该电子元件为主动元件、被动元件或其二者组合。
前述的电子封装件中，该电子元件经由线路结构电性连接该导电柱与该导电穿孔。
前述的电子封装件中，还包括形成于该包覆层上且电性连接该导电柱与该导电穿孔的线路结构。进一步，还包括形成于该线路结构上的多个导电元件，该多个导电元件经由该线路结构电性连接该导电柱与该导电穿孔。
前述的电子封装件中，还包括形成于该包覆层上且电性连接该导电柱与该导电穿孔的多个导电元件。
本发明亦提供一种电子封装件的制法，包括：提供一包覆层，其嵌埋有至少一中介板与多个导电柱，其中，该中介板具有多个导电穿孔；以及设置电子元件于该包覆层的其中一侧上，且令该电子元件电性连接该导电柱与该导电穿孔。
前述的制法中，还包括：提供第一线路结构；将该导电柱与该中介板结合于该第一线路结构上，以令该第一线路结构电性连接该导电柱与该导电穿孔；以及将该包覆层结合于该第一线路结构上，以令该包覆层包覆该中介板与该导电柱。
前述的制法中，还包括于该包覆层上形成第二线路结构，以令该电子元件设于该第二线路结构上，使该电子元件经由该第二线路结构电性连接该导电柱与该导电穿孔。
前述的制法中，还包括于该包覆层的另一侧上形成多个导电元件，且令该多个导电元件电性连接该导电柱与该导电穿孔。
本发明又提供一种电子封装件的制法，包括：提供一电子元件；将多个导电柱与至少一中介板结合于该电子元件上，其中，该中介板具有多个导电穿孔，且令该电子元件电性连接该导电柱与该导电穿孔；以及经由包覆层包覆该中介板与该导电柱。
前述的制法中，还包括形成第一线路结构于该包覆层上，以令该第一线路结构电性连接该导电柱与该导电穿孔。
前述的制法中，还包括：形成第二线路结构于该电子元件上；将该导电柱与该中介板结合于该第二线路结构上，且令该第二线路结构电性连接该导电柱与该导电穿孔；以及将该包覆层结合于该第二线路结构上，以令该包覆层包覆该中介板与该导电柱。
前述的制法中，还包括于该包覆层上形成多个导电元件，且令该多个导电元件电性连接该导电柱与该导电穿孔。
前述的两种制法中，该包覆层具有相对的第一表面与第二表面，且其第二表面齐平该中介板的表面。
前述的两种制法中，该包覆层具有相对的第一表面与第二表面，且其第二表面齐平该导电柱的端面。
前述的两种制法中，该包覆层具有相对的第一表面与第二表面，且该导电穿孔外露于该包覆层的第二表面。
前述的两种制法中，该包覆层具有相对的第一表面与第二表面，且该导电柱的端面外露于该包覆层的第二表面。
前述的两种制法中，该电子元件为主动元件、被动元件或其二者组合。
由上可知，本发明的电子封装件及其制法，主要经由该导电柱作为电子元件的部分电性功能(如电源或接地)的电性传输路径，以减少该导电穿孔的制作数量，故相较于现有技术，本发明不仅能减少制程时间及化学药剂的成本，且能制作小尺寸的中介板以取代现有大面积硅中介板，因而能提高良率。
此外，经由该包覆层包覆该中介板，以于后续形成该封装材时，该包覆层与该封装材之间的热膨胀系数相匹配，因而容易平均分散热应力，故相较于现有技术，本发明于热循环时，能避免该包覆层产生翘曲，进而避免发生植球状况不佳等可靠度问题。
附图说明
图1为现有封装结构的剖视示意图。
图2A至图2G为本发明的电子封装件的制法的第一实施例的剖视示意图。
图2G’及图2G”为对应图2G的其它实施例的剖视示意图。
图2H为图2G的后续制程的剖视示意图。
图3A至图3E为本发明的电子封装件的制法的第二实施例的剖视示意图。
图3A’为对应图3A的其它实施例的剖视示意图。
图3E’及图3E”为对应图3E的其它实施例的剖视示意图。
图4及图4’为本发明的电子封装件的其它实施例的剖视示意图。
符号说明
1 封装结构 1a 硅中介板
10 硅板体 101 导电硅穿孔
11 介电层 12 线路层
13,15 绝缘保护层 14 第一导电元件
16 第二导电元件 160 凸块底下金属层
17 半导体芯片 171,191,292 底胶
18 封装材 19 封装基板
192 焊球 2,2’,2”,3,3’,3”,4,4’ 电子封装件
2a 中介部 20,30 第一线路结构
200 第一绝缘层 201 第一线路重布层
21 中介板 21a 第一侧
21b 第二侧 210 导电穿孔
210a,210b 端面 22 导电体
22a,23a,23b 端面 23 导电柱
24 结合层 25 包覆层
25a 第一表面 25b 第二表面
26,36 第二线路结构 260,360 第二绝缘层
261,361 第二线路重布层 27 导电元件
28 绝缘保护层 29 电子元件
29a 作用面 29b 非作用面
290 电极垫 291 导电凸块
8 布线板件 8a 散热件
80,91 粘着层 9 承载板
90 离型层 S 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2G为本发明的电子封装件2的制法的第一实施例的剖面示意图。
如图2A所示，提供一设于承载板9上的第一线路结构20，且该第一线路结构20上形成有多个导电柱23。
在本实施例中，该第一线路结构20包括至少一第一绝缘层200与至少一设于该第一绝缘层200上的第一线路重布层(Redistribution layer，简称RDL)201。例如，形成该第一线路重布层201的材料为铜，且形成该第一绝缘层200的材料例如为聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。
此外，该承载板9例如为半导体材料(如硅或玻璃)的板体，其上以涂布方式依序形成有一离型层90与一粘着层91，以供该第一线路结构20设于该粘着层91上。
又，该导电柱23设于该第一线路重布层201上并电性连接该第一线路重布层201，且形成该导电柱23的材料为如铜的金属材或焊锡材。
如图2B所示，将至少一中介板21设于该第一线路结构20上，且该中介板21具有相对的第一侧21a与第二侧21b。
在本实施例中，该中介板21为硅中介板(Through Silicon interposer，简称TSI)，其具有多个外露于该第一侧21a的导电穿孔210，如导电硅穿孔(Through-siliconvia，简称TSV)。应可理解地，该导电穿孔210的结构态样繁多，如端处具有垫部，并无特别限制。
此外，该中介板21的第一侧21a以该导电穿孔210的外露端面210a经由多个导电体22结合至该第一线路结构20上以电性连接该第一线路重布层201。例如，该导电体22为如导电线路、或如铜柱、焊锡球等金属凸块、或焊线机制作的钉状(stud)导电物，但不限于此。进一步，可依需求以如底胶的结合层24包覆该些导电体22。
如图2C所示，形成一包覆层25于该第一线路结构20上，以令该包覆层25包覆该中介板21、结合层24与该些导电柱23，其中，该包覆层25具有相对的第一表面25a与第二表面25b，且其以第一表面25a结合该第一线路结构20。接着，经由整平制程，使该包覆层25的第二表面25b齐平该导电柱23的端面23b与该中介板21的第二侧21b(或该导电穿孔210的另一端面210b)，令该导电柱23的端面23b与该中介板21的第二侧21b(或该导电穿孔210的另一端面210b)外露于该包覆层25的第二表面25b。
在本实施例中，该包覆层25为绝缘材，如环氧树脂的封装胶体，其可用压合(lamination)或模压(molding)的方式形成于该第一线路结构20上。
此外，该整平制程经由研磨方式，移除该导电柱23的部分材料、该中介板21的第二侧21b的部分材料与该包覆层25的部分材料。
如图2D所示，形成一第二线路结构26于该包覆层25的第二表面25b上，且令该第二线路结构26电性连接该些导电柱23与该中介板21的导电穿孔210。
在本实施例中，该第二线路结构26包括多个第二绝缘层260、及设于该第二绝缘层260上的多个第二线路重布层(RDL)261，且最外层的第二绝缘层260可作为防焊层，以令最外层的第二线路重布层261外露于该防焊层。或者，该第二线路结构26亦可仅包括单一第二绝缘层260及单一第二线路重布层261。
此外，形成该第二线路重布层261的材料为铜，且形成该第二绝缘层260的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)或其它等的介电材。
如图2E所示，移除该承载板9及其上的离型层90与粘着层91，以外露该第一线路结构20。
在本实施例中，该包覆层25、中介板21与该些导电柱23可作为中介部2a，其可依需求包含该第一线路结构20及/或第二线路结构26。
如图2F所示，于最外层的第二线路重布层261上接置一电子元件29，且可于该第一线路结构20上形成多个如焊球的导电元件27。
在本实施例中，可形成一如防焊层的绝缘保护层28于该第一线路结构20上，且于该绝缘保护层28上形成多个开孔，以令该第一线路重布层201外露于该些开孔，从而供结合该导电元件27。
此外，该电子元件29为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体芯片，且该被动元件例如为电阻、电容及电感。例如，该电子元件29为半导体芯片，如逻辑(logic)芯片，其具有相对的作用面29a与非作用面29b，且以其作用面29a的电极垫290经由多个如焊锡材料的导电凸块291采用覆晶方式设于该第二线路重布层261上并电性连接该第二线路重布层261，并以底胶292包覆该些导电凸块291；或者，该电子元件29以其非作用面29b设于该第二线路结构26上，并可经由多个焊线(图略)以打线方式电性连接该第二线路重布层261；亦或通过如导电胶或焊锡等导电材料(图略)电性连接该第二线路重布层261。然而，有关该电子元件29电性连接该第二线路重布层261的方式不限于上述。
如图2G所示，沿如图2F所示的切割路径S对该中介部2a进行切单制程，以获取该电子封装件2。
在本实施例中，可经由该些导电元件27接置于一布线板件8上侧，如有机材板体(如具有核心层与线路部的封装基板(substrate)或具有线路部的无核心层式(coreless)封装基板)或无机材板体(如硅板材)，且该布线板件8下侧可接置于一如电路板的电子装置(图未示)上，并于该布线板件8上侧形成封装材(图略)以包覆该电子封装件2。进一步，如图2H所示，可依需求配置一散热件8a于该布线板件8上，且该散热件8a经由该粘着层80结合于该布线板件8上，并使该散热件8a结合于该电子元件29的非作用面29b上。
此外，在另一实施例中，如图2G’所示的电子封装件2’，可依需求省略该第二线路结构26的制作，以令该电子元件29接置于该中介板21与该导电柱23上，底胶292接触该包覆层25的第二表面25b。具体地，该电子元件29经由该些导电凸块291电性连接该导电穿孔210与该导电柱23。
或者，在其它实施例中，如图2G”所示的电子封装件2”，亦可依需求省略该第一线路结构20的制作，以令该中介板21的导电穿孔210与该导电柱23经由该些导电元件27接置该布线板件8。
请参阅图3A至图3D，其为本发明的电子封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于电子元件的设置步骤，其它制程大致相同，故以下不再赘述相同处。
如图3A所示，先于承载板9的离型层90(或粘着层91)上设置电子元件29，再于该电子元件29上形成第二线路结构36，且该第二线路结构36包括多个第二绝缘层360及设于该第二绝缘层360上的多个第二线路重布层(RDL)361。
在另一实施例中，可依需求省略该第二线路结构36的制作，以令该导电柱23接置该电子元件29的电极垫290上，如图3A’所示。
如图3B所示，接续图3A的制程，将中介板21以其第二侧21b经由导电体22与结合层24设于该第二线路结构36上。
如图3C所示，以包覆层25包覆该中介板21、结合层24与该些导电柱23，再进行整平制程。接着，形成一第一线路结构30于该包覆层25的第一表面25a上，且该第一线路结构30电性连接该些导电柱23与该中介板21的导电穿孔210。
如图3D所示，移除该承载板9及其上的离型层90，以外露该电子元件29，再进行切单制程以获取该电子封装件3。
在本实施例中，该电子封装件3可经由该些导电元件27接置于一布线板件8(如图3E所示)，且可依需求配置该散热件8a(见图2G)于该布线板件8上。
此外，若接续图3A’的制程，可得到如图3E’所示的电子封装件3’，且中介板21经由导电体22结合及电性连接该电子元件29。或者，于图3A的制程，可依需求省略该第一线路结构30的制作，并令该导电元件27接置于该导电穿孔210与该导电柱23上，以形成如图3E”所示的电子封装件3”。
另外，于第一与第二实施例中，均可依需求省略该第一线路结构20,30与第二线路结构26,36的制作，以形成如图4及图4’所示的电子封装件4,4’。
因此，本发明的制法中，以制作成本极低(如一般封装制程用的铜柱制程)的导电柱23作为该电子元件29与该布线板件8之间的电性传输结构，故相较于现有技术，即使接置于该中介部2a上的电子元件29的数量繁多，本发明的电子封装件2,2’,2”,3,3’,3”,4,4’仍可制作较少的导电穿孔210，因而能减少制程时间及化学药剂的成本，进而降低制程难度及制作成本，以提高良率。
此外，本发明的制法中，经由小尺寸的中介板21取代现有大面积硅中介板，故相较于现有技术的单一大尺寸硅中介板的良率(如制作10个TSV的良率为0.910)，本发明的每一个中介板21的良率较高(如单一个中介板21制作5个TSV的良率为0.95)，致使整体中介部2a的良率较高(整体10个TSV的良率为0.95)。
又，经由该包覆层25包覆该些中介板21，以于后续形成该封装材时，该包覆层25与该封装材之间的热膨胀系数(CTE)相匹配，因而容易平均分散热应力，故于热循环(thermalcycle)时，能避免该中介部2a产生翘曲，因而能避免发生植球状况不佳(即该导电元件27掉落而电性断路)、导电元件27不沾锡(non-wetting)或该布线板件8分裂等可靠度问题，进而能提升应用该电子封装件的终端电子产品(如电脑、手机等)的可靠度问题。
另外，本发明的电子元件29的部分电性功能(如电源或接地)经由导电柱23作为电性传输路径，因而本发明无需制作大面积的中介板21，故相较于现有技术，本发明能有效降低生产成本。
本发明还提供一种电子封装件2,2’,2”,3,3’,3”,4,4’，包括一包覆层25、至少一中介板21、多个导电柱23以及至少一电子元件29。
所述的包覆层25具有相对的第一表面25a与第二表面25b。
所述的中介板21嵌埋于该包覆层25中，且该中介板21具有相对的第一侧21a与第二侧21b、及多个连通该第一侧21a与第二侧21b的导电穿孔210。
所述的导电柱23形成于该包覆层25中并连通该包覆层25的第一表面25a与第二表面25b。
所述的电子元件29形成于该包覆层25的第二表面25b上且电性连接该导电柱23与该导电穿孔210。
在一实施例中，该包覆层25的第一表面25a齐平该中介板21的第一侧21a的表面(如图2G”、图3E、图3E”、图4及图4’所示)；或者，该包覆层25的第二表面25b齐平该中介板21的第二侧21b的表面(如图2G、图2G’、图3E’、图4及图4’所示)。
在一实施例中，该包覆层25的第一表面25a齐平该导电柱23的端面23a(如图2G”、图3E、图3E”、图4及图4’所示)；或者，该包覆层25的第二表面25b齐平该导电柱23的端面23b(如图2G、图2G’、图3E’、图4及图4’所示)。
在一实施例中，该导电穿孔210外露于该包覆层25的第一表面25a或第二表面25b。
在一实施例中，该导电柱23的端面23a外露于该包覆层25的第一表面25a；或者，该导电柱23的端面23b外露于该包覆层25的第二表面25b。
在一实施例中，该电子元件29为主动元件、被动元件或其二者组合。
在一实施例中，该电子元件29经由该第二线路结构26,36电性连接该导电柱23与该导电穿孔210。
在一实施例中，所述的电子封装件2,2’,3,3’还包括形成于该包覆层25上的第一线路结构20,30及/或第二线路结构26,36，电性连接该导电柱23与该导电穿孔210。例如，可于该包覆层25上的第一线路结构20,30上形成多个导电元件27，其经由该第一线路结构20,30电性连接该导电柱23与该导电穿孔210。
在一实施例中，所述的电子封装件2”,3”,4,4’还包括形成于该包覆层25的第一表面25a上的多个导电元件27，其电性连接该导电柱23与该导电穿孔210。
综上所述，本发明的电子封装件及其制法中，经由该导电柱与该中介板嵌埋于该包覆层中以作为中介部，以减少中介板中导电穿孔的数量，故不仅能降低成本，且能提高良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (23)

1.一种电子封装件，其特征在于，包括：
一包覆层；
至少一中介板，其嵌埋于该包覆层中且具有多个导电穿孔；
多个导电柱，其形成于该包覆层中；以及
至少一电子元件，其设于该包覆层上且电性连接该导电柱与该导电穿孔。
2.根据权利要求1所述的电子封装件，其特征在于，该包覆层的表面齐平该中介板的表面。
3.根据权利要求1所述的电子封装件，其特征在于，该包覆层的表面齐平该导电柱的端面。
4.根据权利要求1所述的电子封装件，其特征在于，该导电穿孔外露于该包覆层的表面。
5.根据权利要求1所述的电子封装件，其特征在于，该导电柱的端面外露于该包覆层的表面。
6.根据权利要求1所述的电子封装件，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
7.根据权利要求1所述的电子封装件，其特征在于，该电子元件经由线路结构电性连接该导电柱与该导电穿孔。
8.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括形成于该包覆层上且电性连接该导电柱与该导电穿孔的线路结构。
9.根据权利要求8所述的电子封装件，其特征在于，该电子封装件还包括形成于该线路结构上的多个导电元件，且该多个导电元件经由该线路结构电性连接该导电柱与该导电穿孔。
10.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括形成于该包覆层上的多个导电元件，且该多个导电元件电性连接该导电柱与该导电穿孔。
11.一种电子封装件的制法，其特征在于，包括：
提供一包覆层，其嵌埋有至少一中介板与多个导电柱，且该中介板具有多个导电穿孔；以及
设置电子元件于该包覆层的其中一侧上，且令该电子元件电性连接该导电柱与该导电穿孔。
12.根据权利要求11所述的电子封装件的制法，其特征在于，该制法还包括：
提供第一线路结构；
将该导电柱与该中介板结合于该第一线路结构上，以令该第一线路结构电性连接该导电柱与该导电穿孔；以及
将该包覆层结合于该第一线路结构上，以令该包覆层包覆该中介板与该导电柱。
13.根据权利要求11或12中任一项所述的电子封装件的制法，其特征在于，该制法还包括于该包覆层上形成第二线路结构，以令该电子元件设于该第二线路结构上，使该电子元件经由该第二线路结构电性连接该导电柱与该导电穿孔。
14.根据权利要求11所述的电子封装件的制法，其特征在于，该制法还包括于该包覆层的另一侧上形成多个导电元件，以令该多个导电元件电性连接该导电柱与该导电穿孔。
15.一种电子封装件的制法，其特征在于，包括：
提供一电子元件；
将多个导电柱与至少一中介板结合于该电子元件上，其中，该中介板具有多个导电穿孔，且令该导电柱与该导电穿孔电性连接该电子元件；以及
经由包覆层包覆该中介板与该导电柱。
16.根据权利要求15所述的电子封装件的制法，其特征在于，该制法还包括形成第一线路结构于该包覆层上，以令该第一线路结构电性连接该导电柱与该导电穿孔。
17.根据权利要求15或16中任一项所述的电子封装件的制法，其特征在于，该制法还包括：
形成第二线路结构于该电子元件上；
将该导电柱与该中介板结合于该第二线路结构上，以令该第二线路结构电性连接该导电柱与该导电穿孔；以及
将该包覆层结合于该第二线路结构上，以令该包覆层包覆该中介板与该导电柱。
18.根据权利要求15所述的电子封装件的制法，其特征在于，该制法还包括于该包覆层上形成多个导电元件，以令该多个导电元件电性连接该导电柱与该导电穿孔。
19.根据权利要求11或15中任一项所述的电子封装件的制法，其特征在于，该包覆层具有相对的第一表面与第二表面，且该第二表面齐平该中介板的表面。
20.根据权利要求11或15中任一项所述的电子封装件的制法，其特征在于，该包覆层具有相对的第一表面与第二表面，且该第二表面齐平该导电柱的端面。
21.根据权利要求11或15中任一项所述的电子封装件的制法，其特征在于，该包覆层具有相对的第一表面与第二表面，且该导电穿孔外露于该包覆层的第二表面。
22.根据权利要求11或15中任一项所述的电子封装件的制法，其特征在于，该包覆层具有相对的第一表面与第二表面，且该导电柱的端面外露于该包覆层的第二表面。
23.根据权利要求11或15中任一项所述的电子封装件的制法，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
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