TW202025419A - 低翹曲扇出型封裝結構 - Google Patents
低翹曲扇出型封裝結構 Download PDFInfo
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- TW202025419A TW202025419A TW108115280A TW108115280A TW202025419A TW 202025419 A TW202025419 A TW 202025419A TW 108115280 A TW108115280 A TW 108115280A TW 108115280 A TW108115280 A TW 108115280A TW 202025419 A TW202025419 A TW 202025419A
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Abstract
本發明係一種低翹曲扇出型封裝結構,係包含有一重佈線層、至少一裸晶及一多層封膠;其中各該裸晶之一主動面上多個金屬凸塊係電性連接至該重佈線層的對應內接墊,該多層封膠形成在該重佈線層上以包覆該至少一裸晶,且包含有至少二道不同的膠層,該些膠層具有不同的熱膨脹係數,並分別包覆各該裸晶的側壁;其中最靠近該重佈線層之膠層的熱膨脹係數最小;因此,在形成該多層封膠之高溫製程步驟中,選擇該些膠層的適當熱膨脹係數可減緩膠層與其相接材料層之間的翹曲現象。
Description
本發明係關於一種扇出型封裝結構,尤指一種低翹曲扇出型封裝結構。
相較於使用一預先成型基板的封裝結構,以一扇出型晶圓級封裝製程(FOWLP)或扇出型面板級封裝(FOPLP)製程封裝而成的扇出型封裝結構具有更薄厚度。
在封裝製程中,如圖9所示,先在一玻璃載板40上形成有一黏膠層41,再於該黏膠層41上形成一重佈線層61(RDL);再將多個裸晶62設置在該重佈線層61上,並與該重佈線層61電性連接;之後,以一膠體63包覆該些裸晶62。將該玻璃載板40自該重佈線層61分離,再於該重佈線層61外露的表面上形成多個外凸塊(圖中未示),至此構成該扇出型封裝結構60。
因為在上述封裝製程中使用玻璃載板40,該膠體63的熱膨脹係數與該玻璃載板40的熱膨脹係數並不匹配,造成晶圓或面板在高溫製程步驟中容易出現翹曲現象,使得下一道製程步驟或設備面臨解決翹曲現象,導致扇出型封裝結構的封裝良率減低;因此,目前扇出型封裝結構有必要進一步改良之。
有鑑於以上既有扇出型封裝結構的缺陷,本發明主要目的係提供一種新的扇出型封裝結構。
欲達上述目的所使用的主要技術手段係令該扇出型封裝結構包含有:
一重佈線層,係包含有一介電本體、多個內連接線、多個內接墊及多個外接墊;其中該些內連接線係電性連接該些內接墊及該些外接墊;
至少一裸晶,係具有一主動面及一與主動面相對的背面;其中該主動面具有多個金屬凸塊,該些金屬凸塊係分別電性連接至該重佈線層之對應內接墊;以及
一多層封膠,係形成在該重佈線層上並包覆該至少一裸晶;其中該多層封膠包含:
一第一膠層係形成在該重佈線層上並包覆各該裸晶的側壁的第一部分、該些金屬凸塊及該些內接點;其中該第一膠層具有一第一熱膨脹係數;以及
一第二膠層係形成在該第一膠層上並包覆各該至少一裸晶的側壁的第二部分、該些金屬凸塊及該些內接點;其中該第二膠層具有一第二熱膨脹係數,而該第一熱膨脹係數小於該第二熱膨脹係數。
由上述可知,本發明的扇出封裝結構主要使用一多層封膠,且該多層封膠體包含具有不同的熱膨脹係數的膠層,其中靠近重佈線層之膠層的熱膨脹係數為最小;因此,在形成該多層封膠之步驟中,可選擇具有合適熱膨脹係數的膠層,在高溫的製程中,如此各膠層與其相接的材料層之間的翹曲現象可被改善。
欲達上述目的所使用的主要技術手段係令另一扇出型封裝結構包含有:
一第一重佈線層,係包含有一第一介電本體、多個第一內連接線及多個第一內接墊;其中該些第一內連接線係電性連接該些第一內接墊;
至少一裸晶,係具有一主動面及一與主動面相對的背面;其中該主動面具有多個金屬凸塊,該些金屬凸塊係分別電性連接至該第一重佈線層之對應第一內接墊;
一多層封膠,係形成在該重佈線層上並包覆該至少一裸晶;其中該多層封膠包含:
一第一膠層係形成在該重佈線層上並包覆各該裸晶的側壁的第一部分、該些金屬凸塊及該些內接點;其中該第一膠層具有一第一熱膨脹係數;以及
一第二膠層係形成在該第一膠層上並包覆各該至少一裸晶的側壁的第二部分、該些金屬凸塊及該些內接點;其中該第二膠層具有一第二熱膨脹係數,而該第一熱膨脹係數小於該第二熱膨脹係數;以及
一第二重佈線層,係形成在該第二膠層的頂面,並包含有一第二介電本體、多個第二內連接線、多個第二內接墊及多個第二外接墊;其中該些第二內連接線係電性連接該些第二內接墊及該些第二外接墊。
由上述可知,本發明的扇出封裝結構主要使用一多層封膠,且該多層封膠體包含具有不同的熱膨脹係數的膠層,其中靠近重佈線層之膠層的熱膨脹係數為最小;因此,在形成該多層封膠之步驟中,可選擇具有合適熱膨脹係數的膠層,在高溫的製程中,如此各膠層與其相接的材料層之間的翹曲現象可被改善。
本發明提供一種扇出型封裝結構,減低扇出型封裝結構在高溫製程步驟中的翹曲現象,以下配合數個實施例及圖式詳加說明本發明的技術內容。
請參閱圖1F所示,本發明扇出型封裝結構1的第一實施例,而圖1A至圖1E則是圖1F扇出型封裝結構的製法;在第一實施例中,該製法採用晶片優先製程步驟(chip-first process)。如圖1F所示,該扇出型封裝結構1係包含有一第一重佈線層10、至少一裸晶20及多層封膠體30。
上述第一重佈線層10包含有一介電本體11、多個內連接線12、多個內接墊13及多個外接墊14;其中介電本體11係由聚合物材料製成,例如聚醯亞胺。該些內連接線12電性連接該些內接墊13及該些外接墊14。多個錫球141分別形成在對應的外接墊14上,而該些外接墊14是作為與外部電子元件或印刷電路板電性連接用。
各裸晶20包含一主動面21及一與該主動面21相對的背面22;其中該主動面21具有多個金屬凸塊211,以與該第一重佈線層10的對應內接墊13電性連接。
上述多層封膠體30係形成在該第一重佈線層10上,以包覆該些裸晶21。該多層封膠體30具有至少二道膠層,以分別包覆各裸晶20之側壁的不同部分,且該些膠層具有不同的熱膨脹係數(CTE);其中靠近該第一重佈線層10的膠層的熱膨脹係數為最低。在第一實施例中,多層封膠30依序由第一膠層31、第二膠層32及第三膠層33所組成,其中該第一膠層31具有一第一熱膨脹係數,該第二膠層32具有一第二熱膨脹係數,該第一膠層33具有一第三熱膨脹係;其中該第一熱膨脹係數小於第二熱膨脹係數,而該第三熱膨脹係數小於第二熱膨脹係數。
以下進一步說明圖1F的扇出型封裝結構1的製法,首先請參閱圖1A,先準備一玻璃載板40,並於該玻璃載板40上形成有一黏膠層41,再將多個裸晶20放置在該黏膠層41上,以黏著在該玻璃載板40上。於本實施例中,係以各裸晶20的背面22放置在該黏膠層41上,而具有多個金屬凸塊211之主動面21則朝向遠離該玻璃載板40方向。如圖1B所示,依序將第二膠層32、第三膠層33及第一膠層31’形成在該黏膠層41上,該第二膠層32係包覆各該裸晶20的側壁的第一部分201,該側壁的第一部分201係從各該裸晶20的背面22起算的第一高度位置23,如圖1B所示的h2標記即為該第二膠層32的高度;該第三膠層33形成在該第二膠層32上,並且包覆各該晶片20的側壁的第二部分202,該第二部分是介於第一高度位置23與第二高度位置24之間,如圖1B所示的h3標記即為該第三膠層33的高度;該第一膠層31’形成在該第三膠層33上,並且包覆各該晶片20的側壁的第三部分203,該第三部分203是介於第二高度位置24與各該晶片20的主動面21之間,如圖1B所示的h1標記即為該第一膠層31’的高度。在第一實施例中,該第一膠層31’可進一步包覆該些金屬凸塊211。
如圖1B及圖1C所示,對該第一膠層31’進行一減薄製程(例如研磨製程)直到該些金屬凸塊211自減薄後之第一膠層31外露,故該第一膠層31的表面與該些金屬凸塊211的表面係共平面;此外,在減薄製程後,該第一膠層31的厚度、該第二膠層32的厚度與該第三膠層33的厚度可以相同也可以不同。如圖1D所示,第一重佈線層10係形成在該第一膠層31及該些金屬凸塊211上,以與該些金屬凸塊211電性連接。於第一實施例中,多個錫球141分別形成在該第一重佈線層10之對應外接墊14上。
如圖1D及1E所示,將該玻璃載板40脫離並將黏膠層41移除,以構成圖1F所示的扇出型封裝結構1;此時,各該裸晶20之背面22即外露。再如圖1F所示,該第二膠層32的上表面321與各該裸晶20的背面共平面。
由上述本發明扇出型封裝結構1的製法可知,當該些裸晶20黏著於玻璃載板40後且在形成第一重佈線層10之前,多層封膠30係形成在該玻璃載板40上;因此,第二膠層32的熱膨脹係數可選擇接近於玻璃載板40的熱膨脹係數,如此一來,在高溫製程步驟中,該玻璃載板40與第二膠層32之間的翹曲現象可減緩;此外,由於該玻璃載板40的熱膨脹係數與該第一重佈線層10之介電本體11的熱膨脹係數差距大,故第一膠層31的熱膨脹係數可選擇接近於該介電本體11的熱膨脹係數;如此,於接下來的高溫製程步驟中,該第一膠層31與介電本體11之間的翹曲現象可減緩。
如圖2所示,係為本發明扇出型封裝結構1a的第二實施例,其結構大致與圖1F扇出型封裝結構1相同,惟本實施例扇出型封裝結構1a的多層封膠體30只包含一第一膠層31及一第二膠層32;其中第一膠層31的第一熱膨脹係數低於第二膠層32之第二熱膨脹係數,且第二膠層32的第二熱膨脹係數係與該玻璃載板40的熱膨脹係數相近;此外,該第一膠層31的厚度及該第二膠層32的厚度可相同或不同。
如圖3G所示,係為本發明扇出型封裝結構1b的第三實施例,而圖3A至圖3F則是圖3G扇出型封裝結構1b的製法;在第三實施例中,該製法採用重佈線層優先製程步驟(RDL-first process)。如圖3G所示,該扇出型封裝結構1b的結構大部份與圖1F扇出型封裝結構1大致相同,惟第二膠層32’進一步包覆各該裸晶20之背面22。
以下進一步說明圖3G所示之扇出型封裝結構1b的製法,首先請參閱圖3A,準備一玻璃載板40,並於該玻璃載板40上形成有一黏膠層41,於該黏膠層41上形成一第一重佈線層10;其中該第一重佈線層10之多個內接墊13係外露在介電本體11之頂面。如圖3B所示,將多個裸晶20放置在該第一重佈線層10上,即各該裸晶20之主動面21的金屬凸塊211係對應電性連接至該第一重佈線層10上之內接墊13。再如圖3C所示,相較其他膠層選擇熱膨脹係數接近介電本體11的熱膨脹係數的第一膠層31來形成在該介電本體11上,並包覆各該裸晶20的側壁的第三部分203與各該裸晶20之金屬凸塊211。如圖3D所示,形成在該第一膠層31上的第三膠層33包覆各該裸晶20之側壁的第二部分202;如圖3E所示,形成在該第三膠層33上的第二膠層32’包覆各該裸晶20之側壁的第一部分201與各該裸晶20的背面22。
如圖3E及3F所示,該玻璃載板40自該第一重佈線層10上脫離並將黏膠層41移除,使該第一重佈線層10的外接墊14外露,再如圖3G所示,多個錫球141分別形成在該第一重佈線層10上之對應外接墊14上,至此完成扇出型封裝結構1b。
如圖4A至圖4C所示,同樣以重佈線層優先製程步驟(RDL-first process)封裝圖1F所示之扇出型封裝結構1。在本實施例中,即如同圖3E的第二膠層32’形成後,對該第二膠層32’進行研磨,如圖4A所示,直到各該裸晶20之背面22外露;此時,各該裸晶20的背面22與該第二膠層32係共平面。如圖4A及圖4B所示,將該玻璃載板40自該第一重佈線層10上脫離並將黏膠層41移除,使該些外接墊14外露;如圖4C所示,多個錫球141分別形成在對應的外接墊14上,至此構成圖1F所示的扇出型封裝結構1。
如圖5所示,係為本發明扇出型封裝結構1c的第四實施例,其大多結構與圖3G所示之扇出型封裝結構1b相似,惟本實施例扇出型封裝結構1c只包含有第一膠層31及第二膠層32’;其中該第一膠層31的第一熱膨脹係數低於該第二膠層31’的第二熱膨脹係數。該第一膠層31的第一熱膨脹係數接近於該第一重佈線層10之介電本體11的熱膨脹係數。
如圖6F所示,係為本發明扇出型封裝結構1d的第五實施例,而圖6A至圖6E則是圖6F扇出型封裝結構1d的製法;在第五實施例中,該製法採用晶片置中製程步驟(chip-middle process)。如圖6F所示,在第五實施例中,該扇出型封裝結構1d包含有第一重佈線層10、多個裸晶20、一多層封膠體30、一第二重佈線層10’及多個金屬柱50。
該第一重佈線層10包含有一介電本體11、多個內連接線12及多個內接墊13;其中該介電本體11係由聚合物材料製成,例如聚醯亞胺(PI)。該些內連接線12電性連接該些內接墊13。
各該裸晶20包含有一主動面21及一相對該主動面21之背面22;其中該主動面21包含有多個金屬凸塊211,以電連接至該第一重佈線層10的對應內接墊13。
該多層封膠30係形成在該第一重佈線層10與該第二重佈線層10’之間,以包覆該些裸晶20;又該多層封膠30包含有至少二道膠層,以對應包覆各該裸晶20之側壁的不同部分。在第五實施例中,該多層封膠30具有一第一膠層31、一第三膠層33及一第二膠層32’。該第一膠層31具有一第一熱膨脹係數,該第二膠層32’具有一第二熱膨脹係數,第三膠層33具有一第三熱膨脹係數;其中該第一及第三熱膨脹係數均小於第二熱膨脹係數。
該第二重佈線層10’具有一介電本體11’、多個內連接線12’、多個內接墊13’及多個外接墊14’;其中該介電本體11’係由聚合物材料製成,例如聚醯亞胺(PI)。該些內連接線12’電性連接該些內接墊13’及該些外接墊14’,又該些外接墊14’是作為與外部電子元件或印刷電路板銲接用,而該些內接墊13’透過金屬柱50電性連接至第一重佈線層10的內接墊13,故該第一重佈線層10電連接至第二重佈線層10’。該些金屬柱50穿設在該第一、第三及第二膠層31、33、32’。該第一至第三膠層之厚度可相同或不同。
以下進一步說明圖6F之扇出型封裝結構1d的製法,首先請參閱圖6A所示,準備一玻璃載板40,該玻璃載板40的第一表面形成有一黏膠層41,一第一重佈線層10係形成在該黏膠層41上,該第一重佈線層10的多個內接墊13外露於該介電本體11的頂面。如圖6B所示,該些裸晶20分別設置在該第一重佈線層10上,且各該裸晶10之主動面21上之金屬凸塊211電性連接至該第一重佈線層10上之對應內接墊13。該第一膠層31、第三膠層33及第二膠層32’係依序形成在該第一重佈線層10上,以包覆各該裸晶20之側壁的不同部分。該第二膠層32’進一步包覆各該裸晶20的背面22。請參閱圖6C,多個穿孔301係穿設該第二膠層32’、第三膠層33及第一膠層31;又該些金屬柱50係對應形成在穿孔301中,如圖6D所示,該第二重佈線層10’係形成在第二膠層32’及該些金屬柱50上。該第二重佈線10’的外接墊14’係外露,故而多個錫球141’可分別形成於對應的外接墊14’上。
如圖6D及6E所示,將該玻璃載板40係自該第一重佈線層10上脫離並將黏膠層41移除,以完成圖6F所示之扇出型封裝結構1d。
如圖7E所示,為本發明扇出型封裝結構1e的第六實施例,圖7A至圖7D為圖7E扇出型封裝結構1e的製法,在第六實施例中,同樣使用晶片置中製程步驟(chip-middle process),即同圖6C的第二膠層32’形成後,即對該第二膠層32’進行研磨減薄其厚度,如圖7A所示,直到各該裸晶20之背面22外露為止;此時,各該裸晶20的背面22與該第二膠層32係共平面。如圖7B所示,多個穿孔301係穿設於第二膠層32、第三膠層33及第一膠層31,再於該些穿孔301內形成有金屬柱50。如圖7C所示,該第二重佈線層10’形成在該第二膠層32上、各該裸晶20之背面22與該些金屬柱50上。如圖7D所示,將該玻璃載板40自該第一重佈線10上脫離並將黏膠層移除,圖7E所示之扇出型封裝結構1e即完成。
如圖8A所示,係為本發明扇出型封裝結構1f的第七實施例,其大多結構與圖5所示扇出型封裝結構1c相同,惟其只包含第一膠層31及第二膠層32;其中該第一膠層31的第一熱膨脹係數與該第二膠層32的第二熱膨脹係數均與第一及第二重佈線層10、10’之介電本體11、11’的熱膨脹係數相近。
如圖8B所示,係為本發明扇出型封裝結構1g的第八實施例,其與圖7E扇出型封裝結構1e結構大致相同,惟只包含第一膠層31及第二膠層32;其中該第一膠層31的第一熱膨脹係數與該第二膠層32的第二熱膨脹係數均與第一及第二重佈線層10、10’之介電本體11、11’的熱膨脹係數相近。
綜上所述,本發明的扇出封裝結構主要使用一多層封膠,且該多層封膠體包含具有不同的熱膨脹係數的膠層,其中靠近重佈線層之膠層的熱膨脹係數為最小;因此,在形成該多層封膠之步驟中,可選擇具有合適熱膨脹係數的膠層及/或厚度,在高溫的製程中,如此各膠層與其相接的材料層之間的翹曲現象可被改善;此外,在移除玻璃載板之步驟後,扇出型封裝結構之翹曲也可透過選擇具適當的熱膨脹係數及厚度的膠層來改減緩。
以上所述僅是本發明的實施例而已,並非對本發明做任何形式上的限制,雖然本發明已以實施例揭露如上,然而並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明技術方案的範圍內,當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例,但凡是未脫離本發明技術方案的內容,依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾,均仍屬於本發明技術方案的範圍內。
1、1a、1b、1c、1d、1e、1f、1g:扇出型封裝結構
10:第一重佈線10’:第二重佈線
11、11’:介電本體12、12’:內連接線
13、13’:內接墊14、14’:外接墊
141、141’:錫球20:裸晶
201:第一部分202:第二部分
203:第三部分21:主動面
211:金屬凸塊22:背面
30:多層封膠體301:穿孔
31、31’:第一膠層32、32’:第二膠層
321:上表面33:第三膠層
40:玻璃載板41:黏膠層
50:金屬柱60:扇出型封裝結構
61:重佈線層62:裸晶
63:膠體
圖1A至圖1F:本發明對應扇出型封裝結構的第一實施例之製法中不同步驟的剖面圖。
圖2:本發明扇出型封裝結構的第二實施例的剖面圖。
圖3A至圖3G:本發明對應扇出型封裝結構的第三實施例之製法中不同步驟的剖面圖。
圖4A至圖4C:本發明對應扇出型封裝結構的第一實施例之製法中不同步驟的其他剖面圖。
圖5:本發明扇出型封裝結構的第四實施例的剖面圖。
圖6A至圖6F:本發明對應扇出型封裝結構的第五實施例之製法中不同步驟的剖面圖。
圖7A至圖7E:本發明對應扇出型封裝結構的第六實施例之製法中不同步驟的剖面圖。
圖8A:本發明扇出型封裝結構的第七實施例的剖面圖。
圖8B:本發明扇出型封裝結構的第八實施例的剖面圖。
圖9:既有扇出型封裝結構的剖面圖。
1:扇出型封裝結構
10:第一重佈線
11:介電本體
12:內連接線
13:內接墊
14:外接墊
141:錫球
20:裸晶
201:第一部分
202:第二部分
203:第三部分
21:主動面
211:金屬凸塊
22:背面
30:多層封膠體
31:第一膠層
32:第二膠層
321:上表面
33:第三膠層
Claims (10)
- 一種扇出型封裝結構,包括: 一重佈線層,係包含有一介電本體、多個內連接線、多個內接墊及多個外接墊;其中該些內連接線係電性連接該些內接墊及該些外接墊; 至少一裸晶,係具有一主動面及一與主動面相對的背面;其中該主動面具有多個金屬凸塊,該些金屬凸塊係分別電性連接至該重佈線層之對應內接墊;以及 一多層封膠,係形成在該重佈線層上並包覆該至少一裸晶;其中該多層封膠包含: 一第一膠層係形成在該重佈線層上並包覆各該裸晶的側壁的第一部分、該些金屬凸塊及該些內接點;其中該第一膠層具有一第一熱膨脹係數;以及 一第二膠層係形成在該第一膠層上並包覆各該至少一裸晶的側壁的第二部分、該些金屬凸塊及該些內接點;其中該第二膠層具有一第二熱膨脹係數,而該第一熱膨脹係數小於該第二熱膨脹係數。
- 如請求項1所述之扇出型封裝結構,其中該第二膠層的頂面與各該至少一裸晶的背面係共平面。
- 如請求項1所述之扇出型封裝結構,其中該第二膠層係包覆各該至少一裸晶的背面。
- 如請求項1至3中任一項所述之扇出型封裝結構,係進一步包含一第三膠層,該第三膠層係形成於該一膠層與該第二膠層之間,並包覆各該至少一裸晶的側壁的第三部分;其中該第三膠層具有一第三熱膨脹係數,且該第三熱膨脹係數係小於第二熱膨脹係數。
- 如請求項1至3中任一項所述之扇出型封裝結構,係由一晶片優先製程(chip first process)配合一玻璃載板完成封裝。
- 如請求項1至3中任一項所述之扇出型封裝結構,係由一重佈線層優先製程(RDL first process)配合一玻璃載板完成封裝。
- 一種扇出型封裝結構,包括: 一第一重佈線層,係包含有一第一介電本體、多個第一內連接線及多個第一內接墊;其中該些第一內連接線係電性連接該些第一內接墊; 至少一裸晶,係具有一主動面及一與主動面相對的背面;其中該主動面具有多個金屬凸塊,該些金屬凸塊係分別電性連接至該第一重佈線層之對應第一內接墊; 一多層封膠,係形成在該重佈線層上並包覆該至少一裸晶;其中該多層封膠包含: 一第一膠層係形成在該重佈線層上並包覆各該裸晶的側壁的第一部分、該些金屬凸塊及該些內接點;其中該第一膠層具有一第一熱膨脹係數;以及 一第二膠層係形成在該第一膠層上並包覆各該至少一裸晶的側壁的第二部分、該些金屬凸塊及該些內接點;其中該第二膠層具有一第二熱膨脹係數,而該第一熱膨脹係數小於該第二熱膨脹係數;以及 一第二重佈線層,係形成在該第二膠層的頂面,並包含有一第二介電本體、多個第二內連接線、多個第二內接墊及多個第二外接墊;其中該些第二內連接線係電性連接該些第二內接墊及該些第二外接墊。
- 如請求項7所述之扇出型封裝結構,其中該第二膠層的頂面與各該至少一裸晶的背面係共平面。
- 如請求項7所述之扇出型封裝結構,其中該第二膠層係包覆各該至少一裸晶的背面。
- 如請求項7至9中任一項所述之扇出型封裝結構,係進一步包含一第三膠層,該第三膠層係形成於該一膠層與該第二膠層之間,並包覆各該至少一裸晶的側壁的第三部分;其中該第三膠層具有一第三熱膨脹係數,且該第三熱膨脹係數係小於第二熱膨脹係數。
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US8648470B2 (en) * | 2011-01-21 | 2014-02-11 | Stats Chippac, Ltd. | Semiconductor device and method of forming FO-WLCSP with multiple encapsulants |
US20120268899A1 (en) * | 2011-04-21 | 2012-10-25 | Tessera Research Llc | Reinforced fan-out wafer-level package |
US20180190622A1 (en) * | 2014-03-07 | 2018-07-05 | Bridge Semiconductor Corporation | 3-d stacking semiconductor assembly having heat dissipation characteristics |
KR101933408B1 (ko) * | 2015-11-10 | 2018-12-28 | 삼성전기 주식회사 | 전자부품 패키지 및 이를 포함하는 전자기기 |
KR102052900B1 (ko) * | 2016-10-04 | 2019-12-06 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
TWI622142B (zh) * | 2016-11-07 | 2018-04-21 | 財團法人工業技術研究院 | 晶片封裝體以及晶片封裝方法 |
US10511080B2 (en) * | 2017-08-18 | 2019-12-17 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US11101209B2 (en) * | 2017-09-29 | 2021-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution structures in semiconductor packages and methods of forming same |
KR101942740B1 (ko) * | 2017-10-19 | 2019-01-28 | 삼성전기 주식회사 | 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈 |
KR101901713B1 (ko) * | 2017-10-27 | 2018-09-27 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
KR101939046B1 (ko) * | 2017-10-31 | 2019-01-16 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
KR101963292B1 (ko) * | 2017-10-31 | 2019-03-28 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
KR101942744B1 (ko) * | 2017-11-03 | 2019-01-28 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
KR102073956B1 (ko) * | 2017-11-29 | 2020-02-05 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
KR101942746B1 (ko) * | 2017-11-29 | 2019-01-28 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
US10325786B1 (en) * | 2017-12-07 | 2019-06-18 | Sj Semiconductor (Jiangyin) Corporation | Double-sided plastic fan-out package structure having antenna and manufacturing method thereof |
KR20190075647A (ko) * | 2017-12-21 | 2019-07-01 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
KR101922885B1 (ko) * | 2017-12-22 | 2018-11-28 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
KR102039711B1 (ko) * | 2018-03-13 | 2019-11-01 | 삼성전자주식회사 | 팬-아웃 부품 패키지 |
KR20190121560A (ko) * | 2018-04-18 | 2019-10-28 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
KR102070563B1 (ko) * | 2018-06-01 | 2020-01-29 | 삼성전자주식회사 | 전자파 차폐 구조물 및 이를 포함하는 반도체 패키지 |
KR20190140160A (ko) * | 2018-06-11 | 2019-12-19 | 삼성전자주식회사 | 반도체 패키지 |
KR102164794B1 (ko) * | 2018-08-27 | 2020-10-13 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
KR102081088B1 (ko) * | 2018-08-29 | 2020-02-25 | 삼성전자주식회사 | 반도체 패키지 |
KR102427643B1 (ko) * | 2018-09-27 | 2022-08-01 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
US10867879B2 (en) * | 2018-09-28 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
KR102538180B1 (ko) * | 2018-10-01 | 2023-05-31 | 삼성전자주식회사 | 패드 오픈 구조체 및 이를 포함하는 반도체 패키지 |
KR102554016B1 (ko) * | 2018-10-02 | 2023-07-11 | 삼성전자주식회사 | 반도체 패키지 |
KR102543185B1 (ko) * | 2018-10-08 | 2023-06-14 | 삼성전자주식회사 | 반도체 패키지 |
-
2018
- 2018-12-27 US US16/233,883 patent/US20200211980A1/en not_active Abandoned
-
2019
- 2019-05-02 TW TW108115280A patent/TWI715970B/zh active
Also Published As
Publication number | Publication date |
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TWI715970B (zh) | 2021-01-11 |
US20200211980A1 (en) | 2020-07-02 |
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