CN109994438B - 芯片封装结构及其封装方法 - Google Patents

芯片封装结构及其封装方法 Download PDF

Info

Publication number
CN109994438B
CN109994438B CN201910251627.7A CN201910251627A CN109994438B CN 109994438 B CN109994438 B CN 109994438B CN 201910251627 A CN201910251627 A CN 201910251627A CN 109994438 B CN109994438 B CN 109994438B
Authority
CN
China
Prior art keywords
layer
pad
electrically connected
redistribution
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910251627.7A
Other languages
English (en)
Other versions
CN109994438A (zh
Inventor
席克瑞
秦锋
刘金娥
李小和
崔婷婷
丁渊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai AVIC Optoelectronics Co Ltd
Original Assignee
Shanghai AVIC Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai AVIC Optoelectronics Co Ltd filed Critical Shanghai AVIC Optoelectronics Co Ltd
Priority to CN201910251627.7A priority Critical patent/CN109994438B/zh
Priority to US16/441,501 priority patent/US11257765B2/en
Publication of CN109994438A publication Critical patent/CN109994438A/zh
Application granted granted Critical
Publication of CN109994438B publication Critical patent/CN109994438B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13149—Manganese [Mn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/1316—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive

Abstract

本发明公开了一种芯片封装结构及其封装方法，包括：包封层、重布线层、焊盘组以及多个裸芯片；裸芯片的一侧设置有多个连接柱；包封层覆盖裸芯片和连接柱，且暴露出连接柱远离裸芯片一侧的表面；重布线层位于连接柱远离裸芯片的一侧，且重布线层包括第一重布线路、第二重布线路和第三重布线路；第一重布线路、第二重布线路分别和至少一个连接柱电连接，剩余的连接柱和第三重布线路电连接；焊盘组位于重布线层远离包封层的一侧，且焊盘组包括输入焊盘和输出焊盘。相对于现有技术，封装结构更加简单，由于省去了植球步骤，使得封装结构的制作和使用也更加方便。

Description

芯片封装结构及其封装方法
技术领域
本发明涉及封装技术领域，更具体地，涉及一种芯片封装结构及其封装方法。
背景技术
随着集成电路技术的不断发展，电子产品越来越趋向于小型化、智能化以及高可靠性方向发展，这对电子产品中线路的集成度要求也越来越高。为此，目前的做法主要是将各种工艺制作的芯片集中装配在PCB板(Printed circuit board，印刷线路板)上，芯片之间的信号则通过PCB板上印制的线路进行互通。但存在以下问题：
一方面，在进行芯片的装配时，通常需要对封装好的芯片结构进行植球，然后再焊接到PCB板上，成本高，装配工艺复杂，而且需要对每个植球分别进行焊接操作，工作量大，同时也难以确保每个植球与PCB板之间连接的可靠性，使得电子产品的良率较低；
另一方面，用于芯片之间信号互通的线路占用了PCB板上较大的空间，不利于电子产品的进一步小型化，并且在线路数量较多的情况下，部分线路长度较大，使得电子产品的能耗较高。
发明内容
有鉴于此，本发明提供了一种芯片封装结构及其封装方法，以解决现有技术中存在的技术问题。
本发明提供了一种芯片封装结构，包括：包封层、重布线层、焊盘组以及多个裸芯片；裸芯片的一侧设置有多个连接柱；包封层覆盖裸芯片和连接柱，且暴露出连接柱远离裸芯片一侧的表面；重布线层位于连接柱远离裸芯片的一侧，且重布线层包括第一重布线路、第二重布线路和第三重布线路；第一重布线路、第二重布线路分别和至少一个连接柱电连接，剩余的连接柱和第三重布线路电连接；焊盘组位于重布线层远离包封层的一侧，且焊盘组包括输入焊盘和输出焊盘；输入焊盘和第一重布线路电连接，输出焊盘和第二重布线路电连接；或者，输入焊盘和第二重布线路电连接，输出焊盘和第一重布线路电连接。
本发明提供了一种芯片封装结构的封装方法，包括：提供一衬底基板；提供多个裸芯片，并将裸芯片贴附在衬底基板上；裸芯片的一侧设置有多个连接柱；形成包封层，包封层覆盖裸芯片和连接柱；对包封层进行研磨，暴露出连接柱远离裸芯片一侧的表面；在连接柱远离裸芯片的一侧形成重布线层，重布线层包括第一重布线路、第二重布线路和第三重布线路；其中，第一重布线路、第二重布线路分别和至少一个连接柱电连接，剩余的连接柱和第三重布线电连接；在重布线层远离包封层的一侧形成焊盘组，焊盘组包括输入焊盘和输出焊盘；其中，输入焊盘和第一重布线路电连接，输出焊盘和第二重布线路电连接；或者，输入焊盘和第二重布线路电连接，输出焊盘和第一重布线路电连接；将衬底基板剥离。
此外，本发明还提供了另一种芯片封装结构的封装方法，包括：提供一衬底基板；在衬底基板上形成焊盘组，焊盘组包括输入焊盘和输出焊盘；在焊盘组远离玻璃基板的一侧形成重布线层，重布线层包括第一重布线路、第二重布线路和第三重布线路；其中，第一重布线路和输入焊盘电连接，第二重布线路和输出焊盘电连接；或者，第二重布线路和输入焊盘电连接，第一重布线路和输出焊盘电连接；提供多个裸芯片，裸芯片的一侧设置有多个连接柱；其中，第一重布线路、第二重布线路分别和至少一个连接柱电连接，剩余的连接柱和第三重布线电连接；形成包封层，包封层覆盖裸芯片和连接柱；将衬底基板剥离，暴露出焊盘组的表面。
与现有技术相比，本发明提供的芯片封装结构及其封装方法，至少实现了如下的有益效果：
采用扇出型封装方式对多个裸芯片进行集中封装，裸芯片之间通过重布线层进行信号传输，重布线层可以根据需要设置为单层或多层线路结构，能够有效减小线路所占的空间，有利于提高封装结构的集成度，降低电子产品的能耗。裸芯片上用于外接信号的连接柱通过焊盘组引出，剩余的连接柱通过第三重布线路在封装结构的内部进行连接，也即可以通过一个封装结构代替现有技术中每个芯片单独封装后和PCB板装配的结构，封装结构更加简单，由于省去了植球步骤，使得封装结构的制作和使用也更加方便，有利于降低电子产品的生产成本，并提高电子产品的良率和生产效率。
当然，实施本发明的任一产品不必特定需要同时达到以上所述的所有技术效果。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
被结合在说明书中并构成说明书的一部分的附图示出了本发明的实施例，并且连同其说明一起用于解释本发明的原理。
图1是本发明实施例提供的一种芯片封装结构的平面示意图；
图2是图1中沿A-A方向的一种剖面示意图；
图3是本发明实施例提供的另一种芯片封装结构的平面示意图；
图4是图3中沿B-B方向的一种剖面示意图；
图5是本发明实施例提供的又一种芯片封装结构的平面示意图；
图6是图5中沿C-C方向的一种剖面示意图；
图7是图5中沿C-C方向的另一种剖面示意图；
图8是图1中沿A-A方向的另一种剖面示意图；
图9是图1中沿A-A方向的又一种剖面示意图；
图10是图1中沿A’-A’方向的一种剖面示意图；
图11是本发明实施例提供的一种芯片封装结构的封装方法流程图；
图12-图17是图11所示的封装方法的剖面示意图；
图18是本发明实施例提供的另一种芯片封装结构的封装方法流程图；
图19是图18所示的封装方法的剖面示意图；
图20是本发明实施例提供的又一种芯片封装结构的封装方法流程图；
图21-图24是图20所示的封装方法的剖面示意图；
图25是本发明实施例提供的又一种芯片封装结构的封装方法流程图；
图26是本发明实施例提供的又一种芯片封装结构的封装方法流程图；
图27-图29是图26所示的封装方法的剖面示意图；
图30是本发明实施例提供的又一种芯片封装结构的封装方法流程图；
图31-图35是图30所示的封装方法的剖面示意图；
图36是本发明实施例提供的又一种芯片封装结构的封装方法流程图；
图37是本发明实施例提供的又一种芯片封装结构的封装方法流程图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
在这里示出和讨论的所有例子中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它例子可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
请结合参考图1和图2所示，本发明提供了一种芯片封装结构，包括：包封层10、重布线层20、焊盘组30以及多个裸芯片40；裸芯片40的一侧设置有多个连接柱50；包封层10覆盖裸芯片40和连接柱50，且暴露出连接柱50远离裸芯片40一侧的表面；重布线层20位于连接柱50远离裸芯片40的一侧，且重布线层20包括第一重布线路21、第二重布线路22 和第三重布线路23；第一重布线路21、第二重布线路22分别和至少一个连接柱50电连接，剩余的连接柱50和第三重布线路23电连接；
焊盘组30位于重布线层20远离包封层10的一侧，且焊盘组30包括输入焊盘31和输出焊盘32；输入焊盘31和第一重布线路21电连接，输出焊盘32和第二重布线路22电连接；或者，输入焊盘31和第二重布线路 22电连接，输出焊盘32和第一重布线路21电连接。
本实施例中，裸芯片40可以包括集成电路，裸芯片40的一侧设置多个连接柱50，从而外部信号可以通过连接柱50接入裸芯片40内的集成电路，同时，裸芯片40内集成电路的输出信号也可以通过连接柱50向外部输出。为了使其具有较好的电连接特性，连接柱50可以采用具有较好导电性的材料制成，比如铜、银、金、镍等等，在其他可选的实施例中，连接柱50也可以设计为块状的焊垫结构，但本实施例对此并不作具体限制。
裸芯片40的数量可以根据实际所需的封装结构功能设置，可以理解的是，为了提高封装结构的集成度，封装结构内裸芯片40的数量可以是两个甚至两个以上，图1中仅以设置三个裸芯片40为例进行了示意，后续不再赘述。当然，各裸芯片40的型号及其所具有的功能也可以根据实际需要设置，本实施例的封装结构并不局限于使用相同型号和相同功能的裸芯片40。
裸芯片40和连接柱50通过包封层10覆盖，包封层10的材料可以是 EMC(EpoxyMolding Compound，环氧树脂膜塑料)，具体的，EMC是由环氧树脂为基体树脂，以高性能酚醛树脂为固化剂，加入硅微粉等填料以及多种助剂混配而成的粉状模塑料，具有较好的密封性和易塑封性，从而可以对所覆盖的裸芯片40和连接柱50进行塑封保护。其中，不设置连接柱50的裸芯片40的侧面可以完全覆盖包封层10，也可以仅部分或全部不覆盖包封层10，但本实施例对此并不作具体限制，图2仅以裸芯片40远离连接柱50一侧的表面不覆盖包封层10为例进行了示意。
重布线层20可以对连接柱50的引线逐级放大，实现对裸芯片40的扇出型封装。本实施例中，重布线层20位于连接柱50远离裸芯片40的一侧，且该重布线层20包括第一重布线路21、第二重布线路22和第三重布线路 23，各重布线路的数量可以根据实际情况设置，本实施例对此并不作具体限制。其中，第一重布线路21、第二重布线路22分别和至少一个连接柱 50电连接，同时，焊盘组30的输入焊盘31、输出焊盘32分别和第一重布线路21、第二重布线路22电连接，从而外部信号可以由输入焊盘31接入裸芯片40，裸芯片40的输出信号可以通过和连接柱50电连接的输出焊盘 32向外部输出；当然，焊盘组30的输入焊盘31、输出焊盘32也可以分别和第二重布线路22、第一重布线路21电连接，本实施例对此并不作具体限制。
重布线层20的第三重布线路23和剩余的连接柱50电连接，也即除用于信号输入和输出的连接柱50外，剩余的连接柱50之间可以直接通过第三重布线路23进行线路的排布，实现芯片之间的电连接，可以无需通过焊盘组30引出，从而通过一个封装结构即可实现现有技术中每个芯片单独封装后再和PCB板装配的结构，集成度更高，能够有效适应电子产品的小型化趋势，有利于提高电子产品的生产效率，并且与每个芯片单独封装后通过植球焊接到PCB上的方案相比，成本更低；同时，由于省去了植球工艺，使用更加方便，封装结构的可靠性也更高，有利于提高电子产品的良率；多个裸芯片40集成封装的结构能够有效减小走线距离，降低电子产品的能耗。
重布线层20可以为单层布线结构，比如图1和图2所示。在线路排布较为复杂的情况下，重布线层20也可以为双层或多层结构，比如以图3和图4所示的封装结构为例，各重布线路和第一连接线路24、第二连接线路 25异层设置，在设置两个或者两个以上的输入焊盘31时，为了使输入焊盘31之间具有相同的尺寸以适应连接需求，可以通过第一连接线路24将各输入焊盘31引出至合适的位置；或者，至少存在两条信号相同的第二重布线路22，为了使这两条第二重布线路22能够通过同一个或同一组输出焊盘32将信号引出，可以跨接至少一条第二连接线路25，由于第二连接线路25和第二重布线路22异层设置，能够有效防止第二连接线路25对重布线路产生干扰，相当于线路在横向排布空间受限的情况下增加了线路的纵向排布空间，有利于进一步提高封装结构的集成度。
第一连接线路24和第二连接线路25可以同各重布线路一样采用扇出型封装工艺实现，也即连接线路和重布线路可以共同组成封装结构的重布线层20，且两者的材料可以相同，也可以不同，本实施例对此并不作具体限制。
需要说明的是，为了更加直观地示意本实施例的技术方案，图1至图 4中未示意出其他膜层结构，并且对第一重布线路21、第二重布线路22和第三重布线路23进行了不同图案的填充。可以理解的是，重布线层20的具体线路排布可以根据实际需要设置，图1至图4仅示例性地示意了本实施例的技术方案。
本实施例提供的芯片封装结构，至少具有如下的技术效果：采用扇出型封装方式对多个裸芯片进行集中封装，裸芯片之间通过重布线层进行信号传输，重布线层可以根据需要设置为单层或多层线路结构，能够有效减小线路所占的空间，有利于提高封装结构的集成度，降低电子产品的能耗。裸芯片上用于外接信号的连接柱通过焊盘组引出，剩余的连接柱通过第三重布线路在封装结构的内部进行连接，也即可以通过一个封装结构代替现有技术中多个芯片单独封装后和PCB板装配的结构，封装结构更加简单，由于省去了植球步骤，使得封装结构的制作和使用也更加方便，有利于降低电子产品的生产成本，并提高电子产品的良率和生产效率。
在一些可选的实施例中，请结合参考图5和图6所示，焊盘组30还包括连接焊盘33，连接焊盘33和重布线层20电连接；封装结构还包括至少一个电子器件60，电子器件60包括器件本体61以及设置于器件本体61 上的多个引脚62；引脚62和连接焊盘33电连接。
本实施例中，连接焊盘33和重布线层20电连接，此时连接焊盘33可以直接或通过第三连接线路26间接地和第三重布线路23电连接，也可以和其他重布线路电连接，本实施例对此并不作具体限制，图5和图6仅以前者为例进行了示意，后续不再赘述。
一方面，外接电子器件60有利于提高封装结构中线路排布的灵活性，以适应多种使用需求；另一方面，在进行封装过程中，对于尺寸较大的电子器件60，如将其与裸芯片40一同进行封装，很可能会增加封装结构的尺寸，导致封装结构的集成度难以得到提高，而通过采用将这些电子器件 60外接的方式和封装结构电连接，能够有效确保封装结构的集成度；当然，这些电子器件60也可以是尺寸较小，但需要根据实际情况选择性设置的器件，本实施例对此并不作具体限制。
电子器件60的器件本体61上可以设置多个引脚62，从而可以通过引脚62将电子器件60和连接焊盘33电连接。为了防止电子器件60接入后发生断路现象，第三重布线路23在对应电子器件60的位置应断开设置。
可选的，请继续结合参考图5和图6所示，引脚62通过焊料63和连接焊盘33电连接，也即可以采用焊接工艺将电子器件60焊固在连接焊盘 33上，以确保电连接的稳定性；需要拆除电子器件60时，只需熔化焊料 63即可，拆装操作简单方便，劳动强度低。
焊料63的材料可以是铜、锡、铅、锌、镍、猛、铁或其合金，本实施例对此并不作具体限制。
可选的，请继续结合参考图5和图6所示，电子器件60为电阻、电容、电感、二极管中的任一者，通过合理选择电气器件60的种类和数量，可以使封装结构具有更多的功能，从而使得封装结构的适用范围更广。
可选的，请结合参考图5和图7所示，包封层10包括多个容置腔11；引脚62贯穿连接焊盘33后容置于容置腔11内。
本实施例中，包封层10覆盖了裸芯片40和连接柱50，也即包封层10 的厚度可以设置地较大，此时通过在包封层10中设置容置腔11，使得引脚62长度较大的电子器件60能够较好地适应安装需求。当采用焊接的方式安装电子器件60时，焊料63应填充满引脚62和连接焊盘33之间的间隙，防止外部的水氧影响封装结构的性能，同时增加电性连接的稳定性。
容置腔11腔壁的材料可以和包封层10相同，也可以不同，本实施例对此并不作具体限制。但为了更便于将引脚62容置于容置腔11内，应确保容置腔11的尺寸大于引脚62的尺寸。
可选的，请继续参考图7所示，包封层10远离重布线层20一侧的表面为第一表面m；沿垂直于裸芯片40所在平面的方向上，容置腔11和第一表面m之间的间距为h；其中，h≥0。
本实施例中，在包封层10厚度足够的情况下，容置腔11和第一表面 m之间的间距h可以大于0，也即容置腔11仅贯穿包封层10的部分厚度设置；而在包封层10厚度较小和/或引脚62长度较大的情况下，容置腔11 和第一表面m之间的间距h可以为0，也即容置腔11可以贯穿包封层10 的整个厚度设置，从而无需裁切引脚62也可以将电子器件60安装在封装结构上。
在一些可选的实施例中，请结合参考图1和图8所示，封装结构还包括保护层70；保护层70位于包封层10、裸芯片40远离重布线层20的一侧。
本实施例中，在包封层10、裸芯片40远离重布线层20的一侧设置保护层70，从而保护层70可以和包封层10共同对裸芯片40进行保护，能够有效防止外界环境对裸芯片40的电学性能产生影响。
保护层70的材料可以和包封层10一样，比如两者均为EMC，此时保护层70和包封层10可以均采用注塑工艺成型，有利于减少封装工序，提高电子产品的生产效率。当然，保护层70的材料也可以为其他，本实施例对此并不作具体限制。
可选的，请结合参考图1和图9所示，封装结构还包括柔性基板71；柔性基板71位于保护层70远离重布线层20的一侧。
本实施例中，柔性基板71位于保护层70远离重布线层20的一侧，从而封装结构整体可以以柔性基板71为基底进行面板级封装，空间的利用率得到有效提高，有利于进一步提高封装结构的集成度。此时，保护层70的材料可以是硅化物等具有耐高温性和密封性的材料，一方面，可以阻挡包封层10注塑成型工艺时的高温，对柔性基板71具有较好的保护作用，另一方面，可以有效防止外部的水氧影响封装结构的性能。
柔性基板71的材料可以是聚酰亚胺、聚丙烯树脂或亚克力树脂中的任一者，以使封装结构具有一定的柔性，但本实施例对此并不作具体限制。
在一些可选的实施例中，请结合参考图1和图10所示，多个裸芯片 40包括至少一个第一裸芯片41和至少一个第二裸芯片42；沿垂直于裸芯片40所在平面的方向上，第一裸芯片41的高度为d1，第二裸芯片42的高度为d2；其中，d1≠d2；
设置于第一裸芯片41上的连接柱50为第一连接柱51，设置于第二裸芯片42上的连接柱50为第二连接柱52；第一连接柱51靠近重布线层20 一侧的表面和第二连接柱52靠近重布线层20一侧的表面齐平设置。
本实施例中，第一裸芯片41和第二裸芯片42沿垂直于裸芯片40所在平面方向上的高度可以不相同，以第一裸芯片41的高度d1小于第二裸芯片42的高度d2为例，在第一连接柱51的高度也较小的情况下，第一裸芯片41可以完全被包封层10所覆盖；当然，通过合理设置第一连接柱51的高度，也可以使得第一裸芯片41远离重布线层20一侧的表面和第二裸芯片42远离重布线层20一侧的表面齐平，但本实施例对此并不作具体限制，也即多个裸芯片40之间的高度可以不完全相同，有利于适应多种尺寸芯片封装需求，适用范围更广。
第一连接柱51靠近重布线层20一侧的表面和第二连接柱52靠近重布线层20一侧的表面齐平设置，由于包封层10暴露出连接柱50远离裸芯片 40一侧的表面，从而在形成重布线层20时，各重布线路可以直接和第一连接柱51、第二连接柱52电连接，能够有效提高封装结构内线路连接的可靠性。包封层10暴露出连接柱50表面的方式可以有多种，比如研磨、刻蚀等等，本实施例对此并不作具体限制。
可选的，请继续参考图10所示，沿垂直于裸芯片40所在平面的方向上，第一连接柱51和第二连接柱52的高度相同，从而无论是为高度相同的裸芯片40还是为图10中高度不同的第一裸芯片41和第二裸芯片42配置连接柱50，裸芯片40之间可以共用相同规格的连接柱50，有利于降低封装结构的生产成本。
本发明提供了一种芯片封装结构的封装方法，请结合参考图1、图2、图11至图17所示，包括：
步骤101、提供一衬底基板80；
步骤102、提供多个裸芯片40，并将裸芯片40贴附在衬底基板80上；裸芯片40的一侧设置有多个连接柱50；
步骤103、形成包封层10，包封层10覆盖裸芯片40和连接柱50；
步骤104、对包封层10进行研磨，暴露出连接柱50远离裸芯片40一侧的表面；
步骤105、在连接柱50远离裸芯片40的一侧形成重布线层20，重布线层20包括第一重布线路21、第二重布线路22和第三重布线路23；其中，第一重布线路21、第二重布线路22分别和至少一个连接柱50电连接，剩余的连接柱50和第三重布线路23电连接；
步骤106、在重布线层20远离包封层10的一侧形成焊盘组30，焊盘组30包括输入焊盘31和输出焊盘32；其中，输入焊盘31和第一重布线路21电连接，输出焊盘32和第二重布线路22电连接；或者，输入焊盘 31和第二重布线路22电连接，输出焊盘32和第一重布线路21电连接；
步骤107、将衬底基板80剥离。
本实施例中，衬底基板80的作用主要是对所形成的封装结构起到一定的临时支撑作用，该衬底基板80可以是玻璃基板、硅基板或其他材料的基板，本实施例对此并不作具体限制。
将多个裸芯片40贴附于衬底基板80上时，为了确保各裸芯片40能够在衬底基板80上精确对位，可以预先在衬底基板80上设置一些对位块或对位标记等等。后续对衬底基板80进行剥离操作时，可以采用化学剥离或激光剥离等方式进行，但本实施例对此并不作具体限制。
重布线层20可以通过先形成金属种子层、再电镀金属形成各重布线路的图案的方式形成，金属种子层可以为后续形成的重布线层20提供良好的导电作用；也可以通过先沉积金属层、再对金属层进行刻蚀的方式形成，本实施例对此并不作具体限制，但为了降低生产成本，通常采用前者的方式形成重布线层20。由于重布线层20内的各重布线路需要和连接柱50电连接，故需要在形成重布线层20之间对包封层10进行研磨处理，暴露出连接柱50远离裸芯片40一侧的表面，以增加连接柱50和重布线路之间的连接强度。当然，研磨处理也可以用刻蚀等处理方式替代，本实施例对此也不作具体限制。
形成重布线层20时，重布线层20可以为单层布线结构，比如图1和图2所示；在线路排布较为复杂的情况下，重布线层20也可以为双层或多层结构，比如图3和图4中，各重布线路和相应的连接线路电连接，通过连接线路使得重布线层20的线路排布更加灵活方便。
由于焊盘组30也为金属材料，故可以采用和重布线层20相同的工艺形成，具体可以参考上述对重布线层20的阐述，本实施例在此不再赘述。
第一重布线路21、第二重布线路22分别和至少一个连接柱50电连接，剩余的连接柱50和第三重布线路23电连接，也即除用于信号输入和输出的连接柱50外，剩余的连接柱50之间可以直接通过第三重布线路23进行线路的排布，可以无需通过焊盘组30引出，从而使可以通过一个封装结构实现多个裸芯片40封装在一起的装配结构，集成度更高，能够有效适应电子产品的小型化趋势，有利于提高电子产品的生产效率；同时，由于省去了植球工艺，使用更加方便，成本更低，封装结构的可靠性和良率也更高。
可选的，请结合参考图5、图6、图18和图19所示，在步骤106形成焊盘组30时，焊盘组30还包括连接焊盘33；
在步骤107将衬底基板80剥离之前或之后，还包括：
步骤108、提供至少一个电子器件60，电子器件60包括器件本体61 以及设置于器件本体61上的多个引脚62；
步骤109、将引脚62和连接焊盘33电连接。
本实施例中，电子器件60的安装操作可以在衬底基板80剥离之前进行，或者也可以在衬底基板80剥离之后进行，本实施例对此并不作具体限制，仅以后者为例进行说明。一方面，外接电子器件60有利于提高封装结构中线路排布的灵活性，以适应多种使用需求；另一方面，在进行封装过程中，对于尺寸较大的电子器件60，如将其与裸芯片40一同进行封装，很可能会增加封装结构的尺寸，导致封装结构的集成度难以得到提高，而通过采用将这些电子器件60外接的方式和封装结构电连接，能够有效确保封装结构的集成度；当然，这些电子器件60也可以是尺寸较小，但需要根据实际情况选择性设置的器件，本实施例对此并不作具体限制。
需要说明的是，为了更加直观地示意本实施例的技术方案，图19中仅以重布线层20为双层或多层布线结构为例进行了示意。
可选的，请继续参考图6所示，步骤109将引脚62和连接焊盘33电连接包括：将引脚62采用焊接的方式和连接焊盘33电连接。
本实施例中，引脚62采用焊接的方式和连接焊盘33电连接，能够有效确保连接的稳定性和牢固性；需要拆除电子器件60时，只需熔化焊料 63即可，拆装操作简单方便，劳动强度低。
可选的，请结合参考图5、图7、图20-图24所示，在步骤103形成包封层之前，还包括：
步骤110、在衬底基板80上贴附多个限位柱12；
同时，在步骤109将引脚62和连接焊盘33电连接之前，还包括：
步骤111、利用激光工艺穿透限位柱12，形成容置腔11；
步骤112、将引脚62贯穿连接焊盘33后容置于容置腔11内。
本实施例中，采用激光工艺穿透限位柱12，以形成可以容置电子器件 60引脚62的容置腔11，使得引脚62长度较大的电子器件60能够较好地适应安装需求。由于引脚62贯穿了连接焊盘33，因此在安装电子器件60 之前，还需要在连接焊盘33上预设和容置腔11连通的安装孔13，此时位于连接焊盘22和限位柱12之间的膜层也应据此预设和容置腔11连通的安装孔13，安装孔13可以和容置腔11一样采用激光工艺形成，或者也可以采用刻蚀等工艺形成。
为了便于形成容置腔11，限位柱12应采用容易被激光穿透的材料制成，比如金属、聚酰亚胺或一些容易被激光击穿的无机非金属材料等等。优选的，限位柱12可以为空心结构，比如空心铜柱，此时安装孔13和空心铜柱可以一同采用激光穿透，且激光射至空心铜柱上时，由于空心铜柱为中空结构，激光很容易穿透空心铜柱的顶部，形成容置腔，有利于降低激光工艺所需的能耗，并且穿孔精度也更高。
需要说明的是，虽然包封层10为EMC材料时激光不容易穿透该膜层，但可以通过刻蚀等其他工艺形成图7所示的容置腔11，本实施例仅以采用限位柱12形成容置腔11为例进行了说明。
可选的，请结合参考图1、图8和图25所示，在步骤107将衬底基板 80剥离之后，还包括：
步骤113、在包封层10、裸芯片40远离重布线层20的一侧形成保护层70。
本实施例中，通过步骤113所形成的保护层70，可以和包封层10共同对裸芯片40进行保护，能够有效防止外界环境对裸芯片40的电学性能产生影响。此时，保护层70的材料可以和包封层10一样，比如两者均为 EMC，此时保护层70和包封层10可以均采用注塑工艺成型，有利于减少封装工序，提高电子产品的生产效率。当然，保护层70的材料也可以为其他，本实施例对此并不作具体限制。
可选的，请结合参考图1、图9、图26-图29所示，在步骤102提供至少一个裸芯片40之前，还包括：
步骤114、在衬底基板80上形成柔性基板71；
步骤115、在柔性基板71上形成保护层70；
在步骤102提供至少一个裸芯片40之后，将裸芯片40贴附在保护层 70上。
本实施例中，保护层70和柔性基板71在贴附裸芯片40之前形成，衬底基板80从柔性基板71上剥离即可，能够有效防止衬底基板80剥离过程中对裸芯片40造成伤害，有利于确保裸芯片40的电学特性。同时，封装结构以柔性基板71为基底实现面板级封装，去除衬底基板80时更容易，空间的利用率也能得到有效提高，有利于进一步提高封装结构的集成度。此时，保护层70的材料可以是硅化物等具有耐高温性和密封性的材料，一方面，可以阻挡包封层10注塑成型工艺时的高温，对柔性基板71具有较好的保护作用，另一方面，可以有效防止外部的水氧影响封装结构的性能。
步骤102之后的封装流程可以参考上述实施例的阐述，本实施例在此不再赘述。
此外，本发明还提供了另一种芯片封装结构的封装方法，请结合参考图1、图2、图12、图30-图35所示，包括：
步骤201、提供一衬底基板80；
步骤202、在衬底基板80上形成焊盘组30，焊盘组30包括输入焊盘 31和输出焊盘32；
步骤203、在焊盘组30远离玻璃基板80的一侧形成重布线层20，重布线层20包括第一重布线路21、第二重布线路22和第三重布线路23；其中，第一重布线路21和输入焊盘31电连接，第二重布线路22和输出焊盘 32电连接；或者，第二重布线路22和输入焊盘31电连接，第一重布线路 21和输出焊盘32电连接；
步骤204、提供多个裸芯片40，裸芯片40的一侧设置有多个连接柱 50；其中，第一重布线路21、第二重布线路22分别和至少一个连接柱50 电连接，剩余的连接柱50和第三重布线23电连接；
步骤205、形成包封层10，包封层10覆盖裸芯片40和连接柱50；
步骤206、将衬底基板80剥离，暴露出焊盘组30的表面。
相较于图11所示的封装方法，本实施例通过先形成焊盘组30和重布线层20、再安装裸芯片40的方式对封装结构进行封装，两种封装方法的区别在于安装裸芯片40的先后顺序，至于焊盘组30、重布线层20等膜层的形成方式，可以同图11所示封装方法的阐述，本实施例在此不再赘述。
需要说明的是，由于本实施例对膜层形成的先后顺序进行了调整，对应焊盘组30和重布线层20之间的绝缘层以及位于重布线层20和连接柱 50之间的绝缘层可以采用图35所示的过孔方式实现两膜层之间的电连接，当然也可以采用图2所示的过孔方式实现两膜层之间的电连接，本实施例对此并不作具体限制。
可选的，请结合参考图5、图6、图19和图36所示，在步骤202形成焊盘组30是，焊盘组还包括连接焊盘；
在步骤206将衬底基板80剥离之后，还包括：
步骤207、提供至少一个电子器件60，电子器件60包括器件本体61 以及设置于器件本体61上的多个引脚62；
步骤208、将引脚62和连接焊盘33电连接。
本实施例中，由于采用先形成焊盘组30和重布线层20、再安装裸芯片40的方式对封装结构进行封装，故电子器件60的安装操作需要在衬底基板80剥离之后进行，步骤207和步骤208的安装过程可以同图18所示的封装方法中对应电子器件60安装过程的阐述，本实施例在此不再赘述。
可选的，请结合参考图5、图7、图22-图24以及图37所示，在步骤 205形成包封层10之前，还包括：
步骤209、在重布线层20远离焊盘组30的一侧贴附多个限位柱12；
同时，在步骤208将引脚62和连接焊盘33电连接之前，还包括：
步骤210、利用激光工艺穿透限位柱12，形成容置腔11；
步骤211、将引脚62贯穿连接焊盘33后容置于容置腔11内。
相较于图20所示的封装方法，本实施例通过先形成焊盘组30和重布线层20、再安装裸芯片40的方式对封装结构进行封装，由于限位柱12需要在形成包封层10之前贴附，故在本实施例中，限位柱12贴附在重布线层20远离焊盘组30一侧的绝缘层表面即可，至于步骤210和步骤211的安装过程可以同图20所示的封装方法中对应电子器件60安装过程的阐述，本实施例在此不再赘述。
通过上述实施例可知，本发明提供的芯片封装结构及其封装方法，至少实现了如下的有益效果：
采用扇出型封装方式对多个裸芯片进行集中封装，裸芯片之间通过重布线层进行信号传输，重布线层可以根据需要设置为单层或多层线路结构，能够有效减小线路所占的空间，有利于提高封装结构的集成度，降低电子产品的能耗。裸芯片上用于外接信号的连接柱通过焊盘组引出，剩余的连接柱通过第三重布线路在封装结构的内部进行连接，也即可以通过一个封装结构代替现有技术中每个芯片单独封装后和PCB板装配的结构，封装结构更加简单，由于省去了植球步骤，使得封装结构的制作和使用也更加方便，有利于降低电子产品的生产成本，并提高电子产品的良率和生产效率。
虽然已经通过例子对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上例子仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (16)

1.一种芯片封装结构，其特征在于，包括：包封层、重布线层、焊盘组以及多个裸芯片；
所述裸芯片的一侧设置有多个连接柱；
所述包封层覆盖所述裸芯片和所述连接柱，且暴露出所述连接柱远离所述裸芯片一侧的表面；
所述重布线层位于所述连接柱远离所述裸芯片的一侧，且所述重布线层包括第一重布线路、第二重布线路和第三重布线路；
所述第一重布线路、所述第二重布线路分别和至少一个所述连接柱电连接，剩余的所述连接柱和所述第三重布线路电连接；
所述焊盘组位于所述重布线层远离所述包封层的一侧，且所述焊盘组包括输入焊盘和输出焊盘；
所述输入焊盘和所述第一重布线路电连接，所述输出焊盘和所述第二重布线路电连接；或者，所述输入焊盘和所述第二重布线路电连接，所述输出焊盘和所述第一重布线路电连接；
所述焊盘组还包括连接焊盘，所述封装结构还包括至少一个电子器件，所述电子器件包括器件本体以及设置于所述器件本体上的多个引脚，所述引脚和所述连接焊盘电连接；
所述包封层包括多个容置腔；所述引脚贯穿所述连接焊盘后容置于所述容置腔内。
2.根据权利要求1所述的芯片封装结构，其特征在于，
所述连接焊盘和所述重布线层电连接。
3.根据权利要求1所述的芯片封装结构，其特征在于，
所述包封层远离所述重布线层一侧的表面为第一表面；
沿垂直于所述裸芯片所在平面的方向上，所述容置腔和所述第一表面之间的间距为h；其中，h≥0。
4.根据权利要求2所述的芯片封装结构，其特征在于，
所述引脚通过焊料和所述连接焊盘电连接。
5.根据权利要求2所述的芯片封装结构，其特征在于，
所述电子器件为电阻、电容、电感、二极管中的任一者。
6.根据权利要求1所述的芯片封装结构，其特征在于，
所述封装结构还包括保护层；
所述保护层位于所述包封层、所述裸芯片远离所述重布线层的一侧。
7.根据权利要求6所述的芯片封装结构，其特征在于，
所述封装结构还包括柔性基板；
所述柔性基板位于所述保护层远离所述重布线层的一侧。
8.根据权利要求1所述的芯片封装结构，其特征在于，
所述多个裸芯片包括至少一个第一裸芯片和至少一个第二裸芯片；
沿垂直于所述裸芯片所在平面的方向上，所述第一裸芯片的高度为d1，所述第二裸芯片的高度为d2；其中，d1≠d2；
设置于所述第一裸芯片上的所述连接柱为第一连接柱，设置于所述第二裸芯片上的所述连接柱为第二连接柱；
所述第一连接柱靠近所述重布线层一侧的表面和所述第二连接柱靠近所述重布线层一侧的表面齐平设置。
9.根据权利要求8所述的芯片封装结构，其特征在于，
沿垂直于所述裸芯片所在平面的方向上，所述第一连接柱和所述第二连接柱的高度相同。
10.一种芯片封装结构的封装方法，其特征在于，包括：
提供一衬底基板；
提供多个裸芯片，并将所述裸芯片贴附在所述衬底基板上；所述裸芯片的一侧设置有多个连接柱；
形成包封层，所述包封层覆盖所述裸芯片和所述连接柱；
对所述包封层进行研磨，暴露出所述连接柱远离所述裸芯片一侧的表面；
在所述连接柱远离所述裸芯片的一侧形成重布线层，所述重布线层包括第一重布线路、第二重布线路和第三重布线路；其中，所述第一重布线路、所述第二重布线路分别和至少一个所述连接柱电连接，剩余的所述连接柱和所述第三重布线路电连接；
在所述重布线层远离所述包封层的一侧形成焊盘组，所述焊盘组包括输入焊盘和输出焊盘；其中，所述输入焊盘和所述第一重布线路电连接，所述输出焊盘和所述第二重布线路电连接；或者，所述输入焊盘和所述第二重布线路电连接，所述输出焊盘和所述第一重布线路电连接；
将所述衬底基板剥离；
所述焊盘组还包括连接焊盘；所述将所述衬底基板剥离之前或之后，还包括：
提供至少一个电子器件，所述电子器件包括器件本体以及设置于所述器件本体上的多个引脚，将所述引脚和所述连接焊盘电连接；
所述将所述引脚和所述连接焊盘电连接之前，还包括：
利用激光工艺穿透限位柱，形成容置腔；
将所述引脚贯穿所述连接焊盘后容置于所述容置腔内。
11.根据权利要求10所述的封装方法，其特征在于，
所述形成包封层之前，还包括：
在所述衬底基板上贴附多个所述限位柱。
12.根据权利要求10所述的封装方法，其特征在于，
所述将所述引脚和所述连接焊盘电连接包括：
将所述引脚采用焊接的方式和所述连接焊盘电连接。
13.根据权利要求10所述的封装方法，其特征在于，
所述将所述衬底基板剥离之后，还包括：
在所述包封层、所述裸芯片远离所述重布线层的一侧形成保护层。
14.根据权利要求10所述的封装方法，其特征在于，
所述提供多个裸芯片之前，还包括：
在所述衬底基板上形成柔性基板；
在所述柔性基板上形成保护层；
所述提供至少一个裸芯片之后，将所述裸芯片贴附在所述保护层上。
15.一种芯片封装结构的封装方法，其特征在于，包括：
提供一衬底基板；
在所述衬底基板上形成焊盘组，所述焊盘组包括输入焊盘和输出焊盘；
在所述焊盘组远离所述衬底基板的一侧形成重布线层，所述重布线层包括第一重布线路、第二重布线路和第三重布线路；其中，所述第一重布线路和所述输入焊盘电连接，所述第二重布线路和所述输出焊盘电连接；或者，所述第二重布线路和所述输入焊盘电连接，所述第一重布线路和所述输出焊盘电连接；
提供多个裸芯片，所述裸芯片的一侧设置有多个连接柱；其中，所述第一重布线路、所述第二重布线路分别和至少一个所述连接柱电连接，剩余的所述连接柱和所述第三重布线电连接；
形成包封层，所述包封层覆盖所述裸芯片和所述连接柱；
将所述衬底基板剥离，暴露出所述焊盘组的表面；
所述焊盘组还包括连接焊盘；
所述将所述衬底基板剥离之后，还包括：
提供至少一个电子器件，所述电子器件包括器件本体以及设置于所述器件本体上的多个引脚，将所述引脚和所述连接焊盘电连接；
所述将所述引脚和所述连接焊盘电连接之前，还包括：
利用激光工艺穿透限位柱，形成容置腔；
将所述引脚贯穿所述连接焊盘后容置于所述容置腔内。
16.根据权利要求15所述的封装方法，其特征在于，
所述形成包封层之前，还包括：
在所述重布线层远离所述焊盘组的一侧贴附多个所述限位柱。
CN201910251627.7A 2019-03-29 2019-03-29 芯片封装结构及其封装方法 Active CN109994438B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201910251627.7A CN109994438B (zh) 2019-03-29 2019-03-29 芯片封装结构及其封装方法
US16/441,501 US11257765B2 (en) 2019-03-29 2019-06-14 Chip package structure including connecting posts and chip package method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910251627.7A CN109994438B (zh) 2019-03-29 2019-03-29 芯片封装结构及其封装方法

Publications (2)

Publication Number Publication Date
CN109994438A CN109994438A (zh) 2019-07-09
CN109994438B true CN109994438B (zh) 2021-04-02

Family

ID=67131953

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910251627.7A Active CN109994438B (zh) 2019-03-29 2019-03-29 芯片封装结构及其封装方法

Country Status (2)

Country Link
US (1) US11257765B2 (zh)
CN (1) CN109994438B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
CN110197823B (zh) * 2019-04-09 2021-12-17 上海中航光电子有限公司 面板级芯片装置及其封装方法
CN111554641A (zh) * 2020-05-11 2020-08-18 上海天马微电子有限公司 半导体封装件及其制作方法
CN113380772B (zh) * 2021-06-07 2022-07-19 华进半导体封装先导技术研发中心有限公司 一种芯片封装结构及其封装方法
CN116484796A (zh) * 2022-01-13 2023-07-25 长鑫存储技术有限公司 一种芯片封装结构及存储系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
US20170110441A1 (en) * 2015-10-15 2017-04-20 Silergy Semiconductor Technology (Hangzhou) Ltd Stacked package structure and stacked packaging method for chip
CN107068669A (zh) * 2016-02-10 2017-08-18 台湾积体电路制造股份有限公司 半导体装置封装以及半导体封装及其制造方法
CN109216324A (zh) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 具有用于减少串扰的屏蔽结构的半导体器件

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7388294B2 (en) * 2003-01-27 2008-06-17 Micron Technology, Inc. Semiconductor components having stacked dice
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
US8384199B2 (en) * 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US8592992B2 (en) * 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US9111949B2 (en) * 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US8878360B2 (en) * 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US9177925B2 (en) * 2013-04-18 2015-11-03 Fairfchild Semiconductor Corporation Apparatus related to an improved package including a semiconductor die
US9362234B2 (en) * 2014-01-07 2016-06-07 Freescale Semiconductor, Inc. Shielded device packages having antennas and related fabrication methods
US9252135B2 (en) * 2014-02-13 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US10971476B2 (en) * 2014-02-18 2021-04-06 Qualcomm Incorporated Bottom package with metal post interconnections
TW201539596A (zh) * 2014-04-09 2015-10-16 Tong Hsing Electronic Ind Ltd 中介體及其製造方法
CN105097564B (zh) * 2014-05-12 2018-03-30 中芯国际集成电路制造(上海)有限公司 芯片封装结构的处理方法
US9691743B2 (en) * 2015-09-21 2017-06-27 Nxp Usa, Inc. Localized redistribution layer structure for embedded component package and method
CN109087908B (zh) 2015-12-31 2020-10-27 华为技术有限公司 封装结构、电子设备及封装方法
US10032722B2 (en) * 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9825007B1 (en) * 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
KR102491103B1 (ko) * 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10818635B2 (en) * 2018-04-23 2020-10-27 Deca Technologies Inc. Fully molded semiconductor package for power devices and method of making the same
US20200211980A1 (en) * 2018-12-27 2020-07-02 Powertech Technology Inc. Fan-out package with warpage reduction and manufacturing method thereof
CN110197823B (zh) * 2019-04-09 2021-12-17 上海中航光电子有限公司 面板级芯片装置及其封装方法
KR102494920B1 (ko) * 2019-05-21 2023-02-02 삼성전자주식회사 반도체 패키지
US11862546B2 (en) * 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170110441A1 (en) * 2015-10-15 2017-04-20 Silergy Semiconductor Technology (Hangzhou) Ltd Stacked package structure and stacked packaging method for chip
CN107068669A (zh) * 2016-02-10 2017-08-18 台湾积体电路制造股份有限公司 半导体装置封装以及半导体封装及其制造方法
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
CN109216324A (zh) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 具有用于减少串扰的屏蔽结构的半导体器件

Also Published As

Publication number Publication date
CN109994438A (zh) 2019-07-09
US20200312772A1 (en) 2020-10-01
US11257765B2 (en) 2022-02-22

Similar Documents

Publication Publication Date Title
CN109994438B (zh) 芯片封装结构及其封装方法
US11133242B2 (en) Method of manufacturing semiconductor devices, corresponding device and circuit
US10354984B2 (en) Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same
EP2798675B1 (en) Method for a substrate core layer
US7185426B1 (en) Method of manufacturing a semiconductor package
US8623753B1 (en) Stackable protruding via package and method
US20090134528A1 (en) Semiconductor package, electronic device including the semiconductor package, and method of manufacturing the semiconductor package
EP2988325A2 (en) Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
KR101145041B1 (ko) 반도체칩 패키지, 반도체 모듈 및 그 제조 방법
US20010054756A1 (en) Multi-layered semiconductor device and method for producing the same
EP3147942B1 (en) Semiconductor package, semiconductor device using the same and manufacturing method thereof
TWI461124B (zh) 層疊封裝結構及其製作方法
US9202742B1 (en) Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof
US9462704B1 (en) Extended landing pad substrate package structure and method
US20140048313A1 (en) Thermally enhanced wiring board with thermal pad and electrical post
US11646272B2 (en) Packaging method of panel-level chip device
US5882957A (en) Ball grid array packaging method for an integrated circuit and structure realized by the method
CN111933590B (zh) 封装结构和封装结构制作方法
US20100019374A1 (en) Ball grid array package
KR20140083084A (ko) 전자파 차폐층을 갖는 반도체 패키지 및 그 제조방법
US11205602B2 (en) Semiconductor device and manufacturing method thereof
CN103681359A (zh) 层叠封装结构及其制作方法
JP3781998B2 (ja) 積層型半導体装置の製造方法
US11502054B2 (en) Semiconductor device assembly and method therefor
KR20190058411A (ko) 인쇄회로기판을 이용한 반도체 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant