CN105097564B - 芯片封装结构的处理方法 - Google Patents

芯片封装结构的处理方法 Download PDF

Info

Publication number
CN105097564B
CN105097564B CN201410198249.8A CN201410198249A CN105097564B CN 105097564 B CN105097564 B CN 105097564B CN 201410198249 A CN201410198249 A CN 201410198249A CN 105097564 B CN105097564 B CN 105097564B
Authority
CN
China
Prior art keywords
electric connection
connection structure
processing method
pad
bombardment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410198249.8A
Other languages
English (en)
Other versions
CN105097564A (zh
Inventor
王奇峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201410198249.8A priority Critical patent/CN105097564B/zh
Priority to US14/681,234 priority patent/US9431215B2/en
Publication of CN105097564A publication Critical patent/CN105097564A/zh
Priority to US15/221,856 priority patent/US9698113B2/en
Application granted granted Critical
Publication of CN105097564B publication Critical patent/CN105097564B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81022—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/07—Polyamine or polyimide
    • H01L2924/07025—Polyimide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种芯片封装结构的处理方法。本发明采用O2或N2中的至少一种气体的等离子体轰击第一电连接结构、第二电连接结构及暴露所述第一电连接结构、第二电连接结构的绝缘层。上述轰击过程中，O2或N2所产生的等离子体会与沉积在绝缘层表面的金属阳离子反应生成金属原子或金属化合物，上述金属原子、金属化合物为电中性，因而与绝缘层之间无静电吸附，易于脱离绝缘层表面，且上述金属原子、金属化合物也不易反粘至绝缘层表面，对等离子体腔室抽真空即可将上述金属原子、金属化合物排出。

Description

芯片封装结构的处理方法
技术领域
本发明涉及半导体技术领域，特别涉及一种芯片封装结构的处理方法。
背景技术
现有的芯片封装结构在制作完成后，由于刻蚀工艺中等离子体的轰击、湿法清洗等，会造成金属阳离子在隔绝电连接结构，例如锡球的绝缘材料上沉积。上述沉积的金属阳离子会造成相邻两电连接结构之间电泄露，从而引起封装器件失效。
为解决上述技术问题，现有技术也有一些方案提出。例如采用Ar等离子体轰击上述绝缘层表面，使得绝缘层表层原子携带金属阳离子同时脱离绝缘层，之后抽真空将上述反应产物去除。
然而，实际工艺中发现，上述依赖轰击物理剥离金属阳离子的方式对金属阳离子的去除效果很有限，相邻电连接结构之间仍可能产生电泄露。
有鉴于此，本发明提供一种新的芯片封装结构的处理方法解决上述技术问题。
发明内容
本发明解决的问题是芯片封装结构的相邻电连接结构之间易出现电泄露。
为解决上述问题，本发明提供一种芯片封装结构的处理方法，芯片封装结构至少具有第一电连接结构、第二电连接结构及暴露所述第一电连接结构、第二电连接结构的绝缘层；
采用O2或N2中的至少一种气体的等离子体轰击所述第一电连接结构、第二电连接结构及暴露所述第一电连接结构、第二电连接结构的绝缘层。
可选地，所述第一电连接结构为焊垫或垫重分布层，所述第二电连接结构为焊垫或垫重分布层。
可选地，所述焊垫或垫重分布层的材质为铜或铝。
可选地，所述第一电连接结构为位于焊垫或垫重分布层上的焊球，所述第二电连接结构为位于焊垫或垫重分布层上的焊球。
可选地，所述焊球的材质为铜、锡或银。
可选地，所述第一电连接结构还包括位于所述焊球与焊垫，或所述焊球与垫重分布层之间的球下金属层；所述第二电连接结构还包括位于所述焊球与焊垫，或所述焊球与垫重分布层之间的球下金属层。
可选地，所述球下金属层的材质为钛或铜。
可选地，所述轰击过程中，等离子体腔室内O2的流量范围为5～25sccm，压强范围为1E10-9～1E10-6Pa。
可选地，所述轰击过程中，等离子体腔室内N2的流量范围为5～25sccm，压强范围为1E10-9～1E10-6Pa。
可选地，所述轰击过程中，所加的射频电压大小范围为900V～1100V，频率范围为45Hz～55Hz，功率范围为270W～330W，轰击时间范围为100s～150s。
可选地，所述绝缘层的材质为聚酰亚胺、氮化硅、或氧化硅。
与现有技术相比，本发明的技术方案具有以下优点：1)本发明采用O2或N2中的至少一种气体的等离子体轰击第一电连接结构、第二电连接结构及暴露所述第一电连接结构、第二电连接结构的绝缘层，上述轰击过程中，O2或N2所产生的等离子体会与沉积在绝缘层表面的金属阳离子反应生成金属原子或金属化合物，上述金属原子、金属化合物为电中性，因而与绝缘层之间无静电吸附，易于脱离绝缘层表面，且上述金属原子、金属化合物也不易反粘至绝缘层表面，对等离子体腔室抽真空即可将上述金属原子、金属化合物排出。
2)可选方案中，上述第一电连接结构与第二电连接结构具有多种方案，例如都为焊垫或垫重分布层，或都为焊球，或为焊球及其下的球下金属层。上述提供了多种芯片封装结构的表面结构，不论焊垫、垫重分布层、焊球、或焊球及其下的球下金属层在刻蚀及清洗过程中都有可能造成金属阳离子流失沉积在隔绝相邻上述结构的绝缘层上，对上述绝缘层及金属阳离子进行等离子体轰击，可以使金属阳离子与等离子体中的阴离子、原子或电子结合，变为电中性的金属原子、金属化合物，从而脱离绝缘层表面，避免相邻焊垫之间、相邻垫重分布层之间、相邻焊球之间、或相邻焊球及其下的球下金属层之间出现电泄露，提高了器件的可靠性。
3)可选方案中，所述轰击过程中，等离子体腔室内O2的流量范围为5～25sccm，压强范围为1E10-9～1E10-6Pa，上述压强范围有利于O2电离产生等离子体，5～25sccm流量范围所产生的电子和/或O原子利于与金属阳离子结合生成金属原子或金属化合物。
4)可选方案中，与3)可选方案类似地，所述轰击过程中，等离子体腔室内N2的流量范围为5～25sccm，压强范围为1E10-9～1E10-6Pa，上述压强范围有利于N2电离产生等离子体，5～25sccm流量范围所产生的电子和/或N原子利于与金属阳离子结合生成金属原子或金属化合物。
5)可选方案中，对于4)可选方案中的O2与5)可选方案中的N2，所述轰击过程中，所加的射频电压大小范围为900V～1100V，频率范围为45Hz～55Hz，功率范围为270W～330W，轰击时间范围为100s～150s，上述射频电压大小、频率与功率利于对等离子加速，使其易于与金属阳离子结合，上述轰击时间既实现了金属阳离子电中和或生成金属化合物，又避免了等离子轰击在暴露的电连接结构表面造成缺陷。
附图说明
图1是本发明一个实施例的芯片封装结构在处理过程中的结构示意图；
图2是本发明另一实施例的芯片封装结构在处理过程中的结构示意图；
图3是本发明再一实施例的芯片封装结构在处理过程中的结构示意图。
具体实施方式
如背景技术中所述，现有技术中，为去除芯片封装结构绝缘层表面的金属阳离子，采用Ar轰击上述表面，以使得沉积金属阳离子的绝缘层部分表层原子被轰击脱离上述绝缘层，藉此实现将金属阳离子从绝缘层表面剥离。然而，上述处理方法对金属阳离子的去除效果很有限，相邻电连接结构之间仍存在电泄露。针对上述技术问题，本发明提出采用O2或N2中的至少一种气体的等离子体轰击第一电连接结构、第二电连接结构及暴露所述第一电连接结构、第二电连接结构的绝缘层，上述轰击过程中，O2或N2所产生的等离子体会与沉积在绝缘层表面的金属阳离子反应生成金属原子或金属化合物，上述金属原子、金属化合物为电中性，因而与绝缘层之间无静电吸附，易于脱离绝缘层表面，且上述金属原子、金属化合物也不易再反粘至绝缘层表面，对等离子体腔室抽真空即可将上述金属原子、金属化合物排出。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明一个实施例的芯片封装结构在处理过程中的结构示意图。参照图1所示，芯片封装结构1具有第一焊垫121、第二焊垫122及暴露所述第一焊垫121、第二焊垫122的绝缘层13。
具体地，第一焊垫121与第二焊垫122分别通过金属互连结构11与衬底上的器件，例如晶体管相连，第一焊垫121与第二焊垫122之间电绝缘。
第一焊垫121与第二焊垫122的材质为铝、铜等，通过干法刻蚀工艺形成，可以理解的是，刻蚀过程的副产物去除不干净，会引起铜阳离子、铝阳离子沉积在绝缘层13上。绝缘层13的材质例如为氧化硅。考虑到隔离水汽、污染物等因素，绝缘层13可以为钝化层，其材质可以为氮化硅。考虑到焊垫金属应力一般较大，可能会引起其下的金属互连结构中的介电层断裂，为避免上述问题，绝缘层13的材质可以为聚酰亚胺。
参照图1所示，对于芯片封装结构1，采用O2或N2中的至少一种气体的等离子体轰击所述第一焊垫121、第二焊垫122及暴露第一焊垫121、第二焊垫122的绝缘层13。
具体地，控制等离子体腔室内的氧气压强范围为1E10-9～1E10-6Pa，施加射频电压大小范围为900V～1100V，频率范围为45Hz～55Hz，功率范围为270W～330W，使得O2电离为氧原子O，电子e等。上述氧原子O，电子e与金属阳离子发生反应，以铜为例：
Cu2++O+2e→Cu+O
Cu2++O+2e→CuO
上述金属原子Cu、金属化合物CuO为电中性，因而与绝缘层13之间无静电吸附，易于脱离绝缘层13表面，且上述金属原子Cu、金属化合物CuO也不易再反粘至绝缘层13表面，对等离子体腔室抽真空即可将上述金属原子Cu、金属化合物CuO排出。
一个实施例中，O2流量范围为5～25sccm，上述流量范围所产生的电子和/或O原子利于与金属阳离子结合生成金属原子或金属化合物。一个实施例中，轰击时间为100s～150s，例如120s，上述轰击时间既实现了金属阳离子电中和或生成金属化合物，又避免了等离子轰击在暴露的焊垫电连接结构表面造成缺陷。
除了采用O2等离子体轰击芯片封装结构，还可以采用N2等离子体。具体地，控制等离子体腔室内的氮气压强范围为1E10-9～1E10-6Pa，射频电压大小范围为900V～1100V，频率范围为45Hz～55Hz，功率范围为270W～330W，使得N2电离为氮原子N，电子e等。上述氮原子N，电子e与金属阳离子发生反应，以铝为例：
Al3++N+3e→Al+N
Al3++N+3e→AlN
上述金属原子Al、金属化合物AlN为电中性，因而与绝缘层13之间无静电吸附，易于脱离绝缘层13表面，且上述金属原子Al、金属化合物AlN也不易反粘至绝缘层13表面，对等离子体腔室抽真空即可将上述金属原子Al、金属化合物AlN排出。
一个实施例中，N2流量范围为5～25sccm，上述流量范围所产生的电子和/或N原子利于与金属阳离子结合生成金属原子或金属化合物。一个实施例中，轰击时间为100s～150s，上述轰击时间既实现了金属阳离子电中和或生成金属化合物，又避免了等离子轰击在暴露的电连接结构表面造成缺陷。
可以理解的是，上述对芯片封装结构的处理方法，并不限于两个焊垫，其它实施例中，对具有多个焊垫的芯片封装结构也可以采用上述处理方法，以避免焊垫之间的电泄露，从而提高芯片封装结构的可靠性。另外，也可以采用O2与N2的混合气体所产生的等离子体对芯片封装结构进行处理。
图2是本发明另一个实施例的芯片封装结构在处理过程中的结构示意图。与图1中芯片结构的区别在于：上述处理的绝缘层13不是暴露出第一焊垫121、第二焊垫122，而是暴露出垫重分布层151、152。第一垫重分布层151通过金属互连结构14与第一焊垫121相连，第二垫重分布层152通过金属互连结构14与第二焊垫122相连，两垫重分布层151、152对两焊垫121、122进行了重分布。利用垫重分布层151、152对焊垫121、122之间的间距、位置进行重新规划，可以提高芯片封装结构上的器件密度。
第一垫重分布层151、第二垫重分布层152的材质也为铜或铝，两者之间电绝缘。即芯片封装结构制作完成后，沉积在绝缘层13上的金属阳离子也为铜阳离子或铝阳离子。
除了上述芯片封装结构不同，其余处理方法与图1中实施例的封装结构的处理方法相同。
图3是本发明再一个实施例的芯片封装结构在处理过程中的结构示意图。与图1中芯片结构的区别在于：上述处理的绝缘层13不是隔绝第一焊垫121、第二焊垫122，而是电绝缘分别与第一焊垫121、第二焊垫122相连的第一焊球171、第二焊球172。第一焊球171、第二焊球172的材质为铜、锡或银。即沉积在绝缘层13上的金属阳离子为铜离子、锡离子或银离子。O2或N2电离出的等离子体也能将锡离子与银离子电中和为锡原子与银原子，或与锡离子与银离子生成电中性的锡化合物或银化合物。
此外，参照图3所示，第一焊球171与第一焊垫121之间还具有第一球下金属层161，第二焊球172与第二焊垫122之间还具有第二球下金属层162。第一球下金属层161、第二球下金属层162的材质为钛或铜。即芯片封装结构制作完成后，沉积在绝缘层13上的金属阳离子除了为铜离子、锡离子或银离子外，还可能为钛离子。O2或N2电离出的等离子体也能将钛离子电中和为钛原子或与钛离子生成电中性的钛化合物。
除了上述芯片封装结构的不同，其余处理方法与图1中实施例的封装结构的处理方法相同。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (11)

1.一种芯片封装结构的处理方法，其特征在于，
芯片封装结构至少具有第一电连接结构、第二电连接结构及暴露所述第一电连接结构、第二电连接结构的绝缘层；
采用O2或N2中的至少一种气体的等离子体轰击所述第一电连接结构、第二电连接结构及暴露所述第一电连接结构、第二电连接结构的绝缘层；上述轰击过程中，O2或N2所产生的等离子体会与沉积在绝缘层表面的金属阳离子反应生成金属原子或金属化合物，所述金属原子、金属化合物为电中性，因而与绝缘层之间无静电吸附，且所述金属原子、金属化合物也不易再反粘至绝缘层表面。
2.根据权利要求1所述的处理方法，其特征在于，所述第一电连接结构为焊垫或垫重分布层，所述第二电连接结构为焊垫或垫重分布层。
3.根据权利要求2所述的处理方法，其特征在于，所述焊垫或垫重分布层的材质为铜或铝。
4.根据权利要求1所述的处理方法，其特征在于，所述第一电连接结构为位于焊垫或垫重分布层上的焊球，所述第二电连接结构为位于焊垫或垫重分布层上的焊球。
5.根据权利要求4所述的处理方法，其特征在于，所述焊球的材质为铜、锡或银。
6.根据权利要求4所述的处理方法，其特征在于，所述第一电连接结构还包括位于所述焊球与焊垫，或所述焊球与垫重分布层之间的球下金属层；所述第二电连接结构还包括位于所述焊球与焊垫，或所述焊球与垫重分布层之间的球下金属层。
7.根据权利要求6所述的处理方法，其特征在于，所述球下金属层的材质为钛或铜。
8.根据权利要求1所述的处理方法，其特征在于，所述轰击过程中，等离子体腔室内O2的流量范围为5～25sccm，压强范围为1E10-9～1E10-6Pa。
9.根据权利要求1所述的处理方法，其特征在于，所述轰击过程中，等离子 体腔室内N2的流量范围为5～25sccm，压强范围为1E10-9～1E10-6Pa。
10.根据权利要求8或9所述的处理方法，其特征在于，所述轰击过程中，所加的射频电压大小范围为900V～1100V，频率范围为45Hz～55Hz，功率范围为270W～330W，轰击时间范围为100s～150s。
11.根据权利要求1所述的处理方法，其特征在于，所述绝缘层的材质为聚酰亚胺、氮化硅、或氧化硅。
CN201410198249.8A 2014-05-12 2014-05-12 芯片封装结构的处理方法 Active CN105097564B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410198249.8A CN105097564B (zh) 2014-05-12 2014-05-12 芯片封装结构的处理方法
US14/681,234 US9431215B2 (en) 2014-05-12 2015-04-08 Chip packaging structures and treatment methods thereof
US15/221,856 US9698113B2 (en) 2014-05-12 2016-07-28 Chip packaging structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410198249.8A CN105097564B (zh) 2014-05-12 2014-05-12 芯片封装结构的处理方法

Publications (2)

Publication Number Publication Date
CN105097564A CN105097564A (zh) 2015-11-25
CN105097564B true CN105097564B (zh) 2018-03-30

Family

ID=54368512

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410198249.8A Active CN105097564B (zh) 2014-05-12 2014-05-12 芯片封装结构的处理方法

Country Status (2)

Country Link
US (2) US9431215B2 (zh)
CN (1) CN105097564B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941230B2 (en) * 2015-12-30 2018-04-10 International Business Machines Corporation Electrical connecting structure between a substrate and a semiconductor chip
CN108538735B (zh) * 2017-03-02 2020-05-29 中芯国际集成电路制造(上海)有限公司 金属凸块装置及其制造方法
CN109994438B (zh) * 2019-03-29 2021-04-02 上海中航光电子有限公司 芯片封装结构及其封装方法
KR20220025545A (ko) 2020-08-24 2022-03-03 삼성전자주식회사 신뢰성을 향상시킬 수 있는 반도체 패키지

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1464993A (zh) * 2001-06-29 2003-12-31 西铁城时计株式会社 液晶显示板及其制造方法
CN1926674A (zh) * 2003-07-31 2007-03-07 飞思卡尔半导体公司 具有减小应力的凸起设计的半导体器件
CN102651373A (zh) * 2011-02-23 2012-08-29 索尼公司 半导体器件的制造方法、半导体器件和电子装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6300234B1 (en) * 2000-06-26 2001-10-09 Motorola, Inc. Process for forming an electrical device
MY134318A (en) * 2003-04-02 2007-12-31 Freescale Semiconductor Inc Integrated circuit die having a copper contact and method therefor
JP5118300B2 (ja) * 2005-12-20 2013-01-16 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5324051B2 (ja) * 2007-03-29 2013-10-23 新光電気工業株式会社 配線基板の製造方法及び半導体装置の製造方法及び配線基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1464993A (zh) * 2001-06-29 2003-12-31 西铁城时计株式会社 液晶显示板及其制造方法
CN1926674A (zh) * 2003-07-31 2007-03-07 飞思卡尔半导体公司 具有减小应力的凸起设计的半导体器件
CN102651373A (zh) * 2011-02-23 2012-08-29 索尼公司 半导体器件的制造方法、半导体器件和电子装置

Also Published As

Publication number Publication date
CN105097564A (zh) 2015-11-25
US20160336285A1 (en) 2016-11-17
US20150325544A1 (en) 2015-11-12
US9698113B2 (en) 2017-07-04
US9431215B2 (en) 2016-08-30

Similar Documents

Publication Publication Date Title
CN105097564B (zh) 芯片封装结构的处理方法
US10553508B2 (en) Semiconductor manufacturing using disposable test circuitry within scribe lanes
US10312197B2 (en) Method of manufacturing semiconductor device and semiconductor device
TWI621238B (zh) 半導體裝置及其製造方法
CN104979334A (zh) 半导体器件及方法
US9780021B2 (en) Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and electronic component-mounted structure
JP6066569B2 (ja) 半導体デバイスパッケージング用のパッシベーション層
US10053361B2 (en) Method of selectively removing an anti-stiction layer on a eutectic bonding area
US9953906B2 (en) Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and electronic component-mounted structure
JP4548280B2 (ja) 半導体装置の製造方法
TW201128721A (en) Manufacturing method of semiconductor device
US20170256432A1 (en) Overmolded chip scale package
US9786521B2 (en) Chip package method for reducing chip leakage current
US9698052B2 (en) Method of manufacturing element chip and method of manufacturing electronic component-mounted structure using plasma etch to singulate element chip
TW201732908A (zh) 晶圓接合之設備及方法
JP6492286B2 (ja) 素子チップの製造方法
CN104835748B (zh) 一种提高半导体器件键合可靠性的方法
CN105206598B (zh) 半导体器件及其形成方法
CN104733328B (zh) 晶圆级芯片封装方法
US11081463B2 (en) Bonding method with electron-stimulated desorption
JP5120004B2 (ja) 基板の表面処理方法および半導体パッケージの製造方法
JP2010263137A (ja) 半導体装置及びその製造方法
CN105448643B (zh) 晶圆的处理方法
JPS58158952A (ja) 半導体装置及びその製造法
CN106716606A (zh) 用于氧化等离子体后处理以减少光刻中毒的技术及相关结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant